x86: don't ignore mandatory pseudo prefixes
{vex}, {vex3}, and {evex} are mandatory prefixes, and hence should not be randomly ignored. Fix this for insns without operands as well as for insns referencing the high 16 [XYZ]MM registers. To achieve the former, re-purpose VEX_check_operands(), renaming it to VEX_check_encoding() and moving its only operand check to check_VecOperands(). This involves fixing a testcase relying on {vex2} to get ignored.
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@ -1,3 +1,18 @@
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2020-06-09 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (vex_encoding_error): New enumerator.
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(VEX_check_operands): Rename to VEX_check_encoding. Check
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for vex_encoding_error. Move Imm4 handling ...
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(check_VecOperands): ... here.
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(match_template): Call VEX_check_encoding when there are no
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operands. Split construct calling check_VecOperands and
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VEX_check_encoding (when there are operands).
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(check_register): Don't blindly set vex_encoding_evex.
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* testsuite/gas/i386/pseudos-bad.s,
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testsuite/gas/i386/pseudos-bad.l: New.
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* testsuite/gas/i386/i386.exp: Run new test.
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* testsuite/gas/i386/xmmhi64.s: Drop {vex2}.
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2020-06-08 Alex Coplan <alex.coplan@arm.com>
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* config/tc-arm.c (insns): Add dfb.
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@ -424,7 +424,8 @@ struct _i386_insn
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vex_encoding_default = 0,
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vex_encoding_vex,
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vex_encoding_vex3,
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vex_encoding_evex
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vex_encoding_evex,
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vex_encoding_error
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} vec_encoding;
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/* REP prefix. */
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@ -5999,6 +6000,20 @@ check_VecOperands (const insn_template *t)
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}
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}
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/* Check the special Imm4 cases; must be the first operand. */
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if (t->cpu_flags.bitfield.cpuxop && t->operands == 5)
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{
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if (i.op[0].imms->X_op != O_constant
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|| !fits_in_imm4 (i.op[0].imms->X_add_number))
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{
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i.error = bad_imm4;
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return 1;
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}
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/* Turn off Imm<N> so that update_imm won't complain. */
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operand_type_set (&i.types[0], 0);
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}
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/* Check vector Disp8 operand. */
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if (t->opcode_modifier.disp8memshift
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&& i.disp_encoding != disp_encoding_32bit)
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@ -6068,12 +6083,17 @@ check_VecOperands (const insn_template *t)
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return 0;
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}
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/* Check if operands are valid for the instruction. Update VEX
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operand types. */
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/* Check if encoding requirements are met by the instruction. */
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static int
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VEX_check_operands (const insn_template *t)
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VEX_check_encoding (const insn_template *t)
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{
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if (i.vec_encoding == vex_encoding_error)
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{
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i.error = unsupported;
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return 1;
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}
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if (i.vec_encoding == vex_encoding_evex)
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{
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/* This instruction must be encoded with EVEX prefix. */
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@ -6096,20 +6116,6 @@ VEX_check_operands (const insn_template *t)
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return 0;
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}
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/* Check the special Imm4 cases; must be the first operand. */
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if (t->cpu_flags.bitfield.cpuxop && t->operands == 5)
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{
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if (i.op[0].imms->X_op != O_constant
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|| !fits_in_imm4 (i.op[0].imms->X_add_number))
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{
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i.error = bad_imm4;
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return 1;
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}
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/* Turn off Imm<N> so that update_imm won't complain. */
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operand_type_set (&i.types[0], 0);
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}
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return 0;
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}
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@ -6265,8 +6271,16 @@ match_template (char mnem_suffix)
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/* Do not verify operands when there are none. */
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if (!t->operands)
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/* We've found a match; break out of loop. */
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break;
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{
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if (VEX_check_encoding (t))
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{
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specific_error = i.error;
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continue;
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}
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/* We've found a match; break out of loop. */
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break;
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}
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if (!t->opcode_modifier.jump
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|| t->opcode_modifier.jump == JUMP_ABSOLUTE)
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@ -6509,8 +6523,15 @@ match_template (char mnem_suffix)
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slip through to break. */
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}
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/* Check if vector and VEX operands are valid. */
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if (check_VecOperands (t) || VEX_check_operands (t))
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/* Check if vector operands are valid. */
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if (check_VecOperands (t))
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{
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specific_error = i.error;
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continue;
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}
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/* Check if VEX/EVEX encoding requirements can be satisfied. */
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if (VEX_check_encoding (t))
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{
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specific_error = i.error;
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continue;
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@ -12394,7 +12415,10 @@ static bfd_boolean check_register (const reg_entry *r)
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|| flag_code != CODE_64BIT)
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return FALSE;
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i.vec_encoding = vex_encoding_evex;
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if (i.vec_encoding == vex_encoding_default)
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i.vec_encoding = vex_encoding_evex;
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else if (i.vec_encoding != vex_encoding_evex)
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i.vec_encoding = vex_encoding_error;
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}
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if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
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@ -492,6 +492,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_list_test "cet-ibt-inval"
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run_list_test "cet-shstk-inval"
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run_dump_test "pseudos"
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run_list_test "pseudos-bad"
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run_dump_test "notrack"
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run_dump_test "notrack-intel"
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run_list_test "notrackbad" "-al"
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@ -1074,6 +1075,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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run_list_test "x86-64-cet-ibt-inval"
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run_list_test "x86-64-cet-shstk-inval"
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run_dump_test "x86-64-pseudos"
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run_list_test "x86-64-pseudos-bad"
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run_dump_test "x86-64-notrack"
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run_dump_test "x86-64-notrack-intel"
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run_list_test "x86-64-notrackbad" "-al"
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@ -0,0 +1,9 @@
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.*: Assembler messages:
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.*:3: Error: .*`nop'.*
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.*:4: Error: .*`nop'.*
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.*:6: Error: .*`nop'.*
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.*:7: Error: .*`nop'.*
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.*:9: Error: .*`nop'.*
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.*:10: Error: .*`nop'.*
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.*:12: Error: .*`vzeroall'.*
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.*:13: Error: .*`vmovmskps'.*
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@ -0,0 +1,13 @@
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.text
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pseudos:
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{vex} nop
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{vex} nop %eax
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{vex3} nop
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{vex3} nop %eax
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{evex} nop
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{evex} nop %eax
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{evex} vzeroall
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{evex} vmovmskps %xmm0, %eax
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@ -2,6 +2,6 @@
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.intel_syntax noprefix
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.code64
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xmm:
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{vex2} vaddps xmm0, xmm1, xmm16
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{vex2} vaddps ymm0, ymm1, ymm16
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{vex2} vaddps zmm0, zmm1, zmm16
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vaddps xmm0, xmm1, xmm16
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vaddps ymm0, ymm1, ymm16
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vaddps zmm0, zmm1, zmm16
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