opcodes/
* ppc-opc.c (insert_sprg, extract_sprg): New Functions.
(powerpc_operands <SPRG>): Call the above. Bit field is 5 bits.
(SPRG_MASK): Delete.
(XSPRG_MASK): Mask off extra bits now part of sprg field.
(powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask. Move
mfsprg4..7 after msprg and consolidate.
gas/testsuite
* gas/ppc/booke.s: Add new m[t,f]sprg testcases.
* gas/ppc/booke.d: Likewise.
This commit is contained in:
Alan Modra
parent
953130a55d
commit
da99ee721e
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@ -1,3 +1,9 @@
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2005-03-10 Jeff Baker <jbaker@qnx.com>
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Alan Modra <amodra@bigpond.net.au>
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* gas/ppc/booke.s: Add new m[t,f]sprg testcases.
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* gas/ppc/booke.d: Likewise.
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2005-03-09 Richard Sandiford <rsandifo@redhat.com>
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* gas/mips/vr4130.[sd]: New test.
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@ -93,12 +99,11 @@
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2005-03-03 Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
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* gas/arc/extensions.s: Add tests for extcoreregister
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* gas/arc/extensions.d: Likewise.
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* gas/arc/warn.s: Warnings for readonly core registers
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accessed .
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* gas/arc/warn.d:Likewise.
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* testsuite/gas/arc/arc.exp:Run extensions testcase.
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* gas/arc/extensions.s: Add tests for extcoreregister.
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* gas/arc/extensions.d: Likewise.
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* gas/arc/warn.s: Warnings for readonly core registers accessed.
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* gas/arc/warn.d: Likewise.
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* testsuite/gas/arc/arc.exp: Run extensions testcase.
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2005-03-03 Richard Sandiford <rsandifo@redhat.com>
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@ -106,8 +111,8 @@
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2005-03-03 Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
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* gas/arc/ld.s:Add checks for short immediates with ld
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* gas/arc/ld.d:Likewise.
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* gas/arc/ld.s: Add checks for short immediates with ld.
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* gas/arc/ld.d: Likewise.
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2005-03-02 Daniel Jacobowitz <dan@codesourcery.com>
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@ -142,3 +142,11 @@ Disassembly of section \.text:
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1c0: 7c 00 06 ac mbar
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1c4: 7c 00 06 ac mbar
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1c8: 7c 20 06 ac mbar 1
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1cc: 7c 12 42 a6 mfsprg r0,2
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1d0: 7c 12 42 a6 mfsprg r0,2
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1d4: 7c 12 43 a6 mtsprg 2,r0
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1d8: 7c 12 43 a6 mtsprg 2,r0
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1dc: 7c 07 42 a6 mfsprg r0,7
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1e0: 7c 07 42 a6 mfsprg r0,7
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1e4: 7c 17 43 a6 mtsprg 7,r0
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1e8: 7c 17 43 a6 mtsprg 7,r0
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@ -134,3 +134,12 @@ branch_target_8:
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mbar
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mbar 0
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mbar 1
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mfsprg 0, 2
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mfsprg2 0
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mtsprg 2, 0
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mtsprg2 0
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mfsprg 0, 7
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mfsprg7 0
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mtsprg 7, 0
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mtsprg7 0
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@ -1,3 +1,13 @@
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2005-03-10 Jeff Baker <jbaker@qnx.com>
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Alan Modra <amodra@bigpond.net.au>
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* ppc-opc.c (insert_sprg, extract_sprg): New Functions.
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(powerpc_operands <SPRG>): Call the above. Bit field is 5 bits.
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(SPRG_MASK): Delete.
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(XSPRG_MASK): Mask off extra bits now part of sprg field.
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(powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask. Move
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mfsprg4..7 after msprg and consolidate.
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2005-03-09 Jan-Benedict Glaw <jbglaw@lug-owl.de>
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* vax-dis.c (entry_mask_bit): New array.
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@ -84,6 +84,8 @@ static unsigned long insert_sh6 (unsigned long, long, int, const char **);
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static long extract_sh6 (unsigned long, int, int *);
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static unsigned long insert_spr (unsigned long, long, int, const char **);
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static long extract_spr (unsigned long, int, int *);
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static unsigned long insert_sprg (unsigned long, long, int, const char **);
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static long extract_sprg (unsigned long, int, int *);
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static unsigned long insert_tbr (unsigned long, long, int, const char **);
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static long extract_tbr (unsigned long, int, int *);
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static unsigned long insert_ev2 (unsigned long, long, int, const char **);
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@ -465,8 +467,7 @@ const struct powerpc_operand powerpc_operands[] =
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/* The SPRG register number in an XFX form m[ft]sprg instruction. */
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#define SPRG SPRBAT + 1
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#define SPRG_MASK (0x3 << 16)
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{ 2, 16, NULL, NULL, 0 },
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{ 5, 16, insert_sprg, extract_sprg, 0 },
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/* The SR field in an X form instruction. */
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#define SR SPRG + 1
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@ -1397,6 +1398,47 @@ extract_spr (unsigned long insn,
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return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
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}
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/* Some dialects have 8 SPRG registers instead of the standard 4. */
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static unsigned long
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insert_sprg (unsigned long insn,
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long value,
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int dialect,
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const char **errmsg)
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{
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/* This check uses PPC_OPCODE_403 because PPC405 is later defined
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as a synonym. If ever a 405 specific dialect is added this
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check should use that instead. */
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if (value > 7
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|| (value > 3
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&& (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
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*errmsg = _("invalid sprg number");
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/* If this is mfsprg4..7 then use spr 260..263 which can be read in
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user mode. Anything else must use spr 272..279. */
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if (value <= 3 || (insn & 0x100) != 0)
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value |= 0x10;
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return insn | ((value & 0x17) << 16);
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}
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static long
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extract_sprg (unsigned long insn,
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int dialect,
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int *invalid)
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{
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unsigned long val = (insn >> 16) & 0x1f;
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/* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
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If not BOOKE or 405, then both use only 272..275. */
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if (val <= 3
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|| (val < 0x10 && (insn & 0x100) != 0)
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|| (val - 0x10 > 3
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&& (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
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*invalid = 1;
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return val & 7;
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}
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/* The TBR field in an XFX instruction. This is just like SPR, but it
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is optional. When TBR is omitted, it must be inserted as 268 (the
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magic number of the TB register). These functions treat 0
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@ -1705,7 +1747,7 @@ extract_tbr (unsigned long insn,
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/* An XFX form instruction with the SPR field filled in except for the
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SPRG field. */
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#define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
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#define XSPRG_MASK (XSPR_MASK & ~(0x17 << 16))
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/* An X form instruction with everything filled in except the E field. */
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#define XE_MASK (0xffff7fff)
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@ -3677,25 +3719,21 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
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{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
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{ "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
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{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } },
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{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, BOOKE, { RT } },
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{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } },
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{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, BOOKE, { RT } },
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{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } },
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{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, BOOKE, { RT } },
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{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } },
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{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, BOOKE, { RT } },
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{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
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{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
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{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
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{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
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{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
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{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
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{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
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{ "mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, { RT, SPRG } },
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{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
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{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
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{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
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{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
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{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405 | BOOKE, { RT } },
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{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405 | BOOKE, { RT } },
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{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405 | BOOKE, { RT } },
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{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405 | BOOKE, { RT } },
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{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
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{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
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{ "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
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@ -3998,7 +4036,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } },
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{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } },
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{ "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
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{ "mtsprg", XSPR(31,467,272), XSPRG_MASK,PPC, { SPRG, RS } },
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{ "mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, { SPRG, RS } },
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{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } },
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{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } },
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{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } },
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