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[cgen]

Browse Source 
* intrinsics.scm: Updates to support IVC2.
	(belongs-to-group?): Check IVC2 slots.
	(-slots-attribute): New.
	(targets::attributes): Add SLOTS.
	(target:add-well-known-intrinsics): Add CPMOV.
	(md-insn): Add CPTYPE and CRET?.
	(add-md-insn): Likewise.
	(add-intrinsic-for-isa): Disable the duplicate tests, as IVC2 has
	duplicate insns with different bit patterns.
	(write-cgen-insn?): Add cret? support.
	(intrinsics.h): Add vector types.
	(runtime-op): Add vector support.
	(intrinsic-protos.h): Let GCC define its types.  Add cret? support.

	* cpu/mep-core.cpu: Add CPTYPE and CRET attributes.
	* cpu/mep-ivc2.cpu: Update all insns to include type information.
	(h-cr-ivc2): Default to typeless.
	(h-ccr-ivc2): Fix register width.
	(SLOTS): Fix values and default.
	(ivc2_*): Add control register names.
	(crop, crqp, crpp, croc, crqc, crpc): Default to typeless.

[opcodes]

	* mep-desc.c: Regenerate.
	* mep-desc.h: Regenerate.
	* mep-dis.c: Regenerate.
	* mep-ibld.c: Regenerate.
	* mep-opc.c: Regenerate.

[sid/component/cgen-cpu/mep]

	* ivc2-cop.cxx (ivc2_cphadd_w): Change to return value.
	(ivc2_cpsubaca0u_b): Remove debug line.
	* ivc2-cpu.h (ivc2_cpccadd_b): Change to return value.
	* mep-cop1-16-decode.cxx: Regenerate.
	* mep-cop1-16-sem.cxx: Regenerate.
	* mep-cop1-32-decode.cxx: Regenerate.
	* mep-cop1-32-sem.cxx: Regenerate.
	* mep-cop1-48-decode.cxx: Regenerate.
	* mep-cop1-48-sem.cxx: Regenerate.
	* mep-cop1-64-decode.cxx: Regenerate.
	* mep-cop1-64-sem.cxx: Regenerate.
	* mep-core1-decode.cxx: Regenerate.
	* mep-cpu.h: Regenerate.
	* mep-decode.cxx: Regenerate.
	* mep-desc.h: Regenerate.
This commit is contained in:
DJ Delorie 2009-06-24 03:06:42 +00:00
parent 378a0c07ca
commit dab97f2471
7 changed files with 1558 additions and 951 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
opcodes/ChangeLog
View File

@ -1,5 +1,11 @@
2009-06-23 DJ Delorie <dj@redhat.com>
* mep-desc.c: Regenerate.
* mep-desc.h: Regenerate.
* mep-dis.c: Regenerate.
* mep-ibld.c: Regenerate.
* mep-opc.c: Regenerate.
* mep-asm.c: Regenerate.
* mep-opc.c: Regenerate.
* mep-opc.h: Regenerate.

69
opcodes/mep-asm.c
View File

@ -1023,6 +1023,75 @@ mep_cgen_parse_operand (CGEN_CPU_DESC cd,
case MEP_OPERAND_IVC_X_6_3 :
errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IVC_X_6_3, (unsigned long *) (& fields->f_ivc2_3u6));
break;
case MEP_OPERAND_IVC2_ACC0_0 :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
break;
case MEP_OPERAND_IVC2_ACC0_1 :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
break;
case MEP_OPERAND_IVC2_ACC0_2 :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
break;
case MEP_OPERAND_IVC2_ACC0_3 :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
break;
case MEP_OPERAND_IVC2_ACC0_4 :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
break;
case MEP_OPERAND_IVC2_ACC0_5 :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
break;
case MEP_OPERAND_IVC2_ACC0_6 :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
break;
case MEP_OPERAND_IVC2_ACC0_7 :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
break;
case MEP_OPERAND_IVC2_ACC1_0 :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
break;
case MEP_OPERAND_IVC2_ACC1_1 :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
break;
case MEP_OPERAND_IVC2_ACC1_2 :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
break;
case MEP_OPERAND_IVC2_ACC1_3 :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
break;
case MEP_OPERAND_IVC2_ACC1_4 :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
break;
case MEP_OPERAND_IVC2_ACC1_5 :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
break;
case MEP_OPERAND_IVC2_ACC1_6 :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
break;
case MEP_OPERAND_IVC2_ACC1_7 :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
break;
case MEP_OPERAND_IVC2_CC :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
break;
case MEP_OPERAND_IVC2_COFA0 :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
break;
case MEP_OPERAND_IVC2_COFA1 :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
break;
case MEP_OPERAND_IVC2_COFR0 :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
break;
case MEP_OPERAND_IVC2_COFR1 :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
break;
case MEP_OPERAND_IVC2_CSAR0 :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
break;
case MEP_OPERAND_IVC2_CSAR1 :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
break;
case MEP_OPERAND_IVC2C3CCRN :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & fields->f_ivc2_ccrn_c3);
break;

1965
opcodes/mep-desc.c
View File

File diff suppressed because it is too large Load Diff

46
opcodes/mep-desc.h
View File

@ -92,6 +92,17 @@ typedef enum cdata_attr {
, CDATA_USHORT, CDATA_CHAR, CDATA_UCHAR, CDATA_CP_DATA_BUS_INT
} CDATA_ATTR;
/* Enum declaration for datatype to use for coprocessor values. */
typedef enum cptype_attr {
CPTYPE_CP_DATA_BUS_INT, CPTYPE_VECT, CPTYPE_V2SI, CPTYPE_V4HI
, CPTYPE_V8QI, CPTYPE_V2USI, CPTYPE_V4UHI, CPTYPE_V8UQI
} CPTYPE_ATTR;
/* Enum declaration for Insn's intrinsic returns void, or the first argument rather than (or in addition to) passing it.. */
typedef enum cret_attr {
CRET_VOID, CRET_FIRST, CRET_FIRSTCOPY
} CRET_ATTR;
/* Enum declaration for . */
typedef enum config_attr {
CONFIG_NONE, CONFIG_DEFAULT
@ -258,21 +269,27 @@ typedef enum cgen_operand_type {
, MEP_OPERAND_UDISP7A4, MEP_OPERAND_UIMM7A4, MEP_OPERAND_UIMM24, MEP_OPERAND_CIMM4
, MEP_OPERAND_CIMM5, MEP_OPERAND_CDISP10, MEP_OPERAND_CDISP10A2, MEP_OPERAND_CDISP10A4
, MEP_OPERAND_CDISP10A8, MEP_OPERAND_ZERO, MEP_OPERAND_RL5, MEP_OPERAND_CDISP12
, MEP_OPERAND_C5RMUIMM20, MEP_OPERAND_C5RNMUIMM24, MEP_OPERAND_CP_FLAG, MEP_OPERAND_CROC
, MEP_OPERAND_CRQC, MEP_OPERAND_CRPC, MEP_OPERAND_IVC_X_6_1, MEP_OPERAND_IVC_X_6_2
, MEP_OPERAND_IVC_X_6_3, MEP_OPERAND_IMM3P4, MEP_OPERAND_IMM3P9, MEP_OPERAND_IMM4P8
, MEP_OPERAND_IMM5P7, MEP_OPERAND_IMM6P6, MEP_OPERAND_IMM8P4, MEP_OPERAND_SIMM8P4
, MEP_OPERAND_IMM3P5, MEP_OPERAND_IMM3P12, MEP_OPERAND_IMM4P4, MEP_OPERAND_IMM4P10
, MEP_OPERAND_IMM5P8, MEP_OPERAND_IMM5P3, MEP_OPERAND_IMM6P2, MEP_OPERAND_IMM5P23
, MEP_OPERAND_IMM3P25, MEP_OPERAND_IMM8P0, MEP_OPERAND_SIMM8P0, MEP_OPERAND_SIMM8P20
, MEP_OPERAND_IMM8P20, MEP_OPERAND_CROP, MEP_OPERAND_CRQP, MEP_OPERAND_CRPP
, MEP_OPERAND_IVC_X_0_2, MEP_OPERAND_IVC_X_0_3, MEP_OPERAND_IVC_X_0_4, MEP_OPERAND_IVC_X_0_5
, MEP_OPERAND_IMM16P0, MEP_OPERAND_SIMM16P0, MEP_OPERAND_IVC2RM, MEP_OPERAND_IVC2CRN
, MEP_OPERAND_IVC2CCRN, MEP_OPERAND_IVC2C3CCRN, MEP_OPERAND_MAX
, MEP_OPERAND_C5RMUIMM20, MEP_OPERAND_C5RNMUIMM24, MEP_OPERAND_CP_FLAG, MEP_OPERAND_IVC2_CSAR0
, MEP_OPERAND_IVC2_CC, MEP_OPERAND_IVC2_COFR0, MEP_OPERAND_IVC2_COFR1, MEP_OPERAND_IVC2_COFA0
, MEP_OPERAND_IVC2_COFA1, MEP_OPERAND_IVC2_CSAR1, MEP_OPERAND_IVC2_ACC0_0, MEP_OPERAND_IVC2_ACC0_1
, MEP_OPERAND_IVC2_ACC0_2, MEP_OPERAND_IVC2_ACC0_3, MEP_OPERAND_IVC2_ACC0_4, MEP_OPERAND_IVC2_ACC0_5
, MEP_OPERAND_IVC2_ACC0_6, MEP_OPERAND_IVC2_ACC0_7, MEP_OPERAND_IVC2_ACC1_0, MEP_OPERAND_IVC2_ACC1_1
, MEP_OPERAND_IVC2_ACC1_2, MEP_OPERAND_IVC2_ACC1_3, MEP_OPERAND_IVC2_ACC1_4, MEP_OPERAND_IVC2_ACC1_5
, MEP_OPERAND_IVC2_ACC1_6, MEP_OPERAND_IVC2_ACC1_7, MEP_OPERAND_CROC, MEP_OPERAND_CRQC
, MEP_OPERAND_CRPC, MEP_OPERAND_IVC_X_6_1, MEP_OPERAND_IVC_X_6_2, MEP_OPERAND_IVC_X_6_3
, MEP_OPERAND_IMM3P4, MEP_OPERAND_IMM3P9, MEP_OPERAND_IMM4P8, MEP_OPERAND_IMM5P7
, MEP_OPERAND_IMM6P6, MEP_OPERAND_IMM8P4, MEP_OPERAND_SIMM8P4, MEP_OPERAND_IMM3P5
, MEP_OPERAND_IMM3P12, MEP_OPERAND_IMM4P4, MEP_OPERAND_IMM4P10, MEP_OPERAND_IMM5P8
, MEP_OPERAND_IMM5P3, MEP_OPERAND_IMM6P2, MEP_OPERAND_IMM5P23, MEP_OPERAND_IMM3P25
, MEP_OPERAND_IMM8P0, MEP_OPERAND_SIMM8P0, MEP_OPERAND_SIMM8P20, MEP_OPERAND_IMM8P20
, MEP_OPERAND_CROP, MEP_OPERAND_CRQP, MEP_OPERAND_CRPP, MEP_OPERAND_IVC_X_0_2
, MEP_OPERAND_IVC_X_0_3, MEP_OPERAND_IVC_X_0_4, MEP_OPERAND_IVC_X_0_5, MEP_OPERAND_IMM16P0
, MEP_OPERAND_SIMM16P0, MEP_OPERAND_IVC2RM, MEP_OPERAND_IVC2CRN, MEP_OPERAND_IVC2CCRN
, MEP_OPERAND_IVC2C3CCRN, MEP_OPERAND_MAX
} CGEN_OPERAND_TYPE;
/* Number of operands types. */
#define MAX_OPERANDS 122
#define MAX_OPERANDS 145
/* Maximum number of operands referenced by any insn. */
#define MAX_OPERAND_INSTANCES 8
@ -290,7 +307,8 @@ typedef enum cgen_insn_attr {
, CGEN_INSN_OPTIONAL_VLIW64, CGEN_INSN_MAY_TRAP, CGEN_INSN_VLIW_ALONE, CGEN_INSN_VLIW_NO_CORE_NOP
, CGEN_INSN_VLIW_NO_COP_NOP, CGEN_INSN_VLIW64_NO_MATCHING_NOP, CGEN_INSN_VLIW32_NO_MATCHING_NOP, CGEN_INSN_VOLATILE
, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_ISA
, CGEN_INSN_LATENCY, CGEN_INSN_CONFIG, CGEN_INSN_SLOTS, CGEN_INSN_END_NBOOLS
, CGEN_INSN_CPTYPE, CGEN_INSN_CRET, CGEN_INSN_LATENCY, CGEN_INSN_CONFIG
, CGEN_INSN_SLOTS, CGEN_INSN_END_NBOOLS
} CGEN_INSN_ATTR;
/* Number of non-boolean elements in cgen_insn_attr. */
@ -299,6 +317,8 @@ typedef enum cgen_insn_attr {
/* cgen_insn attribute accessor macros. */
#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset)
#define CGEN_ATTR_CGEN_INSN_CPTYPE_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_CPTYPE-CGEN_INSN_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_INSN_CRET_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_CRET-CGEN_INSN_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_INSN_LATENCY_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_LATENCY-CGEN_INSN_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_INSN_CONFIG_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_CONFIG-CGEN_INSN_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_INSN_SLOTS_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_SLOTS-CGEN_INSN_START_NBOOLS-1].nonbitset)

69
opcodes/mep-dis.c
View File

@ -928,6 +928,75 @@ mep_cgen_print_operand (CGEN_CPU_DESC cd,
case MEP_OPERAND_IVC_X_6_3 :
print_normal (cd, info, fields->f_ivc2_3u6, 0, pc, length);
break;
case MEP_OPERAND_IVC2_ACC0_0 :
print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
break;
case MEP_OPERAND_IVC2_ACC0_1 :
print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
break;
case MEP_OPERAND_IVC2_ACC0_2 :
print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
break;
case MEP_OPERAND_IVC2_ACC0_3 :
print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
break;
case MEP_OPERAND_IVC2_ACC0_4 :
print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
break;
case MEP_OPERAND_IVC2_ACC0_5 :
print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
break;
case MEP_OPERAND_IVC2_ACC0_6 :
print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
break;
case MEP_OPERAND_IVC2_ACC0_7 :
print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
break;
case MEP_OPERAND_IVC2_ACC1_0 :
print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
break;
case MEP_OPERAND_IVC2_ACC1_1 :
print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
break;
case MEP_OPERAND_IVC2_ACC1_2 :
print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
break;
case MEP_OPERAND_IVC2_ACC1_3 :
print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
break;
case MEP_OPERAND_IVC2_ACC1_4 :
print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
break;
case MEP_OPERAND_IVC2_ACC1_5 :
print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
break;
case MEP_OPERAND_IVC2_ACC1_6 :
print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
break;
case MEP_OPERAND_IVC2_ACC1_7 :
print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
break;
case MEP_OPERAND_IVC2_CC :
print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
break;
case MEP_OPERAND_IVC2_COFA0 :
print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
break;
case MEP_OPERAND_IVC2_COFA1 :
print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
break;
case MEP_OPERAND_IVC2_COFR0 :
print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
break;
case MEP_OPERAND_IVC2_COFR1 :
print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
break;
case MEP_OPERAND_IVC2_CSAR0 :
print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
break;
case MEP_OPERAND_IVC2_CSAR1 :
print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
break;
case MEP_OPERAND_IVC2C3CCRN :
print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, fields->f_ivc2_ccrn_c3, 0|(1<<CGEN_OPERAND_VIRTUAL));
break;

322
opcodes/mep-ibld.c
View File

@ -878,6 +878,52 @@ mep_cgen_insert_operand (CGEN_CPU_DESC cd,
case MEP_OPERAND_IVC_X_6_3 :
errmsg = insert_normal (cd, fields->f_ivc2_3u6, 0, 0, 6, 3, 32, total_length, buffer);
break;
case MEP_OPERAND_IVC2_ACC0_0 :
break;
case MEP_OPERAND_IVC2_ACC0_1 :
break;
case MEP_OPERAND_IVC2_ACC0_2 :
break;
case MEP_OPERAND_IVC2_ACC0_3 :
break;
case MEP_OPERAND_IVC2_ACC0_4 :
break;
case MEP_OPERAND_IVC2_ACC0_5 :
break;
case MEP_OPERAND_IVC2_ACC0_6 :
break;
case MEP_OPERAND_IVC2_ACC0_7 :
break;
case MEP_OPERAND_IVC2_ACC1_0 :
break;
case MEP_OPERAND_IVC2_ACC1_1 :
break;
case MEP_OPERAND_IVC2_ACC1_2 :
break;
case MEP_OPERAND_IVC2_ACC1_3 :
break;
case MEP_OPERAND_IVC2_ACC1_4 :
break;
case MEP_OPERAND_IVC2_ACC1_5 :
break;
case MEP_OPERAND_IVC2_ACC1_6 :
break;
case MEP_OPERAND_IVC2_ACC1_7 :
break;
case MEP_OPERAND_IVC2_CC :
break;
case MEP_OPERAND_IVC2_COFA0 :
break;
case MEP_OPERAND_IVC2_COFA1 :
break;
case MEP_OPERAND_IVC2_COFR0 :
break;
case MEP_OPERAND_IVC2_COFR1 :
break;
case MEP_OPERAND_IVC2_CSAR0 :
break;
case MEP_OPERAND_IVC2_CSAR1 :
break;
case MEP_OPERAND_IVC2C3CCRN :
{
{
@ -1459,6 +1505,52 @@ mep_cgen_extract_operand (CGEN_CPU_DESC cd,
case MEP_OPERAND_IVC_X_6_3 :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 6, 3, 32, total_length, pc, & fields->f_ivc2_3u6);
break;
case MEP_OPERAND_IVC2_ACC0_0 :
break;
case MEP_OPERAND_IVC2_ACC0_1 :
break;
case MEP_OPERAND_IVC2_ACC0_2 :
break;
case MEP_OPERAND_IVC2_ACC0_3 :
break;
case MEP_OPERAND_IVC2_ACC0_4 :
break;
case MEP_OPERAND_IVC2_ACC0_5 :
break;
case MEP_OPERAND_IVC2_ACC0_6 :
break;
case MEP_OPERAND_IVC2_ACC0_7 :
break;
case MEP_OPERAND_IVC2_ACC1_0 :
break;
case MEP_OPERAND_IVC2_ACC1_1 :
break;
case MEP_OPERAND_IVC2_ACC1_2 :
break;
case MEP_OPERAND_IVC2_ACC1_3 :
break;
case MEP_OPERAND_IVC2_ACC1_4 :
break;
case MEP_OPERAND_IVC2_ACC1_5 :
break;
case MEP_OPERAND_IVC2_ACC1_6 :
break;
case MEP_OPERAND_IVC2_ACC1_7 :
break;
case MEP_OPERAND_IVC2_CC :
break;
case MEP_OPERAND_IVC2_COFA0 :
break;
case MEP_OPERAND_IVC2_COFA1 :
break;
case MEP_OPERAND_IVC2_COFR0 :
break;
case MEP_OPERAND_IVC2_COFR1 :
break;
case MEP_OPERAND_IVC2_CSAR0 :
break;
case MEP_OPERAND_IVC2_CSAR1 :
break;
case MEP_OPERAND_IVC2C3CCRN :
{
length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 2, 32, total_length, pc, & fields->f_ivc2_ccrn_c3hi);
@ -1917,6 +2009,75 @@ mep_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MEP_OPERAND_IVC_X_6_3 :
value = fields->f_ivc2_3u6;
break;
case MEP_OPERAND_IVC2_ACC0_0 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC0_1 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC0_2 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC0_3 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC0_4 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC0_5 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC0_6 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC0_7 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC1_0 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC1_1 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC1_2 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC1_3 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC1_4 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC1_5 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC1_6 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC1_7 :
value = 0;
break;
case MEP_OPERAND_IVC2_CC :
value = 0;
break;
case MEP_OPERAND_IVC2_COFA0 :
value = 0;
break;
case MEP_OPERAND_IVC2_COFA1 :
value = 0;
break;
case MEP_OPERAND_IVC2_COFR0 :
value = 0;
break;
case MEP_OPERAND_IVC2_COFR1 :
value = 0;
break;
case MEP_OPERAND_IVC2_CSAR0 :
value = 0;
break;
case MEP_OPERAND_IVC2_CSAR1 :
value = 0;
break;
case MEP_OPERAND_IVC2C3CCRN :
value = fields->f_ivc2_ccrn_c3;
break;
@ -2300,6 +2461,75 @@ mep_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MEP_OPERAND_IVC_X_6_3 :
value = fields->f_ivc2_3u6;
break;
case MEP_OPERAND_IVC2_ACC0_0 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC0_1 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC0_2 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC0_3 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC0_4 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC0_5 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC0_6 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC0_7 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC1_0 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC1_1 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC1_2 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC1_3 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC1_4 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC1_5 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC1_6 :
value = 0;
break;
case MEP_OPERAND_IVC2_ACC1_7 :
value = 0;
break;
case MEP_OPERAND_IVC2_CC :
value = 0;
break;
case MEP_OPERAND_IVC2_COFA0 :
value = 0;
break;
case MEP_OPERAND_IVC2_COFA1 :
value = 0;
break;
case MEP_OPERAND_IVC2_COFR0 :
value = 0;
break;
case MEP_OPERAND_IVC2_COFR1 :
value = 0;
break;
case MEP_OPERAND_IVC2_CSAR0 :
value = 0;
break;
case MEP_OPERAND_IVC2_CSAR1 :
value = 0;
break;
case MEP_OPERAND_IVC2C3CCRN :
value = fields->f_ivc2_ccrn_c3;
break;
@ -2684,6 +2914,52 @@ mep_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MEP_OPERAND_IVC_X_6_3 :
fields->f_ivc2_3u6 = value;
break;
case MEP_OPERAND_IVC2_ACC0_0 :
break;
case MEP_OPERAND_IVC2_ACC0_1 :
break;
case MEP_OPERAND_IVC2_ACC0_2 :
break;
case MEP_OPERAND_IVC2_ACC0_3 :
break;
case MEP_OPERAND_IVC2_ACC0_4 :
break;
case MEP_OPERAND_IVC2_ACC0_5 :
break;
case MEP_OPERAND_IVC2_ACC0_6 :
break;
case MEP_OPERAND_IVC2_ACC0_7 :
break;
case MEP_OPERAND_IVC2_ACC1_0 :
break;
case MEP_OPERAND_IVC2_ACC1_1 :
break;
case MEP_OPERAND_IVC2_ACC1_2 :
break;
case MEP_OPERAND_IVC2_ACC1_3 :
break;
case MEP_OPERAND_IVC2_ACC1_4 :
break;
case MEP_OPERAND_IVC2_ACC1_5 :
break;
case MEP_OPERAND_IVC2_ACC1_6 :
break;
case MEP_OPERAND_IVC2_ACC1_7 :
break;
case MEP_OPERAND_IVC2_CC :
break;
case MEP_OPERAND_IVC2_COFA0 :
break;
case MEP_OPERAND_IVC2_COFA1 :
break;
case MEP_OPERAND_IVC2_COFR0 :
break;
case MEP_OPERAND_IVC2_COFR1 :
break;
case MEP_OPERAND_IVC2_CSAR0 :
break;
case MEP_OPERAND_IVC2_CSAR1 :
break;
case MEP_OPERAND_IVC2C3CCRN :
fields->f_ivc2_ccrn_c3 = value;
break;
@ -3041,6 +3317,52 @@ mep_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MEP_OPERAND_IVC_X_6_3 :
fields->f_ivc2_3u6 = value;
break;
case MEP_OPERAND_IVC2_ACC0_0 :
break;
case MEP_OPERAND_IVC2_ACC0_1 :
break;
case MEP_OPERAND_IVC2_ACC0_2 :
break;
case MEP_OPERAND_IVC2_ACC0_3 :
break;
case MEP_OPERAND_IVC2_ACC0_4 :
break;
case MEP_OPERAND_IVC2_ACC0_5 :
break;
case MEP_OPERAND_IVC2_ACC0_6 :
break;
case MEP_OPERAND_IVC2_ACC0_7 :
break;
case MEP_OPERAND_IVC2_ACC1_0 :
break;
case MEP_OPERAND_IVC2_ACC1_1 :
break;
case MEP_OPERAND_IVC2_ACC1_2 :
break;
case MEP_OPERAND_IVC2_ACC1_3 :
break;
case MEP_OPERAND_IVC2_ACC1_4 :
break;
case MEP_OPERAND_IVC2_ACC1_5 :
break;
case MEP_OPERAND_IVC2_ACC1_6 :
break;
case MEP_OPERAND_IVC2_ACC1_7 :
break;
case MEP_OPERAND_IVC2_CC :
break;
case MEP_OPERAND_IVC2_COFA0 :
break;
case MEP_OPERAND_IVC2_COFA1 :
break;
case MEP_OPERAND_IVC2_COFR0 :
break;
case MEP_OPERAND_IVC2_COFR1 :
break;
case MEP_OPERAND_IVC2_CSAR0 :
break;
case MEP_OPERAND_IVC2_CSAR1 :
break;
case MEP_OPERAND_IVC2C3CCRN :
fields->f_ivc2_ccrn_c3 = value;
break;

32
opcodes/mep-opc.c
View File

@ -145,6 +145,12 @@ mep_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
int ok1;
int ok2;
int ok3;
/* If we're assembling VLIW packets, ignore the 12-bit BSR as we
can't relax that. The 24-bit BSR is matched instead. */
if (insn->base->num == MEP_INSN_BSR12
&& cgen_bitset_contains (cd->isas, ISA_EXT_COP1_64))
return 0;
/* If the insn has an option bit set that we don't want,
reject it. */
@ -6173,67 +6179,67 @@ static const CGEN_IBASE mep_cgen_macro_insn_table[] =
/* nop */
{
-1, "nop", "nop", 16,
{ 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
{ 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sb $rnc,$zero($rma) */
{
-1, "sb16-0", "sb", 16,
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sh $rns,$zero($rma) */
{
-1, "sh16-0", "sh", 16,
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sw $rnl,$zero($rma) */
{
-1, "sw16-0", "sw", 16,
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lb $rnc,$zero($rma) */
{
-1, "lb16-0", "lb", 16,
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lh $rns,$zero($rma) */
{
-1, "lh16-0", "lh", 16,
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lw $rnl,$zero($rma) */
{
-1, "lw16-0", "lw", 16,
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lbu $rnuc,$zero($rma) */
{
-1, "lbu16-0", "lbu", 16,
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lhu $rnus,$zero($rma) */
{
-1, "lhu16-0", "lhu", 16,
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* swcp $crn,$zero($rma) */
{
-1, "swcp16-0", "swcp", 16,
{ 0|A(NO_DIS)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
{ 0|A(NO_DIS)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lwcp $crn,$zero($rma) */
{
-1, "lwcp16-0", "lwcp", 16,
{ 0|A(NO_DIS)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
{ 0|A(NO_DIS)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* smcp $crn64,$zero($rma) */
{
-1, "smcp16-0", "smcp", 16,
{ 0|A(NO_DIS)|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
{ 0|A(NO_DIS)|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lmcp $crn64,$zero($rma) */
{
-1, "lmcp16-0", "lmcp", 16,
{ 0|A(NO_DIS)|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
{ 0|A(NO_DIS)|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
};