Add function to fetch 32bit instructions
When address translation of insn fetch fails raise exception immediatly. Use address_word as type of all address variables (instead of unsigned64), the former is configured as either 32 or 64 bit type. Always compile fpu code (no #if has fpu)
This commit is contained in:
Andrew Cagney
parent
49a7683337
commit
dad6f1f326
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@ -1,3 +1,23 @@
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Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
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* interp.c (ColdReset): Remove #ifdef HASFPU, check
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CURRENT_FLOATING_POINT instead.
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* interp.c (ifetch32): New function. Fetch 32 bit instruction.
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(address_translation): Raise exception InstructionFetch when
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translation fails and isINSTRUCTION.
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* interp.c (sim_open, sim_write, sim_monitor, store_word,
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sim_engine_run): Change type of of vaddr and paddr to
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address_word.
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(address_translation, prefetch, load_memory, store_memory,
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cache_op): Change type of vAddr and pAddr to address_word.
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* gencode.c (build_instruction): Change type of vaddr and paddr to
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address_word.
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Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
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@ -1865,7 +1865,7 @@ build_mips16_operands (bitmap)
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if ((op->flags & MIPS16_JUMP_ADDR) != 0)
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{
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printf (" {\n");
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printf (" uword64 paddr;\n");
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printf (" address_word paddr;\n");
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printf (" int uncached;\n");
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printf (" if (AddressTranslation (PC &~ (uword64) 1, isINSTRUCTION, isLOAD, &paddr, &uncached, isTARGET, isREAL))\n");
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printf (" {\n");
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@ -2766,8 +2766,8 @@ build_instruction (doisa, features, mips16, insn)
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/* 16-bit offset is sign-extended and added to the base register to make a virtual address */
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/* The virtual address is translated to a physical address using the TLB */
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/* The hint specifies a cache operation for that address */
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printf(" uword64 vaddr = (op1 + offset);\n");
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printf(" uword64 paddr;\n");
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printf(" address_word vaddr = (op1 + offset);\n");
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printf(" address_word paddr;\n");
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printf(" int uncached;\n");
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/* NOTE: We are assuming that the AddressTranslation is a load: */
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printf(" if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))\n");
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@ -2928,10 +2928,10 @@ build_instruction (doisa, features, mips16, insn)
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}
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if (insn->flags & REG)
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printf(" uword64 vaddr = ((uword64)op1 + op2);\n");
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printf(" address_word vaddr = ((uword64)op1 + op2);\n");
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else
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printf(" uword64 vaddr = ((uword64)op1 + offset);\n");
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printf(" uword64 paddr;\n");
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printf(" address_word vaddr = ((uword64)op1 + offset);\n");
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printf(" address_word paddr;\n");
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printf(" int uncached;\n");
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/* The following check should only occur on normal (non-shifted) memory loads */
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@ -3265,8 +3265,8 @@ build_instruction (doisa, features, mips16, insn)
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case FPPREFX:
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/* This code could be merged with the PREFIX generation above: */
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printf(" uword64 vaddr = ((uword64)op1 + (uword64)op2);\n");
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printf(" uword64 paddr;\n");
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printf(" address_word vaddr = ((uword64)op1 + (uword64)op2);\n");
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printf(" address_word paddr;\n");
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printf(" int uncached;\n");
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printf(" if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))\n");
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printf(" Prefetch(uncached,paddr,vaddr,isDATA,fs);\n");
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@ -441,8 +441,8 @@ sim_open (kind, cb, abfd, argv)
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the MIPS TRAP system, we place our own (simulator specific)
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"undefined" instructions into the relevant vector slots. */
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for (loop = 0; (loop < monitor_size); loop += 4) {
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uword64 vaddr = (monitor_base + loop);
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uword64 paddr;
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address_word vaddr = (monitor_base + loop);
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address_word paddr;
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int cca;
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if (AddressTranslation(vaddr, isDATA, isSTORE, &paddr, &cca, isTARGET, isRAW))
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StoreMemory(cca, AccessLength_WORD,
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@ -457,8 +457,8 @@ sim_open (kind, cb, abfd, argv)
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entry points.*/
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for (loop = 0; (loop < 24); loop++)
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{
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uword64 vaddr = (monitor_base + 0x500 + (loop * 4));
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uword64 paddr;
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address_word vaddr = (monitor_base + 0x500 + (loop * 4));
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address_word paddr;
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int cca;
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unsigned int value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
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switch (loop)
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@ -587,7 +587,7 @@ sim_write (sd,addr,buffer,size)
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way. We can then perform doubleword transfers to and from the
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simulator memory for optimum performance. */
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if (index && (index & 1)) {
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uword64 paddr;
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address_word paddr;
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int cca;
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if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) {
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uword64 value = ((uword64)(*buffer++));
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@ -597,7 +597,7 @@ sim_write (sd,addr,buffer,size)
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index &= ~1; /* logical operations usually quicker than arithmetic on RISC systems */
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}
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if (index && (index & 2)) {
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uword64 paddr;
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address_word paddr;
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int cca;
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if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) {
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uword64 value;
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@ -617,7 +617,7 @@ sim_write (sd,addr,buffer,size)
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index &= ~2;
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}
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if (index && (index & 4)) {
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uword64 paddr;
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address_word paddr;
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int cca;
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if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) {
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uword64 value;
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@ -638,7 +638,7 @@ sim_write (sd,addr,buffer,size)
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index &= ~4;
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}
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for (;index; index -= 8) {
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uword64 paddr;
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address_word paddr;
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int cca;
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if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) {
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uword64 value;
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@ -688,9 +688,11 @@ sim_read (sd,addr,buffer,size)
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to ensure that the source physical address is doubleword aligned
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before, and then deal with trailing bytes. */
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for (index = 0; (index < size); index++) {
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uword64 vaddr,paddr,value;
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address_word vaddr;
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address_word paddr;
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unsigned64 value;
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int cca;
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vaddr = (uword64)addr + index;
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vaddr = (address_word)addr + index;
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if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&cca,isTARGET,isRAW)) {
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LoadMemory(&value,NULL,cca,AccessLength_BYTE,paddr,vaddr,isDATA,isRAW);
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buffer[index] = (unsigned char)(value&0xFF);
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@ -819,38 +821,24 @@ sim_create_inferior (sd, abfd, argv,env)
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#endif /* DEBUG */
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ColdReset(sd);
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/* If we were providing a more complete I/O, co-processor or memory
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simulation, we should perform any "device" initialisation at this
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point. This can include pre-loading memory areas with particular
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patterns (e.g. simulating ROM monitors). */
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#if 1
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if (abfd != NULL)
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PC = (unsigned64) bfd_get_start_address(abfd);
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else
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PC = 0; /* ???? */
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#else
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/* TODO: Sort this properly. SIM_ADDR may already be a 64bit value: */
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PC = SIGNEXTEND(bfd_get_start_address(abfd),32);
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#endif
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/* override PC value set by ColdReset () */
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PC = (unsigned64) bfd_get_start_address (abfd);
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/* Prepare to execute the program to be simulated */
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/* argv and env are NULL terminated lists of pointers */
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if (argv || env) {
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#if 0 /* def DEBUG */
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sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n");
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if (argv || env)
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{
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char **cptr;
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for (cptr = argv; (cptr && *cptr); cptr++)
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printf("DBG: arg \"%s\"\n",*cptr);
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/* We should really place the argv slot values into the argument
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registers, and onto the stack as required. However, this
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assumes that we have a stack defined, which is not
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necessarily true at the moment. */
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char **cptr;
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sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n");
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for (cptr = argv; (cptr && *cptr); cptr++)
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printf("DBG: arg \"%s\"\n",*cptr);
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}
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#endif /* DEBUG */
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/* We should really place the argv slot values into the argument
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registers, and onto the stack as required. However, this
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assumes that we have a stack defined, which is not necessarily
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true at the moment. */
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}
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return SIM_RC_OK;
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}
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@ -984,7 +972,7 @@ sim_monitor(sd,reason)
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switch (reason) {
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case 6: /* int open(char *path,int flags) */
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{
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uword64 paddr;
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address_word paddr;
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int cca;
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if (AddressTranslation(A0,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL))
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V0 = sim_io_open(sd,(char *)((int)paddr),(int)A1);
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@ -995,7 +983,7 @@ sim_monitor(sd,reason)
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case 7: /* int read(int file,char *ptr,int len) */
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{
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uword64 paddr;
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address_word paddr;
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int cca;
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if (AddressTranslation(A1,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL))
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V0 = sim_io_read(sd,(int)A0,(char *)((int)paddr),(int)A2);
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@ -1006,7 +994,7 @@ sim_monitor(sd,reason)
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case 8: /* int write(int file,char *ptr,int len) */
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{
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uword64 paddr;
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address_word paddr;
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int cca;
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if (AddressTranslation(A1,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL))
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V0 = sim_io_write(sd,(int)A0,(const char *)((int)paddr),(int)A2);
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@ -1053,8 +1041,8 @@ sim_monitor(sd,reason)
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/* [A0 + 4] = instruction cache size */
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/* [A0 + 8] = data cache size */
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{
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uword64 vaddr = A0;
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uword64 paddr, value;
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address_word vaddr = A0;
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address_word paddr, value;
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int cca;
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int failed = 0;
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@ -1095,7 +1083,7 @@ sim_monitor(sd,reason)
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/* out: void */
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/* The following is based on the PMON printf source */
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{
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uword64 paddr;
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address_word paddr;
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int cca;
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/* This isn't the quickest way, since we call the host print
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routine for every character almost. But it does avoid
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@ -1210,7 +1198,7 @@ store_word (sd, vaddr, val)
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uword64 vaddr;
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t_reg val;
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{
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uword64 paddr;
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address_word paddr;
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int uncached;
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if ((vaddr & 3) != 0)
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@ -1244,7 +1232,7 @@ load_word (sd, vaddr)
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SignalExceptionAddressLoad ();
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else
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{
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uword64 paddr;
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address_word paddr;
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int uncached;
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if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
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@ -1475,20 +1463,20 @@ void dotrace(SIM_DESC sd,FILE *tracefh,int type,SIM_ADDR address,int width,char
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/*---------------------------------------------------------------------------*/
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static void
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ColdReset(sd)
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ColdReset (sd)
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SIM_DESC sd;
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{
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/* RESET: Fixed PC address: */
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PC = (((uword64)0xFFFFFFFF<<32) | 0xBFC00000);
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PC = UNSIGNED64 (0xFFFFFFFFBFC00000);
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/* The reset vector address is in the unmapped, uncached memory space. */
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SR &= ~(status_SR | status_TS | status_RP);
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SR |= (status_ERL | status_BEV);
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#if defined(HASFPU) && (GPRLEN == (64))
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/* Cheat and allow access to the complete register set immediately: */
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SR |= status_FR; /* 64bit registers */
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#endif /* HASFPU and 64bit FP registers */
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/* Cheat and allow access to the complete register set immediately */
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if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
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&& WITH_TARGET_WORD_BITSIZE == 64)
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SR |= status_FR; /* 64bit registers */
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/* Ensure that any instructions with pending register updates are
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cleared: */
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@ -1499,19 +1487,19 @@ ColdReset(sd)
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PENDING_IN = PENDING_OUT = PENDING_TOTAL = 0;
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}
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#if defined(HASFPU)
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/* Initialise the FPU registers to the unknown state */
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{
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int rn;
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for (rn = 0; (rn < 32); rn++)
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FPR_STATE[rn] = fmt_uninterpreted;
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}
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#endif /* HASFPU */
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if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
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{
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int rn;
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for (rn = 0; (rn < 32); rn++)
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FPR_STATE[rn] = fmt_uninterpreted;
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}
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return;
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}
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/* Description from page A-22 of the "MIPS IV Instruction Set" manual (revision 3.1) */
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/* Description from page A-22 of the "MIPS IV Instruction Set" manual
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(revision 3.1) */
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/* Translate a virtual address to a physical address and cache
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coherence algorithm describing the mechanism used to resolve the
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memory reference. Given the virtual address vAddr, and whether the
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@ -1525,17 +1513,16 @@ ColdReset(sd)
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translation is not present in the TLB or the desired access is not
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permitted the function fails and an exception is taken.
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NOTE: This function is extended to return an exception state. This,
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along with the exception generation is used to notify whether a
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valid address translation occured */
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NOTE: Normally (RAW == 0), when address translation fails, this
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function raises an exception and does not return. */
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int
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address_translation(sd,vAddr,IorD,LorS,pAddr,CCA,host,raw)
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SIM_DESC sd;
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uword64 vAddr;
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address_word vAddr;
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int IorD;
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int LorS;
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uword64 *pAddr;
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address_word *pAddr;
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int *CCA;
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int host;
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int raw;
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@ -1583,17 +1570,21 @@ address_translation(sd,vAddr,IorD,LorS,pAddr,CCA,host,raw)
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res = 0; /* AddressTranslation has failed */
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*pAddr = (SIM_ADDR)-1;
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if (!raw) /* only generate exceptions on real memory transfers */
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if (LorS == isSTORE)
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SignalExceptionAddressStore ();
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else
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SignalExceptionAddressLoad ();
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{
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if (IorD == isINSTRUCTION)
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SignalExceptionInstructionFetch ();
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else if (LorS == isSTORE)
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SignalExceptionAddressStore ();
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else
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SignalExceptionAddressLoad ();
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}
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#ifdef DEBUG
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else
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/* This is a normal occurance during gdb operation, for instance trying
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to print parameters at function start before they have been setup,
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and hence we should not print a warning except when debugging the
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simulator. */
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sim_io_eprintf(sd,"AddressTranslation for %s %s from 0x%s failed\n",(IorD ? "data" : "instruction"),(LorS ? "store" : "load"),pr_addr(vAddr));
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/* This is a normal occurance during gdb operation, for instance
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trying to print parameters at function start before they have
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been setup, and hence we should not print a warning except
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when debugging the simulator. */
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sim_io_eprintf(sd,"AddressTranslation for %s %s from 0x%s failed\n",(IorD ? "data" : "instruction"),(LorS ? "store" : "load"),pr_addr(vAddr));
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#endif
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}
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@ -1610,8 +1601,8 @@ void
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prefetch(sd,CCA,pAddr,vAddr,DATA,hint)
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SIM_DESC sd;
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int CCA;
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uword64 pAddr;
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uword64 vAddr;
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address_word pAddr;
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address_word vAddr;
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int DATA;
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int hint;
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{
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@ -1645,8 +1636,8 @@ load_memory(sd,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw)
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uword64* memval1p;
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int CCA;
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int AccessLength;
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uword64 pAddr;
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uword64 vAddr;
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address_word pAddr;
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address_word vAddr;
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int IorD;
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int raw;
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{
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@ -1841,8 +1832,8 @@ store_memory(sd,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw)
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int AccessLength;
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uword64 MemElem;
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uword64 MemElem1; /* High order 64 bits */
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uword64 pAddr;
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uword64 vAddr;
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address_word pAddr;
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address_word vAddr;
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int raw;
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{
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#ifdef DEBUG
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@ -2003,6 +1994,26 @@ store_memory(sd,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw)
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}
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unsigned32
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ifetch32 (SIM_DESC sd, address_word vaddr)
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{
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/* Copy the action of the LW instruction */
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address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
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address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
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unsigned64 value;
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address_word paddr;
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unsigned32 instruction;
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unsigned byte;
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int cca;
|
||||
AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL);
|
||||
paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
|
||||
LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL);
|
||||
byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
|
||||
instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
|
||||
return instruction;
|
||||
}
|
||||
|
||||
|
||||
/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
|
||||
/* Order loads and stores to synchronise shared memory. Perform the
|
||||
action necessary to make the effects of groups of synchronizable
|
||||
|
|
@ -2269,8 +2280,8 @@ void
|
|||
cache_op(sd,op,pAddr,vAddr,instruction)
|
||||
SIM_DESC sd;
|
||||
int op;
|
||||
uword64 pAddr;
|
||||
uword64 vAddr;
|
||||
address_word pAddr;
|
||||
address_word vAddr;
|
||||
unsigned int instruction;
|
||||
{
|
||||
#if 1 /* stop warning message being displayed (we should really just remove the code) */
|
||||
|
|
@ -3546,8 +3557,14 @@ decode_coproc(sd,instruction)
|
|||
|
||||
/*-- instruction simulation -------------------------------------------------*/
|
||||
|
||||
#if defined (WITH_IGEN)
|
||||
void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal));
|
||||
void
|
||||
old_engine_run (sd, next_cpu_nr, siggnal)
|
||||
#else
|
||||
void
|
||||
sim_engine_run (sd, next_cpu_nr, siggnal)
|
||||
#endif
|
||||
SIM_DESC sd;
|
||||
int next_cpu_nr; /* ignore */
|
||||
int siggnal; /* ignore */
|
||||
|
|
@ -3573,23 +3590,16 @@ sim_engine_run (sd, next_cpu_nr, siggnal)
|
|||
/* main controlling loop */
|
||||
while (1) {
|
||||
/* Fetch the next instruction from the simulator memory: */
|
||||
uword64 vaddr = (uword64)PC;
|
||||
uword64 paddr;
|
||||
address_word vaddr = (uword64)PC;
|
||||
address_word paddr;
|
||||
int cca;
|
||||
unsigned int instruction; /* uword64? what's this used for? FIXME! */
|
||||
|
||||
#ifdef DEBUG
|
||||
{
|
||||
printf("DBG: state = 0x%08X :",state);
|
||||
#if 0
|
||||
if (state & simSTOP) printf(" simSTOP");
|
||||
if (state & simSTEP) printf(" simSTEP");
|
||||
#endif
|
||||
if (state & simHALTEX) printf(" simHALTEX");
|
||||
if (state & simHALTIN) printf(" simHALTIN");
|
||||
#if 0
|
||||
if (state & simBE) printf(" simBE");
|
||||
#endif
|
||||
printf("\n");
|
||||
}
|
||||
#endif /* DEBUG */
|
||||
|
|
|
|||
|
|
@ -35,21 +35,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
|
||||
#include "sim-basics.h"
|
||||
|
||||
|
||||
#if 0
|
||||
/* These are generated files. */
|
||||
#include "itable.h"
|
||||
#include "idecode.h"
|
||||
#include "idecode.h"
|
||||
|
||||
/* dummy - not used */
|
||||
typedef instruction_address sim_cia;
|
||||
static const sim_cia null_cia = {0}; /* dummy */
|
||||
#define NULL_CIA null_cia
|
||||
#else
|
||||
typedef int sim_cia;
|
||||
#endif
|
||||
|
||||
typedef address_word sim_cia;
|
||||
|
||||
#include "sim-base.h"
|
||||
|
||||
|
|
@ -303,13 +289,31 @@ struct _sim_cpu {
|
|||
|
||||
/* The following are internal simulator state variables: */
|
||||
sim_cia cia;
|
||||
#define CPU_CIA(CPU) ((CPU)->cia)
|
||||
#define CPU_CIA(CPU) (PC)
|
||||
address_word ipc; /* internal Instruction PC */
|
||||
address_word dspc; /* delay-slot PC */
|
||||
#define IPC ((STATE_CPU (sd,0))->ipc)
|
||||
#define DSPC ((STATE_CPU (sd,0))->dspc)
|
||||
|
||||
#define NULLIFY_NIA() { nia.ip = cia.dp + 4; nia.dp = nia.ip += 4; }
|
||||
/* Issue a delay slot instruction immediatly by re-calling
|
||||
idecode_issue */
|
||||
#define DELAY_SLOT(TARGET) \
|
||||
do { \
|
||||
address_word target = (TARGET); \
|
||||
instruction_word delay_insn; \
|
||||
sim_events_slip (sd, 1); \
|
||||
PC = CIA + 4; \
|
||||
STATE |= simDELAYSLOT; \
|
||||
delay_insn = IMEM (PC); \
|
||||
idecode_issue (sd, delay_insn, (PC)); \
|
||||
STATE &= !simDELAYSLOT; \
|
||||
PC = target; \
|
||||
} while (0)
|
||||
#define NULLIFY_NEXT_INSTRUCTION() \
|
||||
do { \
|
||||
sim_events_slip (sd, 1); \
|
||||
NIA = CIA + 4; \
|
||||
} while (0)
|
||||
|
||||
|
||||
|
||||
|
|
@ -680,28 +684,29 @@ void decode_coproc PARAMS ((SIM_DESC sd,unsigned int instruction));
|
|||
#define AccessLength_DOUBLEWORD (7)
|
||||
#define AccessLength_QUADWORD (15)
|
||||
|
||||
int address_translation PARAMS ((SIM_DESC sd, uword64 vAddr, int IorD, int LorS, uword64 *pAddr, int *CCA, int host, int raw));
|
||||
int address_translation PARAMS ((SIM_DESC sd, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int host, int raw));
|
||||
#define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
|
||||
address_translation(sd, vAddr,IorD,LorS,pAddr,CCA,host,raw)
|
||||
|
||||
void load_memory PARAMS ((SIM_DESC sd, uword64* memvalp, uword64* memval1p, int CCA, int AccessLength, uword64 pAddr, uword64 vAddr, int IorD, int raw));
|
||||
void load_memory PARAMS ((SIM_DESC sd, uword64* memvalp, uword64* memval1p, int CCA, int AccessLength, address_word pAddr, address_word vAddr, int IorD, int raw));
|
||||
#define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
|
||||
load_memory(sd,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw)
|
||||
|
||||
void store_memory PARAMS ((SIM_DESC sd, int CCA, int AccessLength, uword64 MemElem, uword64 MemElem1, uword64 pAddr, uword64 vAddr, int raw));
|
||||
void store_memory PARAMS ((SIM_DESC sd, int CCA, int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr, int raw));
|
||||
#define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
|
||||
store_memory(sd,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw)
|
||||
|
||||
void cache_op PARAMS ((SIM_DESC sd, int op, uword64 pAddr, uword64 vAddr, unsigned int instruction));
|
||||
void cache_op PARAMS ((SIM_DESC sd, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
|
||||
#define CacheOp(op,pAddr,vAddr,instruction) cache_op(sd,op,pAddr,vAddr,instruction)
|
||||
|
||||
void sync_operation PARAMS ((SIM_DESC sd, int stype));
|
||||
#define SyncOperation(stype) sync_operation (sd, (stype))
|
||||
|
||||
void prefetch PARAMS ((SIM_DESC sd, int CCA, uword64 pAddr, uword64 vAddr, int DATA, int hint));
|
||||
void prefetch PARAMS ((SIM_DESC sd, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
|
||||
#define Prefetch(CCA,pAddr,vAddr,DATA,hint) prefetch(sd,CCA,pAddr,vAddr,DATA,hint)
|
||||
|
||||
#define IMEM(CIA) 0 /* FIXME */
|
||||
unsigned32 ifetch32 PARAMS ((SIM_DESC sd, address_word cia));
|
||||
#define IMEM(CIA) ifetch32 (SD, (CIA))
|
||||
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue