* config/tc-mn10300.c (md_relax_table): More fixes to the offsets in this table.
They should be correct now. * gas/mn10300/relax.s: Add further tests of the relaxing of branch instructions. * gas/mn10300/relax.d: Add expected relocations.
This commit is contained in:
Nick Clifton
parent
7b5ba0cc21
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dae1b34eab
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@ -1,3 +1,8 @@
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2004-11-23 Nick Clifton <nickc@redhat.com>
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* config/tc-mn10300.c (md_relax_table): More fixes to the offsets
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in this table. They should be correct now.
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2004-11-23 Jan Beulich <jbeulich@novell.com>
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* config/tc-i386.h (CpuMMX2): Declare. Artificial classifier to
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@ -54,15 +54,20 @@ const char EXP_CHARS[] = "eE";
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as in 0d1.0. */
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const char FLT_CHARS[] = "dD";
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const relax_typeS md_relax_table[] = {
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const relax_typeS md_relax_table[] =
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{
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/* The plus values for the bCC and fBCC instructions in the table below
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are because the branch instruction is translated into a jump
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instruction that is now +2 or +3 bytes further on in memory, and the
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correct size of jump instruction must be selected. */
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/* bCC relaxing */
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{0x7f, -0x80, 2, 1},
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{0x7fff, -0x8000 + 1, 5, 2},
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{0x7fff + 2, -0x8000 + 2, 5, 2},
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{0x7fffffff, -0x80000000, 7, 0},
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/* bCC relaxing (uncommon cases) */
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/* bCC relaxing (uncommon cases for 3byte length instructions) */
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{0x7f, -0x80, 3, 4},
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{0x7fff, -0x8000 + 1, 6, 5},
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{0x7fff + 3, -0x8000 + 3, 6, 5},
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{0x7fffffff, -0x80000000, 8, 0},
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/* call relaxing */
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@ -80,7 +85,7 @@ const relax_typeS md_relax_table[] = {
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/* fbCC relaxing */
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{0x7f, -0x80, 3, 14},
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{0x7fff, -0x8000 + 1, 6, 15},
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{0x7fff + 3, -0x8000 + 3, 6, 15},
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{0x7fffffff, -0x80000000, 8, 0},
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};
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@ -1,3 +1,9 @@
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2004-11-23 Nick Clifton <nickc@redhat.com>
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* gas/mn10300/relax.s: Add further tests of the relaxing of branch
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instructions.
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* gas/mn10300/relax.d: Add expected relocations.
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2004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
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* gas/arc/ld.s: Add check of load of a long immediate.
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@ -6,12 +6,31 @@
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RELOCATION RECORDS FOR \[.rlcb\]:
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OFFSET TYPE VALUE
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0+8003 R_MN10300_PCREL8 .L0._0\+0x00000001
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0+8005 R_MN10300_PCREL32 .L2\+0x00000001
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0+8005 R_MN10300_PCREL32 .L1\+0x00000001
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RELOCATION RECORDS FOR \[.rsflb\]:
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RELOCATION RECORDS FOR \[.rlfcb\]:
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OFFSET TYPE VALUE
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0+8004 R_MN10300_PCREL8 .L0._1\+0x00000002
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0+8006 R_MN10300_PCREL32 .L4\+0x00000001
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0+8006 R_MN10300_PCREL32 .L2\+0x00000001
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RELOCATION RECORDS FOR \[.rscb\]:
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OFFSET TYPE VALUE
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0+103 R_MN10300_PCREL8 .L0._2\+0x00000001
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0+105 R_MN10300_PCREL16 .L3\+0x00000001
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RELOCATION RECORDS FOR \[.rsfcb\]:
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OFFSET TYPE VALUE
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0+104 R_MN10300_PCREL8 .L0._3\+0x00000002
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0+106 R_MN10300_PCREL16 .L4\+0x00000001
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RELOCATION RECORDS FOR \[.rsucb\]:
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OFFSET TYPE VALUE
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0+104 R_MN10300_PCREL8 .L0._4\+0x00000002
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0+106 R_MN10300_PCREL16 .L5\+0x00000001
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RELOCATION RECORDS FOR \[.rlucb\]:
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OFFSET TYPE VALUE
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0+8004 R_MN10300_PCREL8 .L0._5\+0x00000002
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0+8006 R_MN10300_PCREL32 .L6\+0x00000001
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@ -5,6 +5,22 @@
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relax_long_cond_branch:
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clr d0
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clr d1
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.L1:
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add d1,d0
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inc d1
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.fill 32764, 1, 0xcb
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cmp 9,d1
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ble .L1
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rets
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.section .rlfcb, "ax"
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.global relax_long_float_cond_branch
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relax_long_float_cond_branch:
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clr d0
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clr d1
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.L2:
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add d1,d0
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inc d1
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@ -12,21 +28,66 @@ relax_long_cond_branch:
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.fill 32764, 1, 0xcb
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cmp 9,d1
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ble .L2
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fble .L2
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rets
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.section .rsflb, "ax"
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.global relax_long_float_cond_branch
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relax_long_float_cond_branch:
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.section .rscb, "ax"
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.global relax_short_cond_branch
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relax_short_cond_branch:
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clr d0
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clr d1
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.L3:
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add d1,d0
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inc d1
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.fill 252, 1, 0xcb
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cmp 9,d1
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ble .L3
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rets
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.section .rsfcb, "ax"
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.global relax_short_float_cond_branch
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relax_short_float_cond_branch:
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clr d0
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clr d1
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.L4:
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add d1,d0
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inc d1
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.fill 32764, 1, 0xcb
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.fill 252, 1, 0xcb
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cmp 9,d1
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fble .L4
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rets
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.section .rsucb, "ax"
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.global relax_short_uncommon_cond_branch
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relax_short_uncommon_cond_branch:
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clr d0
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clr d1
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.L5:
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add d1,d0
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inc d1
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.fill 252, 1, 0xcb
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cmp 9,d1
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bvc .L5
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rets
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.section .rlucb, "ax"
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.global relax_long_uncommon_cond_branch
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relax_long_uncommon_cond_branch:
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clr d0
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clr d1
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.L6:
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add d1,d0
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inc d1
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.fill 32764, 1, 0xcb
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cmp 9,d1
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bvc .L6
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rets
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