RISC-V: Improve li expansion for better code density.
li is a pseudo instruction in RISC-V, it might expand to more than one instructions if the immediate value can't fit addi or lui, but the assembler will always using 4-byte instructions during expansion. For example: li a0, 0x12345001 will expand into 12345537 lui a0,0x12345 00150513 addi a0,a0,1 but addi could be compress into 0505 addi a0,a0,1 It because load_const use macro_build to emit instructions, and macro_build call append_insn, and expect it will compress it if possible, but the fact is append_insn never compress anything, So this patch redirect the li expansion flow to normal instruction emission flow via md_assemble, added md_assemblef as an wrapper for that for easier emit instruction with printf-style argument to build instruction. gas/ChangeLog: * tc-riscv.c (md_assemblef): New. (load_const) Use md_assemblef instead of macro_build to emit instructions. * testsuite/gas/riscv/li32.d: New. * testsuite/gas/riscv/li32.s: Ditto. * testsuite/gas/riscv/li64.d: Ditto. * testsuite/gas/riscv/li64.s: Ditto.
This commit is contained in:
Kito Cheng
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23c13d4299
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db3b6ecc28
@ -928,6 +928,29 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
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append_insn (&insn, ep, r);
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}
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/* Build an instruction created by a macro expansion. Like md_assemble but
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accept a printf-style format string and arguments. */
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static void
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md_assemblef (const char *format, ...)
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{
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char *buf = NULL;
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va_list ap;
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int r;
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va_start (ap, format);
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r = vasprintf (&buf, format, ap);
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if (r < 0)
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as_fatal (_("internal error: vasprintf failed"));
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md_assemble (buf);
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free(buf);
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va_end (ap);
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}
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/* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
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unset. */
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static void
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@ -1013,6 +1036,7 @@ static void
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load_const (int reg, expressionS *ep)
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{
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int shift = RISCV_IMM_BITS;
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bfd_vma upper_imm;
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expressionS upper = *ep, lower = *ep;
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lower.X_add_number = (int32_t) ep->X_add_number << (32-shift) >> (32-shift);
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upper.X_add_number -= lower.X_add_number;
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@ -1032,9 +1056,10 @@ load_const (int reg, expressionS *ep)
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upper.X_add_number = (int64_t) upper.X_add_number >> shift;
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load_const (reg, &upper);
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macro_build (NULL, "slli", "d,s,>", reg, reg, shift);
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md_assemblef ("slli x%d, x%d, 0x%x", reg, reg, shift);
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if (lower.X_add_number != 0)
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macro_build (&lower, "addi", "d,s,j", reg, reg, BFD_RELOC_RISCV_LO12_I);
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md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT "d", reg, reg,
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lower.X_add_number);
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}
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else
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{
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@ -1043,13 +1068,16 @@ load_const (int reg, expressionS *ep)
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if (upper.X_add_number != 0)
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{
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macro_build (ep, "lui", "d,u", reg, BFD_RELOC_RISCV_HI20);
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/* Discard low part and zero-extend upper immediate. */
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upper_imm = ((uint32_t)upper.X_add_number >> shift);
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md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT "x", reg, upper_imm);
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hi_reg = reg;
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}
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if (lower.X_add_number != 0 || hi_reg == 0)
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macro_build (ep, ADD32_INSN, "d,s,j", reg, hi_reg,
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BFD_RELOC_RISCV_LO12_I);
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md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT "d", ADD32_INSN, reg, hi_reg,
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lower.X_add_number);
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}
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}
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17
gas/testsuite/gas/riscv/li32.d
Normal file
17
gas/testsuite/gas/riscv/li32.d
Normal file
@ -0,0 +1,17 @@
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#as: -march=rv32ic -mabi=ilp32
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#objdump: -dr
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.*: file format elf32-littleriscv
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Disassembly of section .text:
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0+000 <target>:
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[^:]+:[ ]+6521[ ]+lui[ ]+a0,0x8
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[^:]+:[ ]+0505[ ]+addi[ ]+a0,a0,1
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[^:]+:[ ]+6509[ ]+lui[ ]+a0,0x2
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[^:]+:[ ]+f0150513[ ]+addi[ ]+a0,a0,-255 # .*
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[^:]+:[ ]+12345537[ ]+lui[ ]+a0,0x12345
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[^:]+:[ ]+0505[ ]+addi[ ]+a0,a0,1
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[^:]+:[ ]+f2345537[ ]+lui[ ]+a0,0xf2345
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[^:]+:[ ]+0505[ ]+addi[ ]+a0,a0,1
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5
gas/testsuite/gas/riscv/li32.s
Normal file
5
gas/testsuite/gas/riscv/li32.s
Normal file
@ -0,0 +1,5 @@
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target:
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li a0, 0x8001
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li a0, 0x1f01
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li a0, 0x12345001
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li a0, 0xf2345001
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44
gas/testsuite/gas/riscv/li64.d
Normal file
44
gas/testsuite/gas/riscv/li64.d
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@ -0,0 +1,44 @@
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#as: -march=rv64ic -mabi=lp64
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#objdump: -dr
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.*: file format elf64-littleriscv
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Disassembly of section .text:
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0000000000000000 <target>:
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[^:]+:[ ]+6521[ ]+lui[ ]+a0,0x8
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[^:]+:[ ]+2505[ ]+addiw[ ]+a0,a0,1
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[^:]+:[ ]+6509[ ]+lui[ ]+a0,0x2
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[^:]+:[ ]+f015051b[ ]+addiw[ ]+a0,a0,-255
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[^:]+:[ ]+12345537[ ]+lui[ ]+a0,0x12345
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[^:]+:[ ]+2505[ ]+addiw[ ]+a0,a0,1
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[^:]+:[ ]+000f2537[ ]+lui[ ]+a0,0xf2
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[^:]+:[ ]+3455051b[ ]+addiw[ ]+a0,a0,837
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[^:]+:[ ]+0532[ ]+slli[ ]+a0,a0,0xc
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[^:]+:[ ]+0505[ ]+addi[ ]+a0,a0,1
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[^:]+:[ ]+00f12537[ ]+lui[ ]+a0,0xf12
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[^:]+:[ ]+3455051b[ ]+addiw[ ]+a0,a0,837
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[^:]+:[ ]+0532[ ]+slli[ ]+a0,a0,0xc
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[^:]+:[ ]+0505[ ]+addi[ ]+a0,a0,1
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[^:]+:[ ]+ff010537[ ]+lui[ ]+a0,0xff010
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[^:]+:[ ]+f015051b[ ]+addiw[ ]+a0,a0,-255
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[^:]+:[ ]+054e[ ]+slli[ ]+a0,a0,0x13
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[^:]+:[ ]+80150513[ ]+addi[ ]+a0,a0,-2047 # .*
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[^:]+:[ ]+0536[ ]+slli[ ]+a0,a0,0xd
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[^:]+:[ ]+f0150513[ ]+addi[ ]+a0,a0,-255
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[^:]+:[ ]+0010051b[ ]+addiw[ ]+a0,zero,1
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[^:]+:[ ]+151a[ ]+slli[ ]+a0,a0,0x26
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[^:]+:[ ]+1565[ ]+addi[ ]+a0,a0,-7
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[^:]+:[ ]+0536[ ]+slli[ ]+a0,a0,0xd
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[^:]+:[ ]+34550513[ ]+addi[ ]+a0,a0,837
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[^:]+:[ ]+0532[ ]+slli[ ]+a0,a0,0xc
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[^:]+:[ ]+0505[ ]+addi[ ]+a0,a0,1
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[^:]+:[ ]+01fc4537[ ]+lui[ ]+a0,0x1fc4
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[^:]+:[ ]+c915051b[ ]+addiw[ ]+a0,a0,-879
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[^:]+:[ ]+0536[ ]+slli[ ]+a0,a0,0xd
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[^:]+:[ ]+1565[ ]+addi[ ]+a0,a0,-7
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[^:]+:[ ]+0536[ ]+slli[ ]+a0,a0,0xd
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[^:]+:[ ]+34550513[ ]+addi[ ]+a0,a0,837 # .*
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[^:]+:[ ]+0532[ ]+slli[ ]+a0,a0,0xc
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[^:]+:[ ]+0505[ ]+addi[ ]+a0,a0,1
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9
gas/testsuite/gas/riscv/li64.s
Normal file
9
gas/testsuite/gas/riscv/li64.s
Normal file
@ -0,0 +1,9 @@
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target:
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li a0, 0x8001
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li a0, 0x1f01
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li a0, 0x12345001
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li a0, 0xf2345001
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li a0, 0xf12345001
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li a0, 0xff00ff00ff001f01
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li a0, 0x7ffffffff2345001
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li a0, 0x7f0f243ff2345001
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