2003-10-09 Michael Snyder <msnyder@redhat.com>
* d10v-tdep.c: Random whitespace/comment tweaks.
This commit is contained in:
Michael Snyder
parent
2a7e019d6b
commit
db72fa6bdc
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@ -1,3 +1,7 @@
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2003-10-09 Michael Snyder <msnyder@redhat.com>
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* d10v-tdep.c: Random whitespace/comment tweaks.
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2003-10-09 Elena Zannoni <ezannoni@redhat.com>
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* sh-tdep.c (sh_gdbarch_init): Delete setting of push_dummy_code.
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@ -57,7 +57,7 @@ struct gdbarch_tdep
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};
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/* These are the addresses the D10V-EVA board maps data and
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instruction memory to. */
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instruction memory to. */
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enum memspace {
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DMEM_START = 0x2000000,
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@ -65,7 +65,7 @@ enum memspace {
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STACK_START = 0x200bffe
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};
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/* d10v register names. */
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/* d10v register names. */
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enum
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{
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@ -80,7 +80,7 @@ enum
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NR_A_REGS = 2,
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TS2_NUM_REGS = 37,
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TS3_NUM_REGS = 42,
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/* d10v calling convention. */
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/* d10v calling convention. */
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ARG1_REGNUM = R0_REGNUM,
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ARGN_REGNUM = R3_REGNUM,
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RET1_REGNUM = R0_REGNUM,
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@ -119,7 +119,7 @@ d10v_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
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and TYPE is the type (which is known to be struct, union or array).
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The d10v returns anything less than 8 bytes in size in
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registers. */
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registers. */
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static int
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d10v_use_struct_convention (int gcc_p, struct type *type)
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@ -127,25 +127,25 @@ d10v_use_struct_convention (int gcc_p, struct type *type)
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long alignment;
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int i;
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/* The d10v only passes a struct in a register when that structure
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has an alignment that matches the size of a register. */
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has an alignment that matches the size of a register. */
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/* If the structure doesn't fit in 4 registers, put it on the
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stack. */
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stack. */
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if (TYPE_LENGTH (type) > 8)
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return 1;
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/* If the struct contains only one field, don't put it on the stack
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- gcc can fit it in one or more registers. */
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- gcc can fit it in one or more registers. */
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if (TYPE_NFIELDS (type) == 1)
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return 0;
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alignment = TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0));
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for (i = 1; i < TYPE_NFIELDS (type); i++)
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{
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/* If the alignment changes, just assume it goes on the
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stack. */
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stack. */
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if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, i)) != alignment)
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return 1;
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}
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/* If the alignment is suitable for the d10v's 16 bit registers,
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don't put it on the stack. */
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don't put it on the stack. */
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if (alignment == 2 || alignment == 4)
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return 0;
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return 1;
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@ -162,7 +162,7 @@ d10v_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
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}
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/* Map the REG_NR onto an ascii name. Return NULL or an empty string
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when the reg_nr isn't valid. */
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when the reg_nr isn't valid. */
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enum ts2_regnums
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{
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@ -279,7 +279,7 @@ d10v_ts3_imap_register (void *regcache, int reg_nr)
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/* MAP GDB's internal register numbering (determined by the layout
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from the DEPRECATED_REGISTER_BYTE array) onto the simulator's
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register numbering. */
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register numbering. */
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static int
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d10v_ts2_register_sim_regno (int nr)
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@ -353,7 +353,7 @@ static CORE_ADDR
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d10v_make_iaddr (CORE_ADDR x)
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{
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if (d10v_iaddr_p (x))
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return x; /* Idempotency -- x is already in the IMEM space. */
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return x; /* Idempotency -- x is already in the IMEM space. */
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else
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return (((x) << 2) | IMEM_START);
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}
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@ -505,8 +505,8 @@ d10v_skip_prologue (CORE_ADDR pc)
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CORE_ADDR func_addr, func_end;
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struct symtab_and_line sal;
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/* If we have line debugging information, then the end of the */
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/* prologue should the first assembly instruction of the first source line */
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/* If we have line debugging information, then the end of the prologue
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should the first assembly instruction of the first source line */
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if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
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{
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sal = find_pc_line (func_addr, 0);
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@ -515,7 +515,7 @@ d10v_skip_prologue (CORE_ADDR pc)
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}
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if (target_read_memory (pc, (char *) &op, 4))
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return pc; /* Can't access it -- assume no prologue. */
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return pc; /* Can't access it -- assume no prologue. */
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while (1)
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{
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@ -545,8 +545,9 @@ d10v_skip_prologue (CORE_ADDR pc)
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{
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if (!check_prologue (op2))
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{
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/* if the previous opcode was really part of the prologue */
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/* and not just a NOP, then we want to break after both instructions */
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/* If the previous opcode was really part of the
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prologue and not just a NOP, then we want to
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break after both instructions. */
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if (op1 != 0x5E00)
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pc += 4;
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break;
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@ -657,7 +658,7 @@ prologue_find_regs (struct d10v_unwind_cache *info, unsigned short op,
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the saved registers of frame described by FRAME_INFO. This
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includes special registers such as pc and fp saved in special ways
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in the stack frame. sp is even more special: the address we return
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for it IS the sp for the next frame. */
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for it IS the sp for the next frame. */
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static struct d10v_unwind_cache *
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d10v_frame_unwind_cache (struct frame_info *next_frame,
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@ -908,7 +909,7 @@ d10v_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
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}
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/* When arguments must be pushed onto the stack, they go on in reverse
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order. The below implements a FILO (stack) to do this. */
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order. The below implements a FILO (stack) to do this. */
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struct stack_item
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{
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@ -965,8 +966,8 @@ d10v_push_dummy_code (struct gdbarch *gdbarch,
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static CORE_ADDR
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d10v_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
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struct regcache *regcache, CORE_ADDR bp_addr,
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int nargs, struct value **args, CORE_ADDR sp, int struct_return,
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CORE_ADDR struct_addr)
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int nargs, struct value **args, CORE_ADDR sp,
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int struct_return, CORE_ADDR struct_addr)
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{
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int i;
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int regnum = ARG1_REGNUM;
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@ -1063,7 +1064,7 @@ d10v_extract_return_value (struct type *type, struct regcache *regcache,
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least significant part of the first register. The
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remaining bytes in remaining registers. Interestingly, when
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such values are passed in, the last byte is in the most
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significant byte of that same register - wierd. */
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significant byte of that same register - wierd. */
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int reg = RET1_REGNUM;
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int off = 0;
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if (TYPE_LENGTH (type) & 1)
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@ -1086,7 +1087,7 @@ d10v_extract_return_value (struct type *type, struct regcache *regcache,
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understands. Returns number of bytes that can be transfered
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starting at TARG_ADDR. Return ZERO if no bytes can be transfered
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(segmentation fault). Since the simulator knows all about how the
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VM system works, we just call that to do the translation. */
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VM system works, we just call that to do the translation. */
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static void
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remote_d10v_translate_xfer_address (struct gdbarch *gdbarch,
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@ -1313,7 +1314,8 @@ tdisassemble_command (char *arg, int from_tty)
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}
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}
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printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low), paddr_u (high));
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printf_filtered ("Dump of trace from %s to %s:\n",
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paddr_u (low), paddr_u (high));
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display_trace (low, high);
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@ -1404,7 +1406,7 @@ d10v_frame_this_id (struct frame_info *next_frame,
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func = frame_func_unwind (next_frame);
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/* This is meant to halt the backtrace at "_start". Make sure we
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don't halt it at a generic dummy frame. */
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don't halt it at a generic dummy frame. */
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if (func <= IMEM_START || deprecated_inside_entry_file (func))
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return;
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@ -1483,13 +1485,13 @@ d10v_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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gdbarch_register_name_ftype *d10v_register_name;
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gdbarch_register_sim_regno_ftype *d10v_register_sim_regno;
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/* Find a candidate among the list of pre-declared architectures. */
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/* Find a candidate among the list of pre-declared architectures. */
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arches = gdbarch_list_lookup_by_info (arches, &info);
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if (arches != NULL)
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return arches->gdbarch;
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/* None found, create a new architecture from the information
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provided. */
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provided. */
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tdep = XMALLOC (struct gdbarch_tdep);
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gdbarch = gdbarch_alloc (&info, tdep);
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@ -1535,7 +1537,7 @@ d10v_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
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set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
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/* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long
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double'' is 64 bits. */
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double'' is 64 bits. */
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set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
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set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
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set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
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@ -1549,7 +1551,8 @@ d10v_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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case BFD_ENDIAN_LITTLE:
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set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little);
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set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_little);
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set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_little);
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set_gdbarch_long_double_format (gdbarch,
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&floatformat_ieee_double_little);
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break;
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default:
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internal_error (__FILE__, __LINE__,
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@ -1560,7 +1563,8 @@ d10v_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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set_gdbarch_push_dummy_code (gdbarch, d10v_push_dummy_code);
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set_gdbarch_push_dummy_call (gdbarch, d10v_push_dummy_call);
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set_gdbarch_store_return_value (gdbarch, d10v_store_return_value);
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set_gdbarch_extract_struct_value_address (gdbarch, d10v_extract_struct_value_address);
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set_gdbarch_extract_struct_value_address (gdbarch,
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d10v_extract_struct_value_address);
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set_gdbarch_use_struct_convention (gdbarch, d10v_use_struct_convention);
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set_gdbarch_skip_prologue (gdbarch, d10v_skip_prologue);
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@ -1569,10 +1573,12 @@ d10v_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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set_gdbarch_function_start_offset (gdbarch, 0);
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set_gdbarch_breakpoint_from_pc (gdbarch, d10v_breakpoint_from_pc);
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set_gdbarch_remote_translate_xfer_address (gdbarch, remote_d10v_translate_xfer_address);
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set_gdbarch_remote_translate_xfer_address (gdbarch,
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remote_d10v_translate_xfer_address);
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set_gdbarch_frame_args_skip (gdbarch, 0);
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set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
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set_gdbarch_frameless_function_invocation (gdbarch,
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frameless_look_for_prologue);
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set_gdbarch_frame_align (gdbarch, d10v_frame_align);
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@ -1604,7 +1610,8 @@ _initialize_d10v_tdep (void)
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target_resume_hook = d10v_eva_prepare_to_trace;
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target_wait_loop_hook = d10v_eva_get_trace_data;
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deprecate_cmd (add_com ("regs", class_vars, show_regs, "Print all registers"),
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deprecate_cmd (add_com ("regs", class_vars, show_regs,
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"Print all registers"),
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"info registers");
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add_com ("itrace", class_support, trace_command,
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