2011-03-10 Maxim Grigoriev <maxim2405@gmail.com>
* xtensa-tdep.c (xtensa_c0reg_t): Update comments. (xtensa_call0_frame_cache_t): Update comments. New fields added. (xtensa_alloc_frame_cache): Add initialization for new fields. (xtensa_frame_cache): Change the way how call0_frame_cache () is called. (warning_once): New function. (xtensa_insn_kind): New item c0opc_and. (call0_classify_opcode): Add the case for AND instruction. (call0_track_op): Change arguments. New local variable litbase. Add the case to handle c0opc_and. Update algorithms for c0opc_mov, c0opc_l32r, c0opc_s32i to take into account dynamic stack adjustments in prologue. Add cases for c0opc_l32e, c0opc_s32e, c0opc_rfwo, c0opc_rfwu. (call0_analyze_prologue): Update the comments. Change arguments. Add the variety of updates to handle extended prologues, which now can conduct dynamic stack adjustments. (call0_frame_cache): Likewise. (xtensa_skip_prologue): Update call0_analyze_prologue () function call. (xtensa_gdbarch_init): Initialize xtensa_session_once_reported.
This commit is contained in:
Maxim Grigoriev
parent
a00888a47b
commit
dbab50deda
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@ -1,3 +1,23 @@
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2011-03-10 Maxim Grigoriev <maxim2405@gmail.com>
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* xtensa-tdep.c (xtensa_c0reg_t): Update comments.
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(xtensa_call0_frame_cache_t): Update comments. New fields added.
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(xtensa_alloc_frame_cache): Add initialization for new fields.
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(xtensa_frame_cache): Change the way how call0_frame_cache () is called.
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(warning_once): New function.
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(xtensa_insn_kind): New item c0opc_and.
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(call0_classify_opcode): Add the case for AND instruction.
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(call0_track_op): Change arguments. New local variable litbase. Add the
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case to handle c0opc_and. Update algorithms for c0opc_mov, c0opc_l32r,
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c0opc_s32i to take into account dynamic stack adjustments in prologue.
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Add cases for c0opc_l32e, c0opc_s32e, c0opc_rfwo, c0opc_rfwu.
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(call0_analyze_prologue): Update the comments. Change arguments.
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Add the variety of updates to handle extended prologues, which now can
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conduct dynamic stack adjustments.
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(call0_frame_cache): Likewise.
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(xtensa_skip_prologue): Update call0_analyze_prologue () function call.
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(xtensa_gdbarch_init): Initialize xtensa_session_once_reported.
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2011-03-10 Michael Snyder <msnyder@vmware.com>
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* tracepoint.c (cmd_qtv): Discard unused value 'packet'.
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@ -57,7 +77,7 @@
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2011-03-09 Maxim Grigoriev <maxim2405@gmail.com>
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* xtensa-tdep.c (xtensa_read_register: Add comment.
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* xtensa-tdep.c (xtensa_read_register): Add comment.
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(xtensa_write_register): Likewise.
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(xtensa_hextochar): Add comment and update to match coding conventions.
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(xtensa_frame_cache, xtensa_return_value): Follow coding conventions.
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@ -982,24 +982,30 @@ extern xtensa_isa xtensa_default_isa;
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typedef struct xtensa_c0reg
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{
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int fr_reg; /* original register from which register content
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is derived, or C0_CONST, or C0_INEXP. */
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int fr_ofs; /* constant offset from reg, or immediate value. */
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int to_stk; /* offset from original SP to register (4-byte
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aligned), or C0_NOSTK if register has not
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been saved. */
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int fr_reg; /* original register from which register content
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is derived, or C0_CONST, or C0_INEXP. */
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int fr_ofs; /* constant offset from reg, or immediate value. */
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int to_stk; /* offset from original SP to register (4-byte aligned),
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or C0_NOSTK if register has not been saved. */
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} xtensa_c0reg_t;
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/* Frame cache part for Call0 ABI. */
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typedef struct xtensa_call0_frame_cache
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{
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int c0_frmsz; /* Stack frame size. */
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int c0_hasfp; /* Current frame uses frame
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pointer. */
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int fp_regnum; /* A-register used as FP. */
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int c0_fp; /* Actual value of frame pointer. */
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xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */
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int c0_frmsz; /* Stack frame size. */
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int c0_hasfp; /* Current frame uses frame pointer. */
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int fp_regnum; /* A-register used as FP. */
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int c0_fp; /* Actual value of frame pointer. */
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int c0_fpalign; /* Dinamic adjustment for the stack
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pointer. It's an AND mask. Zero,
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if alignment was not adjusted. */
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int c0_old_sp; /* In case of dynamic adjustment, it is
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a register holding unaligned sp.
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C0_INEXP, when undefined. */
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int c0_sp_ofs; /* If "c0_old_sp" was spilled it's a
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stack offset. C0_NOSTK otherwise. */
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xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */
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} xtensa_call0_frame_cache_t;
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typedef struct xtensa_frame_cache
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@ -1040,6 +1046,9 @@ xtensa_alloc_frame_cache (int windowed)
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cache->c0.c0_hasfp = 0;
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cache->c0.fp_regnum = -1;
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cache->c0.c0_fp = -1;
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cache->c0.c0_fpalign = 0;
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cache->c0.c0_old_sp = C0_INEXP;
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cache->c0.c0_sp_ofs = C0_NOSTK;
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for (i = 0; i < C0_NREGS; i++)
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{
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@ -1261,8 +1270,7 @@ done:
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static void
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call0_frame_cache (struct frame_info *this_frame,
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xtensa_frame_cache_t *cache,
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CORE_ADDR pc, CORE_ADDR litbase);
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xtensa_frame_cache_t *cache, CORE_ADDR pc);
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static void
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xtensa_window_interrupt_frame_cache (struct frame_info *this_frame,
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@ -1408,11 +1416,7 @@ xtensa_frame_cache (struct frame_info *this_frame, void **this_cache)
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}
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else /* Call0 framework. */
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{
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unsigned int litbase_regnum = gdbarch_tdep (gdbarch)->litbase_regnum;
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CORE_ADDR litbase = (litbase_regnum == -1)
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? 0 : get_frame_register_unsigned (this_frame, litbase_regnum);
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call0_frame_cache (this_frame, cache, pc, litbase);
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call0_frame_cache (this_frame, cache, pc);
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fp_regnum = cache->c0.fp_regnum;
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}
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@ -1421,6 +1425,22 @@ xtensa_frame_cache (struct frame_info *this_frame, void **this_cache)
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return cache;
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}
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static int xtensa_session_once_reported = 1;
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/* Report a problem with prologue analysis while doing backtracing.
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But, do it only once to avoid annoyng repeated messages. */
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static inline void warning_once ()
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{
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if (xtensa_session_once_reported == 0)
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warning (_("\
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\nUnrecognised function prologue. Stack trace cannot be resolved. \
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This message will not be repeated in this session.\n"));
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xtensa_session_once_reported = 1;
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}
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static void
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xtensa_frame_this_id (struct frame_info *this_frame,
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void **this_cache,
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@ -2088,6 +2108,7 @@ typedef enum
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c0opc_break, /* Debugger software breakpoints. */
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c0opc_add, /* Adding two registers. */
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c0opc_addi, /* Adding a register and an immediate. */
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c0opc_and, /* Bitwise "and"-ing two registers. */
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c0opc_sub, /* Subtracting a register from a register. */
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c0opc_mov, /* Moving a register to a register. */
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c0opc_movi, /* Moving an immediate to a register. */
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@ -2159,6 +2180,8 @@ call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc)
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else if (strcasecmp (opcname, "add") == 0
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|| strcasecmp (opcname, "add.n") == 0)
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opclass = c0opc_add;
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else if (strcasecmp (opcname, "and") == 0)
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opclass = c0opc_and;
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else if (strcasecmp (opcname, "addi") == 0
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|| strcasecmp (opcname, "addi.n") == 0
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|| strcasecmp (opcname, "addmi") == 0)
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@ -2190,16 +2213,16 @@ call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc)
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be within a bundle. Updates the destination register tracking info
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accordingly. The pc is needed only for pc-relative load instructions
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(eg. l32r). The SP register number is needed to identify stores to
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the stack frame. */
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the stack frame. Returns 0, if analysis was succesfull, non-zero
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otherwise. */
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static void
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call0_track_op (struct gdbarch *gdbarch,
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xtensa_c0reg_t dst[], xtensa_c0reg_t src[],
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static int
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call0_track_op (struct gdbarch *gdbarch, xtensa_c0reg_t dst[], xtensa_c0reg_t src[],
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xtensa_insn_kind opclass, int nods, unsigned odv[],
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CORE_ADDR pc, CORE_ADDR litbase, int spreg)
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CORE_ADDR pc, int spreg, xtensa_frame_cache_t *cache)
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{
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enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
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unsigned litaddr, litval;
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unsigned litbase, litaddr, litval;
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switch (opclass)
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{
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@ -2224,6 +2247,39 @@ call0_track_op (struct gdbarch *gdbarch,
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}
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else dst[odv[0]].fr_reg = C0_INEXP;
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break;
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case c0opc_and:
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/* 3 operands: dst, src1, src2. */
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gdb_assert (nods == 3);
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if (cache->c0.c0_fpalign == 0)
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{
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/* Handle dynamic stack alignment. */
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if ((src[odv[0]].fr_reg == spreg) && (src[odv[1]].fr_reg == spreg))
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{
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if (src[odv[2]].fr_reg == C0_CONST)
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cache->c0.c0_fpalign = src[odv[2]].fr_ofs;
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break;
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}
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else if ((src[odv[0]].fr_reg == spreg)
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&& (src[odv[2]].fr_reg == spreg))
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{
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if (src[odv[1]].fr_reg == C0_CONST)
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cache->c0.c0_fpalign = src[odv[1]].fr_ofs;
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break;
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}
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/* else fall through. */
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}
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if (src[odv[1]].fr_reg == C0_CONST)
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{
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dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
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dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs & src[odv[1]].fr_ofs;
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}
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else if (src[odv[2]].fr_reg == C0_CONST)
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{
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dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
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dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs & src[odv[2]].fr_ofs;
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}
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else dst[odv[0]].fr_reg = C0_INEXP;
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break;
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case c0opc_sub:
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/* 3 operands: dst, src1, src2. */
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gdb_assert (nods == 3);
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case c0opc_mov:
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/* 2 operands: dst, src [, src]. */
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gdb_assert (nods == 2);
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/* First, check if it's a special case of saving unaligned SP
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to a spare register in case of dynamic stack adjustment.
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But, only do it one time. The second time could be initializing
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frame pointer. We don't want to overwrite the first one. */
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if ((odv[1] == spreg) && (cache->c0.c0_old_sp == C0_INEXP))
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cache->c0.c0_old_sp = odv[0];
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dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
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dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs;
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break;
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@ -2249,6 +2312,10 @@ call0_track_op (struct gdbarch *gdbarch,
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case c0opc_l32r:
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/* 2 operands: dst, literal offset. */
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gdb_assert (nods == 2);
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/* litbase = xtensa_get_litbase (pc); can be also used. */
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litbase = (gdbarch_tdep (gdbarch)->litbase_regnum == -1)
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? 0 : xtensa_read_register
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(gdbarch_tdep (gdbarch)->litbase_regnum);
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litaddr = litbase & 1
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? (litbase & ~1) + (signed)odv[1]
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: (pc + 3 + (signed)odv[1]) & ~3;
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@ -2259,6 +2326,13 @@ call0_track_op (struct gdbarch *gdbarch,
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case c0opc_s32i:
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/* 3 operands: value, base, offset. */
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gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS);
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/* First, check if it's a spill for saved unaligned SP,
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when dynamic stack adjustment was applied to this frame. */
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if ((cache->c0.c0_fpalign != 0) /* Dynamic stack adjustment. */
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&& (odv[1] == spreg) /* SP usage indicates spill. */
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&& (odv[0] == cache->c0.c0_old_sp)) /* Old SP register spilled. */
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cache->c0.c0_sp_ofs = odv[2];
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if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */
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&& (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */
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&& src[odv[0]].fr_reg >= 0 /* Value is from a register. */
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@ -2270,20 +2344,29 @@ call0_track_op (struct gdbarch *gdbarch,
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dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2];
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}
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break;
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/* If we end up inside Window Overflow / Underflow interrupt handler
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report an error because these handlers should have been handled
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already in a different way. */
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case c0opc_l32e:
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case c0opc_s32e:
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case c0opc_rfwo:
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case c0opc_rfwu:
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return 1;
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default:
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gdb_assert_not_reached ("unexpected instruction kind");
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return 1;
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}
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return 0;
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}
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/* Analyze prologue of the function at start address to determine if it uses
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/* Analyze prologue of the function at start address to determine if it uses
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the Call0 ABI, and if so track register moves and linear modifications
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in the prologue up to the PC or just beyond the prologue, whichever is first.
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An 'entry' instruction indicates non-Call0 ABI and the end of the prologue.
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The prologue may overlap non-prologue instructions but is guaranteed to end
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by the first flow-control instruction (jump, branch, call or return).
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Since an optimized function may move information around and change the
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stack frame arbitrarily during the prologue, the information is guaranteed
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valid only at the point in the function indicated by the PC.
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in the prologue up to the PC or just beyond the prologue, whichever is
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first. An 'entry' instruction indicates non-Call0 ABI and the end of the
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prologue. The prologue may overlap non-prologue instructions but is
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guaranteed to end by the first flow-control instruction (jump, branch,
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call or return). Since an optimized function may move information around
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and change the stack frame arbitrarily during the prologue, the information
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is guaranteed valid only at the point in the function indicated by the PC.
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May be used to skip the prologue or identify the ABI, w/o tracking.
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Returns: Address of first instruction after prologue, or PC (whichever
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@ -2293,21 +2376,17 @@ call0_track_op (struct gdbarch *gdbarch,
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pc Program counter to stop at. Use 0 to continue to end of prologue.
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If 0, avoids infinite run-on in corrupt code memory by bounding
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the scan to the end of the function if that can be determined.
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nregs Number of general registers to track (size of rt[] array).
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nregs Number of general registers to track.
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InOut args:
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rt[] Array[nregs] of xtensa_c0reg structures for register tracking info.
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If NULL, registers are not tracked.
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Output args:
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call0 If != NULL, *call0 is set non-zero if Call0 ABI used, else 0
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(more accurately, non-zero until 'entry' insn is encountered).
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cache Xtensa frame cache.
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Note that these may produce useful results even if decoding fails
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because they begin with default assumptions that analysis may change. */
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static CORE_ADDR
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call0_analyze_prologue (struct gdbarch *gdbarch,
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CORE_ADDR start, CORE_ADDR pc, CORE_ADDR litbase,
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int nregs, xtensa_c0reg_t rt[], int *call0)
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CORE_ADDR start, CORE_ADDR pc,
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int nregs, xtensa_frame_cache_t *cache)
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{
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CORE_ADDR ia; /* Current insn address in prologue. */
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CORE_ADDR ba = 0; /* Current address at base of insn buffer. */
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@ -2359,15 +2438,8 @@ call0_analyze_prologue (struct gdbarch *gdbarch,
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else
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body_pc = min (pc, body_pc);
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if (call0 != NULL)
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*call0 = 1;
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if (rt != NULL)
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{
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rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t));
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/* rt is already initialized in xtensa_alloc_frame_cache(). */
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}
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else nregs = 0;
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cache->call0 = 1;
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rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t));
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if (!xtensa_default_isa)
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xtensa_default_isa = xtensa_isa_init (0, 0);
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@ -2386,9 +2458,8 @@ call0_analyze_prologue (struct gdbarch *gdbarch,
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{
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ba = ia;
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bt = (ba + XTENSA_ISA_BSZ) < body_pc ? ba + XTENSA_ISA_BSZ : body_pc;
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read_memory (ba, ibuf, bt - ba);
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/* If there is a memory reading error read_memory () will report it
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and then throw an exception, stopping command execution. */
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if (target_read_memory (ba, ibuf, bt - ba) != 0 )
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error (_("Unable to read target memory ..."));
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}
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/* Decode format information. */
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@ -2418,7 +2489,7 @@ call0_analyze_prologue (struct gdbarch *gdbarch,
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register changes do not take effect within this bundle. */
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for (j = 0; j < nregs; ++j)
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rtmp[j] = rt[j];
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rtmp[j] = cache->c0.c0_rt[j];
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for (is = 0; is < islots; ++is)
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{
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|
|
@ -2429,8 +2500,7 @@ call0_analyze_prologue (struct gdbarch *gdbarch,
|
|||
goto done;
|
||||
|
||||
opc = xtensa_opcode_decode (isa, ifmt, is, slot);
|
||||
DEBUGVERB ("[call0_analyze_prologue] instr "
|
||||
"addr = 0x%08x, opc = %d\n",
|
||||
DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
|
||||
(unsigned)ia, opc);
|
||||
if (opc == XTENSA_UNDEFINED)
|
||||
opclass = c0opc_illegal;
|
||||
|
|
@ -2449,23 +2519,20 @@ call0_analyze_prologue (struct gdbarch *gdbarch,
|
|||
case c0opc_uninteresting:
|
||||
continue;
|
||||
|
||||
case c0opc_flow:
|
||||
case c0opc_flow: /* Flow control instructions stop analysis. */
|
||||
case c0opc_rwxsr: /* RSR, WSR, XSR instructions stop analysis. */
|
||||
goto done;
|
||||
|
||||
case c0opc_entry:
|
||||
if (call0 != NULL)
|
||||
*call0 = 0;
|
||||
cache->call0 = 0;
|
||||
ia += ilen; /* Skip over 'entry' insn. */
|
||||
goto done;
|
||||
|
||||
default:
|
||||
if (call0 != NULL)
|
||||
*call0 = 1;
|
||||
cache->call0 = 1;
|
||||
}
|
||||
|
||||
/* Only expected opcodes should get this far. */
|
||||
if (rt == NULL)
|
||||
continue;
|
||||
|
||||
/* Extract and decode the operands. */
|
||||
nods = xtensa_opcode_num_operands (isa, opc);
|
||||
|
|
@ -2491,7 +2558,13 @@ call0_analyze_prologue (struct gdbarch *gdbarch,
|
|||
if (opclass == c0opc_mov && nods == 3)
|
||||
{
|
||||
if (odv[2] == odv[1])
|
||||
nods = 2;
|
||||
{
|
||||
nods = 2;
|
||||
if ((odv[0] == 1) && (odv[1] != 1))
|
||||
/* OR A1, An, An , where n != 1.
|
||||
This means we are inside epilogue already. */
|
||||
goto done;
|
||||
}
|
||||
else
|
||||
{
|
||||
opclass = c0opc_uninteresting;
|
||||
|
|
@ -2500,8 +2573,10 @@ call0_analyze_prologue (struct gdbarch *gdbarch,
|
|||
}
|
||||
|
||||
/* Track register movement and modification for this operation. */
|
||||
call0_track_op (gdbarch, rt, rtmp, opclass,
|
||||
nods, odv, ia, litbase, 1);
|
||||
fail = call0_track_op (gdbarch, cache->c0.c0_rt, rtmp,
|
||||
opclass, nods, odv, ia, 1, cache);
|
||||
if (fail)
|
||||
goto done;
|
||||
}
|
||||
}
|
||||
done:
|
||||
|
|
@ -2516,39 +2591,38 @@ done:
|
|||
|
||||
static void
|
||||
call0_frame_cache (struct frame_info *this_frame,
|
||||
xtensa_frame_cache_t *cache,
|
||||
CORE_ADDR pc, CORE_ADDR litbase)
|
||||
xtensa_frame_cache_t *cache, CORE_ADDR pc)
|
||||
{
|
||||
struct gdbarch *gdbarch = get_frame_arch (this_frame);
|
||||
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
|
||||
CORE_ADDR start_pc; /* The beginning of the function. */
|
||||
CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */
|
||||
CORE_ADDR sp, fp, ra;
|
||||
int fp_regnum, c0_hasfp, c0_frmsz, prev_sp, to_stk;
|
||||
int fp_regnum = C0_SP, c0_hasfp = 0, c0_frmsz = 0, prev_sp = 0, to_stk;
|
||||
|
||||
sp = get_frame_register_unsigned
|
||||
(this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
|
||||
fp = sp; /* Assume FP == SP until proven otherwise. */
|
||||
|
||||
/* Find the beginning of the prologue of the function containing the PC
|
||||
and analyze it up to the PC or the end of the prologue. */
|
||||
|
||||
if (find_pc_partial_function (pc, NULL, &start_pc, NULL))
|
||||
{
|
||||
body_pc = call0_analyze_prologue (gdbarch, start_pc, pc, litbase,
|
||||
C0_NREGS,
|
||||
&cache->c0.c0_rt[0],
|
||||
&cache->call0);
|
||||
body_pc = call0_analyze_prologue (gdbarch, start_pc, pc, C0_NREGS, cache);
|
||||
|
||||
if (body_pc == XTENSA_ISA_BADPC)
|
||||
error (_("Xtensa-specific internal error: CALL0 prologue \
|
||||
analysis failed in this frame. GDB command execution stopped."));
|
||||
{
|
||||
warning_once ();
|
||||
ra = 0;
|
||||
goto finish_frame_analysis;
|
||||
}
|
||||
}
|
||||
|
||||
sp = get_frame_register_unsigned
|
||||
(this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
|
||||
fp = sp; /* Assume FP == SP until proven otherwise. */
|
||||
|
||||
/* Get the frame information and FP (if used) at the current PC.
|
||||
If PC is in the prologue, the prologue analysis is more reliable
|
||||
than DWARF info. We don't not know for sure if PC is in the prologue,
|
||||
but we know no calls have yet taken place, so we can almost
|
||||
than DWARF info. We don't not know for sure, if PC is in the prologue,
|
||||
but we do know no calls have yet taken place, so we can almost
|
||||
certainly rely on the prologue analysis. */
|
||||
|
||||
if (body_pc <= pc)
|
||||
|
|
@ -2571,7 +2645,35 @@ analysis failed in this frame. GDB command execution stopped."));
|
|||
start_pc = pc;
|
||||
}
|
||||
|
||||
prev_sp = fp + c0_frmsz;
|
||||
if (cache->c0.c0_fpalign)
|
||||
{
|
||||
/* This frame has a special prologue with a dynamic stack adjustment
|
||||
to force an alignment, which is bigger than standard 16 bytes. */
|
||||
|
||||
CORE_ADDR unaligned_sp;
|
||||
|
||||
if (cache->c0.c0_old_sp == C0_INEXP)
|
||||
/* This can't be. Prologue code should be consistent.
|
||||
Unaligned stack pointer should be saved in a spare register. */
|
||||
{
|
||||
warning_once ();
|
||||
ra = 0;
|
||||
goto finish_frame_analysis;
|
||||
}
|
||||
|
||||
if (cache->c0.c0_sp_ofs == C0_NOSTK)
|
||||
/* Saved unaligned value of SP is kept in a register. */
|
||||
unaligned_sp = get_frame_register_unsigned
|
||||
(this_frame, gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_old_sp);
|
||||
else
|
||||
/* Get the value from stack. */
|
||||
unaligned_sp = (CORE_ADDR)
|
||||
read_memory_integer (fp + cache->c0.c0_sp_ofs, 4, byte_order);
|
||||
|
||||
prev_sp = unaligned_sp + c0_frmsz;
|
||||
}
|
||||
else
|
||||
prev_sp = fp + c0_frmsz;
|
||||
|
||||
/* Frame size from debug info or prologue tracking does not account for
|
||||
alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
|
||||
|
|
@ -2579,8 +2681,6 @@ analysis failed in this frame. GDB command execution stopped."));
|
|||
{
|
||||
fp = get_frame_register_unsigned (this_frame, fp_regnum);
|
||||
|
||||
/* Recalculate previous SP. */
|
||||
prev_sp = fp + c0_frmsz;
|
||||
/* Update the stack frame size. */
|
||||
c0_frmsz += fp - sp;
|
||||
}
|
||||
|
|
@ -2597,23 +2697,21 @@ analysis failed in this frame. GDB command execution stopped."));
|
|||
else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST
|
||||
&& cache->c0.c0_rt[C0_RA].fr_ofs == 0)
|
||||
{
|
||||
/* Special case for terminating backtrace at a function that
|
||||
wants to be seen as the outermost. Such a function will
|
||||
clear it's RA (A0) register to 0 in the prologue instead of
|
||||
saving its original value. */
|
||||
/* Special case for terminating backtrace at a function that wants to
|
||||
be seen as the outermost one. Such a function will clear it's RA (A0)
|
||||
register to 0 in the prologue instead of saving its original value. */
|
||||
ra = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* RA was copied to another register or (before any function
|
||||
call) may still be in the original RA register. This is not
|
||||
always reliable: even in a leaf function, register tracking
|
||||
stops after prologue, and even in prologue, non-prologue
|
||||
instructions (not tracked) may overwrite RA or any register
|
||||
it was copied to. If likely in prologue or before any call,
|
||||
use retracking info and hope for the best (compiler should
|
||||
have saved RA in stack if not in a leaf function). If not in
|
||||
prologue, too bad. */
|
||||
/* RA was copied to another register or (before any function call) may
|
||||
still be in the original RA register. This is not always reliable:
|
||||
even in a leaf function, register tracking stops after prologue, and
|
||||
even in prologue, non-prologue instructions (not tracked) may overwrite
|
||||
RA or any register it was copied to. If likely in prologue or before
|
||||
any call, use retracking info and hope for the best (compiler should
|
||||
have saved RA in stack if not in a leaf function). If not in prologue,
|
||||
too bad. */
|
||||
|
||||
int i;
|
||||
for (i = 0;
|
||||
|
|
@ -2631,6 +2729,7 @@ analysis failed in this frame. GDB command execution stopped."));
|
|||
else ra = 0;
|
||||
}
|
||||
|
||||
finish_frame_analysis:
|
||||
cache->pc = start_pc;
|
||||
cache->ra = ra;
|
||||
/* RA == 0 marks the outermost frame. Do not go past it. */
|
||||
|
|
@ -2971,7 +3070,8 @@ xtensa_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
|
|||
}
|
||||
|
||||
/* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
|
||||
body_pc = call0_analyze_prologue (gdbarch, start_pc, 0, 0, 0, NULL, NULL);
|
||||
body_pc = call0_analyze_prologue (gdbarch, start_pc, 0, 0,
|
||||
xtensa_alloc_frame_cache (0));
|
||||
return body_pc != 0 ? body_pc : start_pc;
|
||||
}
|
||||
|
||||
|
|
@ -3122,6 +3222,7 @@ xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
|
|||
|
||||
/* Verify our configuration. */
|
||||
xtensa_verify_config (gdbarch);
|
||||
xtensa_session_once_reported = 0;
|
||||
|
||||
/* Pseudo-Register read/write. */
|
||||
set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read);
|
||||
|
|
|
|||
Loading…
Reference in New Issue