x86: replace Reg8, Reg16, Reg32, and Reg64
Use a combination of a single new Reg bit and Byte, Word, Dword, or Qword instead. Besides shrinking the number of operand type bits this has the benefit of making register handling more similar to accumulator handling (a generic flag is being accompanied by a "size qualifier"). It requires, however, to split a few insn templates, as it is no longer correct to have combinations like Reg32|Reg64|Byte. This slight growth in size will hopefully be outweighed by this change paving the road for folding a presumably much larger number of templates later on.
This commit is contained in:
Jan Beulich
Jan Beulich
parent
eccab96d54
commit
dc821c5f9a
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@ -1,3 +1,23 @@
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2017-12-18 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (operand_type_check, pi): Switch .reg<N> to
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just .reg.
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(operand_size_match): Qualify .anysize check with .reg one.
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Extend .acc check to also cover .reg.
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(operand_type_register_match): Drop m0 and m1 parameters. Switch
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.reg<N> to .byte/.word/.dword/.qword. Drop .acc special
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handling.
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(md_assemble): Expand .reg8 checks to .reg plus .bytes ones.
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(optimize_imm, process_suffix, check_byte_reg, check_long_reg,
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check_qword_reg, check_word_reg): Expand .reg<N> checks to .reg
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plus size ones.
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(match_template): Drop arguments from calls to
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operand_type_register_match().
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(build_modrm_byte, i386_addressing_mode, i386_index_check,
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parse_real_register): Replace .reg<N> checks.
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* config/tc-i386-intel.c (i386_intel_simplify,
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i386_intel_operand): Switch .reg16 to .word.
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2017-12-17 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/22623
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@ -451,7 +451,7 @@ static int i386_intel_simplify (expressionS *e)
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{
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resolve_expression (scale);
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if (scale->X_op != O_constant
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|| intel_state.index->reg_type.bitfield.reg16)
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|| intel_state.index->reg_type.bitfield.word)
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scale->X_add_number = 0;
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intel_state.scale_factor *= scale->X_add_number;
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}
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@ -897,8 +897,8 @@ i386_intel_operand (char *operand_string, int got_a_float)
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mode we have to do this here. */
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if (intel_state.base
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&& intel_state.index
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&& intel_state.base->reg_type.bitfield.reg16
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&& intel_state.index->reg_type.bitfield.reg16
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&& intel_state.base->reg_type.bitfield.word
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&& intel_state.index->reg_type.bitfield.word
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&& intel_state.base->reg_num >= 6
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&& intel_state.index->reg_num < 6)
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{
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@ -1775,10 +1775,7 @@ operand_type_check (i386_operand_type t, enum operand_type c)
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switch (c)
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{
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case reg:
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return (t.bitfield.reg8
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|| t.bitfield.reg16
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|| t.bitfield.reg32
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|| t.bitfield.reg64);
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return t.bitfield.reg;
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case imm:
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return (t.bitfield.imm8
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@ -1867,10 +1864,12 @@ operand_size_match (const insn_template *t)
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/* Check memory and accumulator operand size. */
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for (j = 0; j < i.operands; j++)
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{
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if (t->operand_types[j].bitfield.anysize)
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if (!i.types[j].bitfield.reg && t->operand_types[j].bitfield.anysize)
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continue;
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if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
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if ((t->operand_types[j].bitfield.reg
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|| t->operand_types[j].bitfield.acc)
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&& !match_reg_size (t, j))
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{
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match = 0;
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break;
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@ -1898,7 +1897,8 @@ mismatch:
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match = 1;
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for (j = 0; j < 2; j++)
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{
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if (t->operand_types[j].bitfield.acc
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if ((t->operand_types[j].bitfield.reg
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|| t->operand_types[j].bitfield.acc)
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&& !match_reg_size (t, j ? 0 : 1))
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goto mismatch;
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@ -1940,14 +1940,11 @@ mismatch:
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}
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/* If given types g0 and g1 are registers they must be of the same type
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unless the expected operand type register overlap is null.
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Note that Acc in a template matches every size of reg. */
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unless the expected operand type register overlap is null. */
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static INLINE int
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operand_type_register_match (i386_operand_type m0,
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i386_operand_type g0,
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operand_type_register_match (i386_operand_type g0,
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i386_operand_type t0,
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i386_operand_type m1,
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i386_operand_type g1,
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i386_operand_type t1)
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{
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@ -1957,32 +1954,16 @@ operand_type_register_match (i386_operand_type m0,
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if (!operand_type_check (g1, reg))
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return 1;
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if (g0.bitfield.reg8 == g1.bitfield.reg8
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&& g0.bitfield.reg16 == g1.bitfield.reg16
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&& g0.bitfield.reg32 == g1.bitfield.reg32
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&& g0.bitfield.reg64 == g1.bitfield.reg64)
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if (g0.bitfield.byte == g1.bitfield.byte
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&& g0.bitfield.word == g1.bitfield.word
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&& g0.bitfield.dword == g1.bitfield.dword
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&& g0.bitfield.qword == g1.bitfield.qword)
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return 1;
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if (m0.bitfield.acc)
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{
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t0.bitfield.reg8 = 1;
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t0.bitfield.reg16 = 1;
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t0.bitfield.reg32 = 1;
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t0.bitfield.reg64 = 1;
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}
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if (m1.bitfield.acc)
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{
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t1.bitfield.reg8 = 1;
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t1.bitfield.reg16 = 1;
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t1.bitfield.reg32 = 1;
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t1.bitfield.reg64 = 1;
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}
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if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
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&& !(t0.bitfield.reg16 & t1.bitfield.reg16)
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&& !(t0.bitfield.reg32 & t1.bitfield.reg32)
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&& !(t0.bitfield.reg64 & t1.bitfield.reg64))
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if (!(t0.bitfield.byte & t1.bitfield.byte)
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&& !(t0.bitfield.word & t1.bitfield.word)
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&& !(t0.bitfield.dword & t1.bitfield.dword)
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&& !(t0.bitfield.qword & t1.bitfield.qword))
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return 1;
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i.error = register_type_mismatch;
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@ -2821,10 +2802,7 @@ pi (char *line, i386_insn *x)
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fprintf (stdout, " #%d: ", j + 1);
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pt (x->types[j]);
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fprintf (stdout, "\n");
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if (x->types[j].bitfield.reg8
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|| x->types[j].bitfield.reg16
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|| x->types[j].bitfield.reg32
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|| x->types[j].bitfield.reg64
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if (x->types[j].bitfield.reg
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|| x->types[j].bitfield.regmmx
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|| x->types[j].bitfield.regxmm
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|| x->types[j].bitfield.regymm
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@ -3856,12 +3834,12 @@ md_assemble (char *line)
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instruction already has a prefix, we need to convert old
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registers to new ones. */
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if ((i.types[0].bitfield.reg8
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if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
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&& (i.op[0].regs->reg_flags & RegRex64) != 0)
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|| (i.types[1].bitfield.reg8
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|| (i.types[1].bitfield.reg && i.types[1].bitfield.byte
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&& (i.op[1].regs->reg_flags & RegRex64) != 0)
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|| ((i.types[0].bitfield.reg8
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|| i.types[1].bitfield.reg8)
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|| (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
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|| (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
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&& i.rex != 0))
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{
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int x;
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@ -3870,7 +3848,7 @@ md_assemble (char *line)
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for (x = 0; x < 2; x++)
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{
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/* Look for 8 bit operand that uses old registers. */
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if (i.types[x].bitfield.reg8
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if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
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&& (i.op[x].regs->reg_flags & RegRex64) == 0)
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{
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/* In case it is "hi" register, give up. */
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@ -4377,22 +4355,22 @@ optimize_imm (void)
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but the following works for instructions with immediates.
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In any case, we can't set i.suffix yet. */
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for (op = i.operands; --op >= 0;)
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if (i.types[op].bitfield.reg8)
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if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
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{
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guess_suffix = BYTE_MNEM_SUFFIX;
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break;
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}
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else if (i.types[op].bitfield.reg16)
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else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
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{
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guess_suffix = WORD_MNEM_SUFFIX;
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break;
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}
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else if (i.types[op].bitfield.reg32)
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else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
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{
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guess_suffix = LONG_MNEM_SUFFIX;
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break;
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}
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else if (i.types[op].bitfield.reg64)
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else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
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{
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guess_suffix = QWORD_MNEM_SUFFIX;
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break;
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@ -5084,9 +5062,9 @@ match_template (char mnem_suffix)
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if (!operand_type_match (overlap0, i.types[0])
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|| !operand_type_match (overlap1, i.types[1])
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|| (check_register
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&& !operand_type_register_match (overlap0, i.types[0],
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&& !operand_type_register_match (i.types[0],
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operand_types[0],
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overlap1, i.types[1],
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i.types[1],
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operand_types[1])))
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{
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/* Check if other direction is valid ... */
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@ -5100,10 +5078,8 @@ check_reverse:
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if (!operand_type_match (overlap0, i.types[0])
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|| !operand_type_match (overlap1, i.types[1])
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|| (check_register
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&& !operand_type_register_match (overlap0,
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i.types[0],
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&& !operand_type_register_match (i.types[0],
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operand_types[1],
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overlap1,
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i.types[1],
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operand_types[0])))
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{
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@ -5144,10 +5120,8 @@ check_reverse:
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{
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case 5:
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if (!operand_type_match (overlap4, i.types[4])
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|| !operand_type_register_match (overlap3,
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i.types[3],
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|| !operand_type_register_match (i.types[3],
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operand_types[3],
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overlap4,
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i.types[4],
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operand_types[4]))
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continue;
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@ -5155,10 +5129,8 @@ check_reverse:
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case 4:
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if (!operand_type_match (overlap3, i.types[3])
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|| (check_register
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&& !operand_type_register_match (overlap2,
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i.types[2],
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&& !operand_type_register_match (i.types[2],
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operand_types[2],
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overlap3,
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i.types[3],
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operand_types[3])))
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continue;
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@ -5170,10 +5142,8 @@ check_reverse:
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register consistency between operands 2 and 3. */
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if (!operand_type_match (overlap2, i.types[2])
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|| (check_register
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&& !operand_type_register_match (overlap1,
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i.types[1],
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&& !operand_type_register_match (i.types[1],
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operand_types[1],
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overlap2,
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i.types[2],
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operand_types[2])))
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continue;
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@ -5381,16 +5351,16 @@ process_suffix (void)
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type. */
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if (i.tm.base_opcode == 0xf20f38f1)
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{
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if (i.types[0].bitfield.reg16)
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if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
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i.suffix = WORD_MNEM_SUFFIX;
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else if (i.types[0].bitfield.reg32)
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else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
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i.suffix = LONG_MNEM_SUFFIX;
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else if (i.types[0].bitfield.reg64)
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else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
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i.suffix = QWORD_MNEM_SUFFIX;
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}
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else if (i.tm.base_opcode == 0xf20f38f0)
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{
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if (i.types[0].bitfield.reg8)
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if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
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i.suffix = BYTE_MNEM_SUFFIX;
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}
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@ -5411,22 +5381,22 @@ process_suffix (void)
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if (!i.tm.operand_types[op].bitfield.inoutportreg
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&& !i.tm.operand_types[op].bitfield.shiftcount)
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{
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if (i.types[op].bitfield.reg8)
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if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
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{
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i.suffix = BYTE_MNEM_SUFFIX;
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break;
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}
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else if (i.types[op].bitfield.reg16)
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if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
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{
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i.suffix = WORD_MNEM_SUFFIX;
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break;
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}
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else if (i.types[op].bitfield.reg32)
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if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
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{
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i.suffix = LONG_MNEM_SUFFIX;
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break;
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}
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else if (i.types[op].bitfield.reg64)
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if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
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{
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i.suffix = QWORD_MNEM_SUFFIX;
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break;
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@ -5583,9 +5553,9 @@ process_suffix (void)
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/* The address size override prefix changes the size of the
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first operand. */
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if ((flag_code == CODE_32BIT
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&& i.op->regs[0].reg_type.bitfield.reg16)
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&& i.op->regs[0].reg_type.bitfield.word)
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|| (flag_code != CODE_32BIT
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&& i.op->regs[0].reg_type.bitfield.reg32))
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&& i.op->regs[0].reg_type.bitfield.dword))
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if (!add_prefix (ADDR_PREFIX_OPCODE))
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return 0;
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}
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@ -5642,10 +5612,14 @@ check_byte_reg (void)
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for (op = i.operands; --op >= 0;)
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{
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/* Skip non-register operands. */
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if (!i.types[op].bitfield.reg)
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continue;
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/* If this is an eight bit register, it's OK. If it's the 16 or
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32 bit version of an eight bit register, we will just use the
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low portion, and that's OK too. */
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if (i.types[op].bitfield.reg8)
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if (i.types[op].bitfield.byte)
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continue;
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/* I/O port address operands are OK too. */
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|
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@ -5656,9 +5630,9 @@ check_byte_reg (void)
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if (i.tm.base_opcode == 0xf20f38f0)
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continue;
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if ((i.types[op].bitfield.reg16
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|| i.types[op].bitfield.reg32
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|| i.types[op].bitfield.reg64)
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if ((i.types[op].bitfield.word
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|| i.types[op].bitfield.dword
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|| i.types[op].bitfield.qword)
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&& i.op[op].regs->reg_num < 4
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/* Prohibit these changes in 64bit mode, since the lowering
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would be more complicated. */
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|
|
@ -5668,7 +5642,7 @@ check_byte_reg (void)
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if (!quiet_warnings)
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as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
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register_prefix,
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(i.op[op].regs + (i.types[op].bitfield.reg16
|
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(i.op[op].regs + (i.types[op].bitfield.word
|
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? REGNAM_AL - REGNAM_AX
|
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: REGNAM_AL - REGNAM_EAX))->reg_name,
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register_prefix,
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|
|
@ -5678,9 +5652,7 @@ check_byte_reg (void)
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continue;
|
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}
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/* Any other register is bad. */
|
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if (i.types[op].bitfield.reg16
|
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|| i.types[op].bitfield.reg32
|
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|| i.types[op].bitfield.reg64
|
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if (i.types[op].bitfield.reg
|
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|| i.types[op].bitfield.regmmx
|
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|| i.types[op].bitfield.regxmm
|
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|| i.types[op].bitfield.regymm
|
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|
|
@ -5710,12 +5682,16 @@ check_long_reg (void)
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int op;
|
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|
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for (op = i.operands; --op >= 0;)
|
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/* Skip non-register operands. */
|
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if (!i.types[op].bitfield.reg)
|
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continue;
|
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/* Reject eight bit registers, except where the template requires
|
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them. (eg. movzb) */
|
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if (i.types[op].bitfield.reg8
|
||||
&& (i.tm.operand_types[op].bitfield.reg16
|
||||
|| i.tm.operand_types[op].bitfield.reg32
|
||||
|| i.tm.operand_types[op].bitfield.acc))
|
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else if (i.types[op].bitfield.byte
|
||||
&& (i.tm.operand_types[op].bitfield.reg
|
||||
|| i.tm.operand_types[op].bitfield.acc)
|
||||
&& (i.tm.operand_types[op].bitfield.word
|
||||
|| i.tm.operand_types[op].bitfield.dword))
|
||||
{
|
||||
as_bad (_("`%s%s' not allowed with `%s%c'"),
|
||||
register_prefix,
|
||||
|
|
@ -5726,9 +5702,10 @@ check_long_reg (void)
|
|||
}
|
||||
/* Warn if the e prefix on a general reg is missing. */
|
||||
else if ((!quiet_warnings || flag_code == CODE_64BIT)
|
||||
&& i.types[op].bitfield.reg16
|
||||
&& (i.tm.operand_types[op].bitfield.reg32
|
||||
|| i.tm.operand_types[op].bitfield.acc))
|
||||
&& i.types[op].bitfield.word
|
||||
&& (i.tm.operand_types[op].bitfield.reg
|
||||
|| i.tm.operand_types[op].bitfield.acc)
|
||||
&& i.tm.operand_types[op].bitfield.dword)
|
||||
{
|
||||
/* Prohibit these changes in the 64bit mode, since the
|
||||
lowering is more complicated. */
|
||||
|
|
@ -5747,9 +5724,10 @@ check_long_reg (void)
|
|||
#endif
|
||||
}
|
||||
/* Warn if the r prefix on a general reg is present. */
|
||||
else if (i.types[op].bitfield.reg64
|
||||
&& (i.tm.operand_types[op].bitfield.reg32
|
||||
|| i.tm.operand_types[op].bitfield.acc))
|
||||
else if (i.types[op].bitfield.qword
|
||||
&& (i.tm.operand_types[op].bitfield.reg
|
||||
|| i.tm.operand_types[op].bitfield.acc)
|
||||
&& i.tm.operand_types[op].bitfield.dword)
|
||||
{
|
||||
if (intel_syntax
|
||||
&& i.tm.opcode_modifier.toqword
|
||||
|
|
@ -5775,12 +5753,16 @@ check_qword_reg (void)
|
|||
int op;
|
||||
|
||||
for (op = i.operands; --op >= 0; )
|
||||
/* Skip non-register operands. */
|
||||
if (!i.types[op].bitfield.reg)
|
||||
continue;
|
||||
/* Reject eight bit registers, except where the template requires
|
||||
them. (eg. movzb) */
|
||||
if (i.types[op].bitfield.reg8
|
||||
&& (i.tm.operand_types[op].bitfield.reg16
|
||||
|| i.tm.operand_types[op].bitfield.reg32
|
||||
|| i.tm.operand_types[op].bitfield.acc))
|
||||
else if (i.types[op].bitfield.byte
|
||||
&& (i.tm.operand_types[op].bitfield.reg
|
||||
|| i.tm.operand_types[op].bitfield.acc)
|
||||
&& (i.tm.operand_types[op].bitfield.word
|
||||
|| i.tm.operand_types[op].bitfield.dword))
|
||||
{
|
||||
as_bad (_("`%s%s' not allowed with `%s%c'"),
|
||||
register_prefix,
|
||||
|
|
@ -5790,10 +5772,11 @@ check_qword_reg (void)
|
|||
return 0;
|
||||
}
|
||||
/* Warn if the r prefix on a general reg is missing. */
|
||||
else if ((i.types[op].bitfield.reg16
|
||||
|| i.types[op].bitfield.reg32)
|
||||
&& (i.tm.operand_types[op].bitfield.reg64
|
||||
|| i.tm.operand_types[op].bitfield.acc))
|
||||
else if ((i.types[op].bitfield.word
|
||||
|| i.types[op].bitfield.dword)
|
||||
&& (i.tm.operand_types[op].bitfield.reg
|
||||
|| i.tm.operand_types[op].bitfield.acc)
|
||||
&& i.tm.operand_types[op].bitfield.qword)
|
||||
{
|
||||
/* Prohibit these changes in the 64bit mode, since the
|
||||
lowering is more complicated. */
|
||||
|
|
@ -5820,12 +5803,16 @@ check_word_reg (void)
|
|||
{
|
||||
int op;
|
||||
for (op = i.operands; --op >= 0;)
|
||||
/* Skip non-register operands. */
|
||||
if (!i.types[op].bitfield.reg)
|
||||
continue;
|
||||
/* Reject eight bit registers, except where the template requires
|
||||
them. (eg. movzb) */
|
||||
if (i.types[op].bitfield.reg8
|
||||
&& (i.tm.operand_types[op].bitfield.reg16
|
||||
|| i.tm.operand_types[op].bitfield.reg32
|
||||
|| i.tm.operand_types[op].bitfield.acc))
|
||||
else if (i.types[op].bitfield.byte
|
||||
&& (i.tm.operand_types[op].bitfield.reg
|
||||
|| i.tm.operand_types[op].bitfield.acc)
|
||||
&& (i.tm.operand_types[op].bitfield.word
|
||||
|| i.tm.operand_types[op].bitfield.dword))
|
||||
{
|
||||
as_bad (_("`%s%s' not allowed with `%s%c'"),
|
||||
register_prefix,
|
||||
|
|
@ -5836,10 +5823,11 @@ check_word_reg (void)
|
|||
}
|
||||
/* Warn if the e or r prefix on a general reg is present. */
|
||||
else if ((!quiet_warnings || flag_code == CODE_64BIT)
|
||||
&& (i.types[op].bitfield.reg32
|
||||
|| i.types[op].bitfield.reg64)
|
||||
&& (i.tm.operand_types[op].bitfield.reg16
|
||||
|| i.tm.operand_types[op].bitfield.acc))
|
||||
&& (i.types[op].bitfield.dword
|
||||
|| i.types[op].bitfield.qword)
|
||||
&& (i.tm.operand_types[op].bitfield.reg
|
||||
|| i.tm.operand_types[op].bitfield.acc)
|
||||
&& i.tm.operand_types[op].bitfield.word)
|
||||
{
|
||||
/* Prohibit these changes in the 64bit mode, since the
|
||||
lowering is more complicated. */
|
||||
|
|
@ -6458,8 +6446,8 @@ build_modrm_byte (void)
|
|||
op = i.tm.operand_types[vvvv];
|
||||
op.bitfield.regmem = 0;
|
||||
if ((dest + 1) >= i.operands
|
||||
|| (!op.bitfield.reg32
|
||||
&& !op.bitfield.reg64
|
||||
|| ((!op.bitfield.reg
|
||||
|| (!op.bitfield.dword && !op.bitfield.qword))
|
||||
&& !operand_type_equal (&op, ®xmm)
|
||||
&& !operand_type_equal (&op, ®ymm)
|
||||
&& !operand_type_equal (&op, ®zmm)
|
||||
|
|
@ -6639,7 +6627,7 @@ build_modrm_byte (void)
|
|||
if (! i.disp_operands)
|
||||
fake_zero_displacement = 1;
|
||||
}
|
||||
else if (i.base_reg->reg_type.bitfield.reg16)
|
||||
else if (i.base_reg->reg_type.bitfield.word)
|
||||
{
|
||||
gas_assert (!i.tm.opcode_modifier.vecsib);
|
||||
switch (i.base_reg->reg_num)
|
||||
|
|
@ -6819,10 +6807,7 @@ build_modrm_byte (void)
|
|||
unsigned int vex_reg = ~0;
|
||||
|
||||
for (op = 0; op < i.operands; op++)
|
||||
if (i.types[op].bitfield.reg8
|
||||
|| i.types[op].bitfield.reg16
|
||||
|| i.types[op].bitfield.reg32
|
||||
|| i.types[op].bitfield.reg64
|
||||
if (i.types[op].bitfield.reg
|
||||
|| i.types[op].bitfield.regmmx
|
||||
|| i.types[op].bitfield.regxmm
|
||||
|| i.types[op].bitfield.regymm
|
||||
|
|
@ -6892,8 +6877,8 @@ build_modrm_byte (void)
|
|||
{
|
||||
i386_operand_type *type = &i.tm.operand_types[vex_reg];
|
||||
|
||||
if (type->bitfield.reg32 != 1
|
||||
&& type->bitfield.reg64 != 1
|
||||
if ((!type->bitfield.reg
|
||||
|| (!type->bitfield.dword && !type->bitfield.qword))
|
||||
&& !operand_type_equal (type, ®xmm)
|
||||
&& !operand_type_equal (type, ®ymm)
|
||||
&& !operand_type_equal (type, ®zmm)
|
||||
|
|
@ -7357,7 +7342,7 @@ check_prefix:
|
|||
==> need second modrm byte. */
|
||||
if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
|
||||
&& i.rm.mode != 3
|
||||
&& !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
|
||||
&& !(i.base_reg && i.base_reg->reg_type.bitfield.word))
|
||||
FRAG_APPEND_1_CHAR ((i.sib.base << 0
|
||||
| i.sib.index << 3
|
||||
| i.sib.scale << 6));
|
||||
|
|
@ -8626,10 +8611,10 @@ i386_addressing_mode (void)
|
|||
{
|
||||
if (addr_reg->reg_num == RegEip
|
||||
|| addr_reg->reg_num == RegEiz
|
||||
|| addr_reg->reg_type.bitfield.reg32)
|
||||
|| addr_reg->reg_type.bitfield.dword)
|
||||
addr_mode = CODE_32BIT;
|
||||
else if (flag_code != CODE_64BIT
|
||||
&& addr_reg->reg_type.bitfield.reg16)
|
||||
&& addr_reg->reg_type.bitfield.word)
|
||||
addr_mode = CODE_16BIT;
|
||||
|
||||
if (addr_mode != flag_code)
|
||||
|
|
@ -8708,10 +8693,10 @@ i386_index_check (const char *operand_string)
|
|||
if (i.mem_operands
|
||||
&& i.base_reg
|
||||
&& !((addr_mode == CODE_64BIT
|
||||
&& i.base_reg->reg_type.bitfield.reg64)
|
||||
&& i.base_reg->reg_type.bitfield.qword)
|
||||
|| (addr_mode == CODE_32BIT
|
||||
? i.base_reg->reg_type.bitfield.reg32
|
||||
: i.base_reg->reg_type.bitfield.reg16)))
|
||||
? i.base_reg->reg_type.bitfield.dword
|
||||
: i.base_reg->reg_type.bitfield.word)))
|
||||
goto bad_address;
|
||||
|
||||
as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
|
||||
|
|
@ -8737,8 +8722,8 @@ bad_address:
|
|||
/* 32-bit/64-bit checks. */
|
||||
if ((i.base_reg
|
||||
&& (addr_mode == CODE_64BIT
|
||||
? !i.base_reg->reg_type.bitfield.reg64
|
||||
: !i.base_reg->reg_type.bitfield.reg32)
|
||||
? !i.base_reg->reg_type.bitfield.qword
|
||||
: !i.base_reg->reg_type.bitfield.dword)
|
||||
&& (i.index_reg
|
||||
|| (i.base_reg->reg_num
|
||||
!= (addr_mode == CODE_64BIT ? RegRip : RegEip))))
|
||||
|
|
@ -8747,9 +8732,9 @@ bad_address:
|
|||
&& !i.index_reg->reg_type.bitfield.regymm
|
||||
&& !i.index_reg->reg_type.bitfield.regzmm
|
||||
&& ((addr_mode == CODE_64BIT
|
||||
? !(i.index_reg->reg_type.bitfield.reg64
|
||||
? !(i.index_reg->reg_type.bitfield.qword
|
||||
|| i.index_reg->reg_num == RegRiz)
|
||||
: !(i.index_reg->reg_type.bitfield.reg32
|
||||
: !(i.index_reg->reg_type.bitfield.dword
|
||||
|| i.index_reg->reg_num == RegEiz))
|
||||
|| !i.index_reg->reg_type.bitfield.baseindex)))
|
||||
goto bad_address;
|
||||
|
|
@ -8775,10 +8760,10 @@ bad_address:
|
|||
{
|
||||
/* 16-bit checks. */
|
||||
if ((i.base_reg
|
||||
&& (!i.base_reg->reg_type.bitfield.reg16
|
||||
&& (!i.base_reg->reg_type.bitfield.word
|
||||
|| !i.base_reg->reg_type.bitfield.baseindex))
|
||||
|| (i.index_reg
|
||||
&& (!i.index_reg->reg_type.bitfield.reg16
|
||||
&& (!i.index_reg->reg_type.bitfield.word
|
||||
|| !i.index_reg->reg_type.bitfield.baseindex
|
||||
|| !(i.base_reg
|
||||
&& i.base_reg->reg_num < 6
|
||||
|
|
@ -9781,7 +9766,7 @@ parse_real_register (char *reg_string, char **end_op)
|
|||
if (operand_type_all_zero (&r->reg_type))
|
||||
return (const reg_entry *) NULL;
|
||||
|
||||
if ((r->reg_type.bitfield.reg32
|
||||
if ((r->reg_type.bitfield.dword
|
||||
|| r->reg_type.bitfield.sreg3
|
||||
|| r->reg_type.bitfield.control
|
||||
|| r->reg_type.bitfield.debug
|
||||
|
|
@ -9830,7 +9815,7 @@ parse_real_register (char *reg_string, char **end_op)
|
|||
}
|
||||
|
||||
if (((r->reg_flags & (RegRex64 | RegRex))
|
||||
|| r->reg_type.bitfield.reg64)
|
||||
|| r->reg_type.bitfield.qword)
|
||||
&& (!cpu_arch_flags.bitfield.cpulm
|
||||
|| !operand_type_equal (&r->reg_type, &control))
|
||||
&& flag_code != CODE_64BIT)
|
||||
|
|
|
|||
|
|
@ -1,3 +1,23 @@
|
|||
2017-12-18 Jan Beulich <jbeulich@suse.com>
|
||||
|
||||
* i386-gen.c (operand_type_shorthands): New.
|
||||
(opcode_modifiers): Replace Reg<N> with just Reg.
|
||||
(set_bitfield_from_cpu_flag_init): Rename to
|
||||
set_bitfield_from_shorthand. Drop value parameter. Process
|
||||
operand_type_shorthands.
|
||||
(set_bitfield): Adjust call accordingly.
|
||||
* i386-opc.h (enum of operand types): Replace Reg<N> with just
|
||||
Reg.
|
||||
(union i386_operand_type): Replace reg<N> with just reg.
|
||||
* i386-opc.tbl (extractps, pextrb, pextrw, pinsrb, pinsrw,
|
||||
vextractps, vpextrb, vpextrw, vpinsrb, vpinsrw): Split into
|
||||
separate register and memory forms.
|
||||
* i386-reg.tbl (al): Drop Byte.
|
||||
(ax): Drop Word.
|
||||
(eax): Drop Dword.
|
||||
(rax): Drop Qword.
|
||||
* i386-init.h, i386-tbl.h: Re-generate.
|
||||
|
||||
2017-12-15 Dimitar Dimitrov <dimitar@dinux.eu>
|
||||
|
||||
* disassemble.c (disassemble_init_for_target): Don't put PRU
|
||||
|
|
|
|||
|
|
@ -335,6 +335,14 @@ static initializer cpu_flag_init[] =
|
|||
"CpuAVX512_BITALG" },
|
||||
};
|
||||
|
||||
static const initializer operand_type_shorthands[] =
|
||||
{
|
||||
{ "Reg8", "Reg|Byte" },
|
||||
{ "Reg16", "Reg|Word" },
|
||||
{ "Reg32", "Reg|Dword" },
|
||||
{ "Reg64", "Reg|Qword" },
|
||||
};
|
||||
|
||||
static initializer operand_type_init[] =
|
||||
{
|
||||
{ "OPERAND_TYPE_NONE",
|
||||
|
|
@ -631,10 +639,7 @@ static bitfield opcode_modifiers[] =
|
|||
|
||||
static bitfield operand_types[] =
|
||||
{
|
||||
BITFIELD (Reg8),
|
||||
BITFIELD (Reg16),
|
||||
BITFIELD (Reg32),
|
||||
BITFIELD (Reg64),
|
||||
BITFIELD (Reg),
|
||||
BITFIELD (FloatReg),
|
||||
BITFIELD (RegMMX),
|
||||
BITFIELD (RegXMM),
|
||||
|
|
@ -789,9 +794,8 @@ next_field (char *str, char sep, char **next, char *last)
|
|||
static void set_bitfield (char *, bitfield *, int, unsigned int, int);
|
||||
|
||||
static int
|
||||
set_bitfield_from_cpu_flag_init (char *f, bitfield *array,
|
||||
int value, unsigned int size,
|
||||
int lineno)
|
||||
set_bitfield_from_shorthand (char *f, bitfield *array, unsigned int size,
|
||||
int lineno)
|
||||
{
|
||||
char *str, *next, *last;
|
||||
unsigned int i;
|
||||
|
|
@ -812,6 +816,22 @@ set_bitfield_from_cpu_flag_init (char *f, bitfield *array,
|
|||
return 0;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE (operand_type_shorthands); i++)
|
||||
if (strcmp (operand_type_shorthands[i].name, f) == 0)
|
||||
{
|
||||
/* Turn on selective bits. */
|
||||
char *init = xstrdup (operand_type_shorthands[i].init);
|
||||
last = init + strlen (init);
|
||||
for (next = init; next && next < last; )
|
||||
{
|
||||
str = next_field (next, '|', &next, last);
|
||||
if (str)
|
||||
set_bitfield (str, array, 1, size, lineno);
|
||||
}
|
||||
free (init);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
|
@ -862,8 +882,8 @@ set_bitfield (char *f, bitfield *array, int value,
|
|||
}
|
||||
}
|
||||
|
||||
/* Handle CPU_XXX_FLAGS. */
|
||||
if (!set_bitfield_from_cpu_flag_init (f, array, value, size, lineno))
|
||||
/* Handle shorthands. */
|
||||
if (value == 1 && !set_bitfield_from_shorthand (f, array, size, lineno))
|
||||
return;
|
||||
|
||||
if (lineno != -1)
|
||||
|
|
|
|||
|
|
@ -1174,254 +1174,254 @@
|
|||
#define OPERAND_TYPE_NONE \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG8 \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG16 \
|
||||
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG32 \
|
||||
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG64 \
|
||||
{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM1 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM8 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM8S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_BASEINDEX \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP8 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP16 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_INOUTPORTREG \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_SHIFTCOUNT \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_CONTROL \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_TEST \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DEBUG \
|
||||
{ { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_FLOATREG \
|
||||
{ { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_FLOATACC \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_SREG2 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_SREG3 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_JUMPABSOLUTE \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGMMX \
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGXMM \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGYMM \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
{ { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGZMM \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGMASK \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ESSEG \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC32 \
|
||||
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC64 \
|
||||
{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_INOUTPORTREG \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG16_INOUTPORTREG \
|
||||
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP16_32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ANYDISP \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32_32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_DISP32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM64_DISP64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_64_DISP32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_64_DISP32_64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, \
|
||||
0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_VEC_IMM4 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }
|
||||
0, 0, 0, 0, 1, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGBND \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } }
|
||||
0, 0, 0, 0, 0, 1, 0 } }
|
||||
|
|
|
|||
|
|
@ -685,14 +685,8 @@ typedef struct i386_opcode_modifier
|
|||
|
||||
enum
|
||||
{
|
||||
/* 8bit register */
|
||||
Reg8 = 0,
|
||||
/* 16bit register */
|
||||
Reg16,
|
||||
/* 32bit register */
|
||||
Reg32,
|
||||
/* 64bit register */
|
||||
Reg64,
|
||||
/* Register (qualified by Byte, Word, etc) */
|
||||
Reg = 0,
|
||||
/* Floating pointer stack register */
|
||||
FloatReg,
|
||||
/* MMX register */
|
||||
|
|
@ -814,10 +808,7 @@ typedef union i386_operand_type
|
|||
{
|
||||
struct
|
||||
{
|
||||
unsigned int reg8:1;
|
||||
unsigned int reg16:1;
|
||||
unsigned int reg32:1;
|
||||
unsigned int reg64:1;
|
||||
unsigned int reg:1;
|
||||
unsigned int floatreg:1;
|
||||
unsigned int regmmx:1;
|
||||
unsigned int regxmm:1;
|
||||
|
|
|
|||
|
|
@ -1269,13 +1269,18 @@ pavgw, 2, 0xfe3, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_
|
|||
pavgw, 2, 0x66e3, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
|
||||
pavgw, 2, 0x660fe3, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
|
||||
pextrw, 3, 0x66c5, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64 }
|
||||
pextrw, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64|Word|Unspecified|BaseIndex }
|
||||
pextrw, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64|RegMem }
|
||||
pextrw, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Word|Unspecified|BaseIndex }
|
||||
pextrw, 3, 0x660fc5, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64 }
|
||||
pextrw, 3, 0x660f3a15, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|Word|Unspecified|BaseIndex }
|
||||
pextrw, 3, 0x660f3a15, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|RegMem }
|
||||
pextrw, 3, 0x660f3a15, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Word|Unspecified|BaseIndex }
|
||||
pextrw, 3, 0xfc5, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|NoAVX, { Imm8, RegMMX, Reg32|Reg64 }
|
||||
pinsrw, 3, 0x66c4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, Reg32|Reg64|Word|Unspecified|BaseIndex, RegXMM }
|
||||
pinsrw, 3, 0x660fc4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64|Word|Unspecified|BaseIndex, RegXMM }
|
||||
pinsrw, 3, 0xfc4, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|NoAVX, { Imm8, Reg32|Reg64|Word|Unspecified|BaseIndex, RegMMX }
|
||||
pinsrw, 3, 0x66c4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, Reg32|Reg64, RegXMM }
|
||||
pinsrw, 3, 0x66c4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SSE2AVX, { Imm8, Word|Unspecified|BaseIndex, RegXMM }
|
||||
pinsrw, 3, 0x660fc4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64, RegXMM }
|
||||
pinsrw, 3, 0x660fc4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM }
|
||||
pinsrw, 3, 0xfc4, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|NoAVX, { Imm8, Reg32|Reg64, RegMMX }
|
||||
pinsrw, 3, 0xfc4, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoAVX, { Imm8, Word|Unspecified|BaseIndex, RegMMX }
|
||||
pmaxsw, 2, 0x66ee, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
|
||||
pmaxsw, 2, 0x660fee, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
|
||||
pmaxsw, 2, 0xfee, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX }
|
||||
|
|
@ -1656,8 +1661,10 @@ dppd, 3, 0x6641, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreS
|
|||
dppd, 3, 0x660f3a41, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
|
||||
dpps, 3, 0x6640, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
|
||||
dpps, 3, 0x660f3a40, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
|
||||
extractps, 3, 0x6617, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64|Dword|Unspecified|BaseIndex }
|
||||
extractps, 3, 0x660f3a17, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|Dword|Unspecified|BaseIndex }
|
||||
extractps, 3, 0x6617, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
|
||||
extractps, 3, 0x6617, None, 1, CpuAVX|Cpu64, Modrm|Vex|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg64|RegMem }
|
||||
extractps, 3, 0x660f3a17, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
|
||||
extractps, 3, 0x660f3a17, None, 3, CpuSSE4_1|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg64|RegMem }
|
||||
insertps, 3, 0x6621, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
|
||||
insertps, 3, 0x660f3a21, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
|
||||
movntdqa, 2, 0x662a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex, RegXMM }
|
||||
|
|
@ -1674,16 +1681,20 @@ pblendw, 3, 0x660e, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|Igno
|
|||
pblendw, 3, 0x660f3a0e, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
|
||||
pcmpeqq, 2, 0x6629, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
|
||||
pcmpeqq, 2, 0x660f3829, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
|
||||
pextrb, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64|Byte|Unspecified|BaseIndex }
|
||||
pextrb, 3, 0x660f3a14, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|Byte|Unspecified|BaseIndex }
|
||||
pextrb, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64|RegMem }
|
||||
pextrb, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Byte|Unspecified|BaseIndex }
|
||||
pextrb, 3, 0x660f3a14, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|RegMem }
|
||||
pextrb, 3, 0x660f3a14, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Byte|Unspecified|BaseIndex }
|
||||
pextrd, 3, 0x6616, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
|
||||
pextrd, 3, 0x660f3a16, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
|
||||
pextrq, 3, 0x6616, None, 1, CpuAVX|Cpu64, Modrm|Vex|VexOpcode=2|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Reg64|Qword|Unspecified|BaseIndex }
|
||||
pextrq, 3, 0x660f3a16, None, 3, CpuSSE4_1|Cpu64, Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|Qword|Unspecified|BaseIndex }
|
||||
phminposuw, 2, 0x6641, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
|
||||
phminposuw, 2, 0x660f3841, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
|
||||
pinsrb, 3, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, Reg32|Reg64|Byte|Unspecified|BaseIndex, RegXMM }
|
||||
pinsrb, 3, 0x660f3a20, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64|Byte|Unspecified|BaseIndex, RegXMM }
|
||||
pinsrb, 3, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, Reg32|Reg64, RegXMM }
|
||||
pinsrb, 3, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Byte|Unspecified|BaseIndex, RegXMM }
|
||||
pinsrb, 3, 0x660f3a20, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64, RegXMM }
|
||||
pinsrb, 3, 0x660f3a20, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM }
|
||||
pinsrd, 3, 0x6622, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Reg32|Dword|Unspecified|BaseIndex, RegXMM }
|
||||
pinsrd, 3, 0x660f3a22, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Dword|Unspecified|BaseIndex, RegXMM }
|
||||
pinsrq, 3, 0x6622, None, 1, CpuAVX|Cpu64, Modrm|Vex|VexOpcode=2|Size64|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, Reg64|Qword|Unspecified|BaseIndex, RegXMM }
|
||||
|
|
@ -2103,7 +2114,8 @@ vdppd, 4, 0x6641, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|Ignore
|
|||
vdpps, 4, 0x6640, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vdpps, 4, 0x6640, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
|
||||
vextractf128, 3, 0x6619, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, Xmmword|Unspecified|BaseIndex|RegXMM }
|
||||
vextractps, 3, 0x6617, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|Dword|Unspecified|BaseIndex }
|
||||
vextractps, 3, 0x6617, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
|
||||
vextractps, 3, 0x6617, None, 1, CpuAVX|Cpu64, Modrm|Vex|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg64|RegMem }
|
||||
vhaddpd, 3, 0x667c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vhaddpd, 3, 0x667c, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
|
||||
vhaddps, 3, 0xf27c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
|
|
@ -2266,11 +2278,13 @@ vpermilps, 3, 0x660c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|Ig
|
|||
vpermilps, 3, 0x660c, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
|
||||
vpermilps, 3, 0x6604, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM }
|
||||
vpermilps, 3, 0x6604, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Ymmword|Unspecified|BaseIndex|RegYMM, RegYMM }
|
||||
vpextrb, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|Byte|Unspecified|BaseIndex }
|
||||
vpextrb, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|RegMem }
|
||||
vpextrb, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Byte|Unspecified|BaseIndex }
|
||||
vpextrd, 3, 0x6616, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
|
||||
vpextrq, 3, 0x6616, None, 1, CpuAVX|Cpu64, Modrm|Vex|VexOpcode=2|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|Qword|Unspecified|BaseIndex }
|
||||
vpextrw, 3, 0x66c5, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64 }
|
||||
vpextrw, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|Word|Unspecified|BaseIndex }
|
||||
vpextrw, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|RegMem }
|
||||
vpextrw, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Word|Unspecified|BaseIndex }
|
||||
vphaddd, 3, 0x6602, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vphaddsw, 3, 0x6603, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vphaddw, 3, 0x6601, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
|
|
@ -2278,10 +2292,12 @@ vphminposuw, 2, 0x6641, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize
|
|||
vphsubd, 3, 0x6606, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vphsubsw, 3, 0x6607, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vphsubw, 3, 0x6605, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vpinsrb, 4, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64|Byte|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpinsrb, 4, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
|
||||
vpinsrb, 4, 0x6620, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpinsrd, 4, 0x6622, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpinsrq, 4, 0x6622, None, 1, CpuAVX|Cpu64, Modrm|Vex|VexOpcode=2|Size64|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg64|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpinsrw, 4, 0x66c4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpinsrw, 4, 0x66c4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
|
||||
vpinsrw, 4, 0x66c4, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpmaddubsw, 3, 0x6604, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vpmaddwd, 3, 0x66f5, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
vpmaxsb, 3, 0x663c, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
|
||||
|
|
@ -3779,7 +3795,8 @@ vextractf64x4, 3, 0x661B, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|VexOpcode=
|
|||
vextracti64x4, 3, 0x663B, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=2|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM, RegYMM|RegMem }
|
||||
vextracti64x4, 3, 0x663B, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|VexOpcode=2|VexW=2|VecESize=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM, YMMword|Unspecified|BaseIndex }
|
||||
|
||||
vextractps, 3, 0x6617, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=2|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|Reg32|Dword|Unspecified|BaseIndex }
|
||||
vextractps, 3, 0x6617, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=2|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
|
||||
vextractps, 3, 0x6617, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=2|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|RegMem }
|
||||
|
||||
vfixupimmpd, 4, 0x6654, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|Broadcast=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|Qword|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
|
||||
vfixupimmpd, 5, 0x6654, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=2|VexVVVV=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegZMM, RegZMM, RegZMM }
|
||||
|
|
@ -5708,12 +5725,16 @@ vpsrldq, 3, 0x6673, 3, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|VexOpcode=0|VexV
|
|||
vpsrldq, 3, 0x6673, 3, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|VexOpcode=0|VexVVVV=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, YMMword|Unspecified|BaseIndex, RegYMM }
|
||||
|
||||
vpextrw, 3, 0x66C5, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 }
|
||||
vpinsrw, 4, 0x66C4, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Reg64|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpinsrw, 4, 0x66C4, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
|
||||
vpinsrw, 4, 0x66C4, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
|
||||
vpextrb, 3, 0x6614, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64|Byte|Unspecified|BaseIndex }
|
||||
vpinsrb, 4, 0x6620, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Reg64|Byte|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
vpextrb, 3, 0x6614, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64|RegMem }
|
||||
vpextrb, 3, 0x6614, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Byte|Unspecified|BaseIndex }
|
||||
vpinsrb, 4, 0x6620, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM }
|
||||
vpinsrb, 4, 0x6620, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
|
||||
vpextrw, 3, 0x6615, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64|Word|Unspecified|BaseIndex }
|
||||
vpextrw, 3, 0x6615, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64|RegMem }
|
||||
vpextrw, 3, 0x6615, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Word|Unspecified|BaseIndex }
|
||||
|
||||
vpmaddwd, 3, 0x66F5, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex, RegZMM, RegZMM }
|
||||
vpmaddwd, 3, 0x66F5, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex, RegXMM, RegXMM }
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
// Make %st first as we test for it.
|
||||
st, FloatReg|FloatAcc, 0, 0, 11, 33
|
||||
// 8 bit regs
|
||||
al, Reg8|Acc|Byte, 0, 0, Dw2Inval, Dw2Inval
|
||||
al, Reg8|Acc, 0, 0, Dw2Inval, Dw2Inval
|
||||
cl, Reg8|ShiftCount, 0, 1, Dw2Inval, Dw2Inval
|
||||
dl, Reg8, 0, 2, Dw2Inval, Dw2Inval
|
||||
bl, Reg8, 0, 3, Dw2Inval, Dw2Inval
|
||||
|
|
@ -46,7 +46,7 @@ r13b, Reg8, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval
|
|||
r14b, Reg8, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval
|
||||
r15b, Reg8, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval
|
||||
// 16 bit regs
|
||||
ax, Reg16|Acc|Word, 0, 0, Dw2Inval, Dw2Inval
|
||||
ax, Reg16|Acc, 0, 0, Dw2Inval, Dw2Inval
|
||||
cx, Reg16, 0, 1, Dw2Inval, Dw2Inval
|
||||
dx, Reg16|InOutPortReg, 0, 2, Dw2Inval, Dw2Inval
|
||||
bx, Reg16|BaseIndex, 0, 3, Dw2Inval, Dw2Inval
|
||||
|
|
@ -63,7 +63,7 @@ r13w, Reg16, RegRex, 5, Dw2Inval, Dw2Inval
|
|||
r14w, Reg16, RegRex, 6, Dw2Inval, Dw2Inval
|
||||
r15w, Reg16, RegRex, 7, Dw2Inval, Dw2Inval
|
||||
// 32 bit regs
|
||||
eax, Reg32|BaseIndex|Acc|Dword, 0, 0, 0, Dw2Inval
|
||||
eax, Reg32|BaseIndex|Acc, 0, 0, 0, Dw2Inval
|
||||
ecx, Reg32|BaseIndex, 0, 1, 1, Dw2Inval
|
||||
edx, Reg32|BaseIndex, 0, 2, 2, Dw2Inval
|
||||
ebx, Reg32|BaseIndex, 0, 3, 3, Dw2Inval
|
||||
|
|
@ -79,7 +79,7 @@ r12d, Reg32|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval
|
|||
r13d, Reg32|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval
|
||||
r14d, Reg32|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval
|
||||
r15d, Reg32|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval
|
||||
rax, Reg64|BaseIndex|Acc|Qword, 0, 0, Dw2Inval, 0
|
||||
rax, Reg64|BaseIndex|Acc, 0, 0, Dw2Inval, 0
|
||||
rcx, Reg64|BaseIndex, 0, 1, Dw2Inval, 2
|
||||
rdx, Reg64|BaseIndex, 0, 2, Dw2Inval, 1
|
||||
rbx, Reg64|BaseIndex, 0, 3, Dw2Inval, 3
|
||||
|
|
|
|||
66656
opcodes/i386-tbl.h
66656
opcodes/i386-tbl.h
File diff suppressed because it is too large
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Reference in New Issue