PowerPC add initial -mfuture instruction support
This patch adds initial 64-bit insn assembler/disassembler support. The only instruction added is "pnop" along with the automatic aligning of prefix instruction so they do not cross 64-byte boundaries. include/ * dis-asm.h (WIDE_OUTPUT): Define. * opcode/ppc.h (prefix_opcodes, prefix_num_opcodes): Declare. (PPC_OPCODE_POWERXX, PPC_GET_PREFIX, PPC_GET_SUFFIX), (PPC_PREFIX_P, PPC_PREFIX_SEG): Define. opcodes/ * ppc-dis.c (ppc_opts): Add "future" entry. (PREFIX_OPCD_SEGS): Define. (prefix_opcd_indices): New array. (disassemble_init_powerpc): Initialize prefix_opcd_indices. (lookup_prefix): New function. (print_insn_powerpc): Handle 64-bit prefix instructions. * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK), (PMRR, POWERXX): Define. (prefix_opcodes): New instruction table. (prefix_num_opcodes): New constant. binutils/ * objdump.c (disassemble_bytes): Set WIDE_OUTPUT in flags. gas/ * config/tc-ppc.c (ppc_setup_opcodes): Handle prefix_opcodes. (struct insn_label_list): New. (insn_labels, free_insn_labels): New variables. (ppc_record_label, ppc_clear_labels, ppc_start_line_hook): New funcs. (ppc_frob_label, ppc_new_dot_label): Move functions earlier in file and call ppc_record_label. (md_assemble): Handle 64-bit prefix instructions. Align labels that are on the same line as a prefix instruction. * config/tc-ppc.h (tc_frob_label, ppc_frob_label): Move to later in the file. (md_start_line_hook): Define. (ppc_start_line_hook): Declare. * testsuite/gas/ppc/prefix-align.d, * testsuite/gas/ppc/prefix-align.s: New test. * testsuite/gas/ppc/ppc.exp: Run new test.
This commit is contained in:
Peter Bergner
Alan Modra
parent
fcb36d7462
commit
dd7efa7915
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@ -1,3 +1,7 @@
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2019-05-24 Alan Modra <amodra@gmail.com>
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* objdump.c (disassemble_bytes): Set WIDE_OUTPUT in flags.
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2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
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* MAINTAINERS: Add myself as the maintainer for BPF.
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@ -1946,7 +1946,8 @@ disassemble_bytes (struct disassemble_info * inf,
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inf->stream = &sfile;
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inf->bytes_per_line = 0;
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inf->bytes_per_chunk = 0;
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inf->flags = disassemble_all ? DISASSEMBLE_DATA : 0;
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inf->flags = ((disassemble_all ? DISASSEMBLE_DATA : 0)
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| (wide_output ? WIDE_OUTPUT : 0));
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if (machine)
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inf->flags |= USER_SPECIFIED_MACHINE_TYPE;
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@ -1,3 +1,22 @@
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2019-05-24 Peter Bergner <bergner@linux.ibm.com>
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Alan Modra <amodra@gmail.com>
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* config/tc-ppc.c (ppc_setup_opcodes): Handle prefix_opcodes.
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(struct insn_label_list): New.
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(insn_labels, free_insn_labels): New variables.
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(ppc_record_label, ppc_clear_labels, ppc_start_line_hook): New funcs.
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(ppc_frob_label, ppc_new_dot_label): Move functions earlier in file
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and call ppc_record_label.
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(md_assemble): Handle 64-bit prefix instructions. Align labels
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that are on the same line as a prefix instruction.
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* config/tc-ppc.h (tc_frob_label, ppc_frob_label): Move to
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later in the file.
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(md_start_line_hook): Define.
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(ppc_start_line_hook): Declare.
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* testsuite/gas/ppc/prefix-align.d,
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* testsuite/gas/ppc/prefix-align.s: New test.
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* testsuite/gas/ppc/ppc.exp: Run new test.
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2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
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* configure.ac: Handle bpf-*-* targets.
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@ -1673,6 +1673,50 @@ ppc_setup_opcodes (void)
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for (op = powerpc_opcodes; op < op_end; op++)
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hash_insert (ppc_hash, op->name, (void *) op);
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op_end = prefix_opcodes + prefix_num_opcodes;
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for (op = prefix_opcodes; op < op_end; op++)
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{
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if (ENABLE_CHECKING)
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{
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unsigned int new_opcode = PPC_PREFIX_SEG (op[0].opcode);
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#ifdef PRINT_OPCODE_TABLE
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printf ("%-14s\t#%04u\tmajor op/2: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n",
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op->name, (unsigned int) (op - prefix_opcodes),
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new_opcode, (unsigned long long) op->opcode,
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(unsigned long long) op->mask, (unsigned long long) op->flags);
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#endif
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/* The major opcodes had better be sorted. Code in the disassembler
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assumes the insns are sorted according to major opcode. */
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if (op != prefix_opcodes
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&& new_opcode < PPC_PREFIX_SEG (op[-1].opcode))
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{
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as_bad (_("major opcode is not sorted for %s"), op->name);
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bad_insn = TRUE;
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}
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bad_insn |= insn_validate (op);
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}
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if ((ppc_cpu & op->flags) != 0
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&& !(ppc_cpu & op->deprecated))
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{
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const char *retval;
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retval = hash_insert (ppc_hash, op->name, (void *) op);
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if (retval != NULL)
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{
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as_bad (_("duplicate instruction %s"),
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op->name);
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bad_insn = TRUE;
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}
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}
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}
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if ((ppc_cpu & PPC_OPCODE_ANY) != 0)
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for (op = prefix_opcodes; op < op_end; op++)
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hash_insert (ppc_hash, op->name, (void *) op);
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op_end = vle_opcodes + vle_num_opcodes;
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for (op = vle_opcodes; op < op_end; op++)
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{
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@ -2740,6 +2784,90 @@ ppc_apuinfo_section_add (unsigned int apu, unsigned int version)
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#undef APUID
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#endif
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/* Various frobbings of labels and their addresses. */
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/* Symbols labelling the current insn. */
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struct insn_label_list
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{
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struct insn_label_list *next;
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symbolS *label;
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};
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static struct insn_label_list *insn_labels;
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static struct insn_label_list *free_insn_labels;
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static void
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ppc_record_label (symbolS *sym)
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{
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struct insn_label_list *l;
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if (free_insn_labels == NULL)
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l = XNEW (struct insn_label_list);
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else
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{
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l = free_insn_labels;
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free_insn_labels = l->next;
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}
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l->label = sym;
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l->next = insn_labels;
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insn_labels = l;
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}
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static void
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ppc_clear_labels (void)
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{
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while (insn_labels != NULL)
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{
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struct insn_label_list *l = insn_labels;
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insn_labels = l->next;
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l->next = free_insn_labels;
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free_insn_labels = l;
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}
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}
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void
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ppc_start_line_hook (void)
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{
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ppc_clear_labels ();
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}
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void
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ppc_new_dot_label (symbolS *sym)
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{
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ppc_record_label (sym);
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#ifdef OBJ_XCOFF
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/* Anchor this label to the current csect for relocations. */
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symbol_get_tc (sym)->within = ppc_current_csect;
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#endif
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}
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void
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ppc_frob_label (symbolS *sym)
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{
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ppc_record_label (sym);
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#ifdef OBJ_XCOFF
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/* Set the class of a label based on where it is defined. This handles
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symbols without suffixes. Also, move the symbol so that it follows
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the csect symbol. */
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if (ppc_current_csect != (symbolS *) NULL)
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{
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if (symbol_get_tc (sym)->symbol_class == -1)
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symbol_get_tc (sym)->symbol_class = symbol_get_tc (ppc_current_csect)->symbol_class;
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symbol_remove (sym, &symbol_rootP, &symbol_lastP);
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symbol_append (sym, symbol_get_tc (ppc_current_csect)->within,
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&symbol_rootP, &symbol_lastP);
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symbol_get_tc (ppc_current_csect)->within = sym;
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symbol_get_tc (sym)->within = ppc_current_csect;
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}
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#endif
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#ifdef OBJ_ELF
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dwarf2_emit_label (sym);
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#endif
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}
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/* We need to keep a list of fixups. We can't simply generate them as
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we go, because that would require us to first create the frag, and
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@ -3074,6 +3202,7 @@ md_assemble (char *str)
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else
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ppc_macro (s, macro);
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ppc_clear_labels ();
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return;
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}
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@ -3828,14 +3957,50 @@ md_assemble (char *str)
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if ((frag_now_fix () & addr_mask) != 0)
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as_bad (_("instruction address is not a multiple of %d"), addr_mask + 1);
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/* Differentiate between two and four byte insns. */
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/* Differentiate between two, four, and eight byte insns. */
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insn_length = 4;
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if ((ppc_cpu & PPC_OPCODE_VLE) != 0 && PPC_OP_SE_VLE (insn))
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insn_length = 2;
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else if ((opcode->flags & PPC_OPCODE_POWERXX) != 0
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&& PPC_PREFIX_P (insn))
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{
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struct insn_label_list *l;
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insn_length = 8;
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/* 8-byte prefix instructions are not allowed to cross 64-byte
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boundaries. */
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frag_align_code (6, 4);
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record_alignment (now_seg, 6);
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/* Update "dot" in any expressions used by this instruction, and
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a label attached to the instruction. By "attached" we mean
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on the same source line as the instruction and without any
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intervening semicolons. */
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dot_value = frag_now_fix ();
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dot_frag = frag_now;
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for (l = insn_labels; l != NULL; l = l->next)
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{
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symbol_set_frag (l->label, dot_frag);
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S_SET_VALUE (l->label, dot_value);
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}
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}
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ppc_clear_labels ();
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f = frag_more (insn_length);
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frag_now->insn_addr = addr_mask;
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md_number_to_chars (f, insn, insn_length);
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/* The prefix part of an 8-byte instruction always occupies the lower
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addressed word in a doubleword, regardless of endianness. */
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if (!target_big_endian && insn_length == 8)
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{
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md_number_to_chars (f, PPC_GET_PREFIX (insn), 4);
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md_number_to_chars (f + 4, PPC_GET_SUFFIX (insn), 4);
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}
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else
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md_number_to_chars (f, insn, insn_length);
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last_insn = insn;
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last_seg = now_seg;
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last_subseg = now_subseg;
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@ -6118,30 +6283,6 @@ ppc_symbol_new_hook (symbolS *sym)
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as_bad (_("unrecognized symbol suffix"));
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}
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/* Set the class of a label based on where it is defined. This
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handles symbols without suffixes. Also, move the symbol so that it
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follows the csect symbol. */
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void
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ppc_frob_label (symbolS *sym)
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{
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if (ppc_current_csect != (symbolS *) NULL)
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{
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if (symbol_get_tc (sym)->symbol_class == -1)
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symbol_get_tc (sym)->symbol_class = symbol_get_tc (ppc_current_csect)->symbol_class;
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symbol_remove (sym, &symbol_rootP, &symbol_lastP);
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symbol_append (sym, symbol_get_tc (ppc_current_csect)->within,
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&symbol_rootP, &symbol_lastP);
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symbol_get_tc (ppc_current_csect)->within = sym;
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symbol_get_tc (sym)->within = ppc_current_csect;
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}
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#ifdef OBJ_ELF
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dwarf2_emit_label (sym);
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#endif
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}
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/* This variable is set by ppc_frob_symbol if any absolute symbols are
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seen. It tells ppc_adjust_symtab whether it needs to look through
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the symbols. */
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@ -6673,14 +6814,6 @@ ppc_force_relocation (fixS *fix)
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return generic_force_reloc (fix);
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}
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void
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ppc_new_dot_label (symbolS *sym)
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{
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/* Anchor this label to the current csect for relocations. */
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symbol_get_tc (sym)->within = ppc_current_csect;
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}
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#endif /* OBJ_XCOFF */
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#ifdef OBJ_ELF
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@ -171,10 +171,6 @@ extern char *ppc_canonicalize_symbol_name (char *);
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#define tc_symbol_new_hook(sym) ppc_symbol_new_hook (sym)
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extern void ppc_symbol_new_hook (symbolS *);
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/* Set the symbol class of a label based on the csect. */
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#define tc_frob_label(sym) ppc_frob_label (sym)
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extern void ppc_frob_label (symbolS *);
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/* TOC relocs requires special handling. */
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#define tc_fix_adjustable(FIX) ppc_fix_adjustable (FIX)
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extern int ppc_fix_adjustable (struct fix *);
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@ -206,11 +202,11 @@ do { \
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extern void ppc_xcoff_end (void);
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#define md_end ppc_xcoff_end
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#endif /* OBJ_XCOFF */
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#define tc_new_dot_label(sym) ppc_new_dot_label (sym)
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extern void ppc_new_dot_label (symbolS *);
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#endif /* OBJ_XCOFF */
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extern const char ppc_symbol_chars[];
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#define tc_symbol_chars ppc_symbol_chars
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@ -282,6 +278,14 @@ extern int ppc_force_relocation (struct fix *);
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#define TC_VALIDATE_FIX_SUB(FIX, SEG) 0
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/* Various frobbings of labels and their addresses. */
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#define md_start_line_hook() ppc_start_line_hook ()
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extern void ppc_start_line_hook (void);
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/* Set the symbol class of a label based on the csect. */
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#define tc_frob_label(sym) ppc_frob_label (sym)
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extern void ppc_frob_label (symbolS *);
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/* call md_pcrel_from_section, not md_pcrel_from */
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#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section(FIX, SEC)
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extern long md_pcrel_from_section (struct fix *, segT);
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@ -114,3 +114,4 @@ run_dump_test "vsx2"
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run_dump_test "vsx3"
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run_dump_test "htm"
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run_dump_test "titan"
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run_dump_test "prefix-align"
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@ -0,0 +1,30 @@
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#as: -mfuture
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#objdump: -dr -Mfuture
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#name: POWERXX alignment of labels test
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.*
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Disassembly of section \.text:
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0+00 <_start>:
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0: (48 00 00 3c|3c 00 00 48) b 3c <_start\+0x3c>
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4: (48 00 00 3c|3c 00 00 48) b 40 <_start\+0x40>
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8: (48 00 00 40|40 00 00 48) b 48 <_start\+0x48>
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c: (7f e0 00 08|08 00 e0 7f) trap
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10: (7f e0 00 08|08 00 e0 7f) trap
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14: (7f e0 00 08|08 00 e0 7f) trap
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18: (7f e0 00 08|08 00 e0 7f) trap
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1c: (7f e0 00 08|08 00 e0 7f) trap
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20: (7f e0 00 08|08 00 e0 7f) trap
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24: (7f e0 00 08|08 00 e0 7f) trap
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28: (7f e0 00 08|08 00 e0 7f) trap
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2c: (7f e0 00 08|08 00 e0 7f) trap
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30: (7f e0 00 08|08 00 e0 7f) trap
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34: (7f e0 00 08|08 00 e0 7f) trap
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38: (7f e0 00 08|08 00 e0 7f) trap
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3c: (60 00 00 00|00 00 00 60) nop
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40: (07 00 00 00|00 00 00 07) pnop
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44: (00 00 00 00|00 00 00 00)
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48: (4e 80 00 20|20 00 80 4e) blr
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#pass
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@ -0,0 +1,21 @@
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.text
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_start:
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b 1f;
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b 2f;
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b 3f;
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trap
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trap
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trap
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trap
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trap
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trap
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trap
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trap
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trap
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trap
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trap
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trap
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1:
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2: pnop
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3:
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blr
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@ -1,3 +1,11 @@
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2019-05-24 Peter Bergner <bergner@linux.ibm.com>
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Alan Modra <amodra@gmail.com>
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* dis-asm.h (WIDE_OUTPUT): Define.
|
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* opcode/ppc.h (prefix_opcodes, prefix_num_opcodes): Declare.
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(PPC_OPCODE_POWERXX, PPC_GET_PREFIX, PPC_GET_SUFFIX),
|
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(PPC_PREFIX_P, PPC_PREFIX_SEG): Define.
|
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|
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2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
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* elf/bpf.h: New file.
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@ -116,6 +116,8 @@ typedef struct disassemble_info
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/* Set if the user has specifically set the machine type encoded in the
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mach field of this structure. */
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#define USER_SPECIFIED_MACHINE_TYPE (1 << 29)
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||||
/* Set if the user has requested wide output. */
|
||||
#define WIDE_OUTPUT (1 << 28)
|
||||
|
||||
/* Use internally by the target specific disassembly code. */
|
||||
void *private_data;
|
||||
|
|
|
|||
|
|
@ -68,6 +68,8 @@ struct powerpc_opcode
|
|||
instructions. */
|
||||
extern const struct powerpc_opcode powerpc_opcodes[];
|
||||
extern const unsigned int powerpc_num_opcodes;
|
||||
extern const struct powerpc_opcode prefix_opcodes[];
|
||||
extern const unsigned int prefix_num_opcodes;
|
||||
extern const struct powerpc_opcode vle_opcodes[];
|
||||
extern const unsigned int vle_num_opcodes;
|
||||
extern const struct powerpc_opcode spe2_opcodes[];
|
||||
|
|
@ -226,6 +228,9 @@ extern const unsigned int spe2_num_opcodes;
|
|||
/* Opcode is supported by EFS2. */
|
||||
#define PPC_OPCODE_EFS2 0x200000000000ull
|
||||
|
||||
/* Opcode is only supported by powerxx architecture. */
|
||||
#define PPC_OPCODE_POWERXX 0x400000000000ull
|
||||
|
||||
/* A macro to extract the major opcode from an instruction. */
|
||||
#define PPC_OP(i) (((i) >> 26) & 0x3f)
|
||||
|
||||
|
|
@ -243,6 +248,19 @@ extern const unsigned int spe2_num_opcodes;
|
|||
|
||||
/* A macro to convert a SPE2 extended opcode to a SPE2 xopcode segment. */
|
||||
#define SPE2_XOP_TO_SEG(i) ((i) >> 7)
|
||||
|
||||
/* A macro to extract the prefix word from an 8-byte PREFIX instruction. */
|
||||
#define PPC_GET_PREFIX(i) (((i) >> 32) & ((1LL << 32) - 1))
|
||||
|
||||
/* A macro to extract the suffix word from an 8-byte PREFIX instruction. */
|
||||
#define PPC_GET_SUFFIX(i) ((i) & ((1LL << 32) - 1))
|
||||
|
||||
/* A macro to determine whether insn I is an 8-byte prefix instruction. */
|
||||
#define PPC_PREFIX_P(i) (PPC_OP (PPC_GET_PREFIX (i)) == 0x1)
|
||||
|
||||
/* A macro used to hash 8-byte PREFIX instructions. */
|
||||
#define PPC_PREFIX_SEG(i) (PPC_OP (i) >> 1)
|
||||
|
||||
|
||||
/* The operands table is an array of struct powerpc_operand. */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,17 @@
|
|||
2019-05-24 Peter Bergner <bergner@linux.ibm.com>
|
||||
Alan Modra <amodra@gmail.com>
|
||||
|
||||
* ppc-dis.c (ppc_opts): Add "future" entry.
|
||||
(PREFIX_OPCD_SEGS): Define.
|
||||
(prefix_opcd_indices): New array.
|
||||
(disassemble_init_powerpc): Initialize prefix_opcd_indices.
|
||||
(lookup_prefix): New function.
|
||||
(print_insn_powerpc): Handle 64-bit prefix instructions.
|
||||
* ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
|
||||
(PMRR, POWERXX): Define.
|
||||
(prefix_opcodes): New instruction table.
|
||||
(prefix_num_opcodes): New constant.
|
||||
|
||||
2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
|
||||
|
||||
* configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
|
||||
|
|
|
|||
|
|
@ -185,6 +185,11 @@ struct ppc_mopt ppc_opts[] = {
|
|||
| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
|
||||
| PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
|
||||
0 },
|
||||
{ "future", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
|
||||
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
|
||||
| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
|
||||
| PPC_OPCODE_POWERXX | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
|
||||
0 },
|
||||
{ "ppc", PPC_OPCODE_PPC,
|
||||
0 },
|
||||
{ "ppc32", PPC_OPCODE_PPC,
|
||||
|
|
@ -376,6 +381,8 @@ powerpc_init_dialect (struct disassemble_info *info)
|
|||
|
||||
#define PPC_OPCD_SEGS (1 + PPC_OP (-1))
|
||||
static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS + 1];
|
||||
#define PREFIX_OPCD_SEGS (1 + PPC_PREFIX_SEG (-1))
|
||||
static unsigned short prefix_opcd_indices[PPC_OPCD_SEGS+1];
|
||||
#define VLE_OPCD_SEGS (1 + VLE_OP_TO_SEG (VLE_OP (-1, 0xffff)))
|
||||
static unsigned short vle_opcd_indices[VLE_OPCD_SEGS + 1];
|
||||
#define SPE2_OPCD_SEGS (1 + SPE2_XOP_TO_SEG (SPE2_XOP (-1)))
|
||||
|
|
@ -400,6 +407,15 @@ disassemble_init_powerpc (struct disassemble_info *info)
|
|||
break;
|
||||
}
|
||||
|
||||
/* 64-bit prefix opcodes */
|
||||
for (seg = 0, idx = 0; seg <= PREFIX_OPCD_SEGS; seg++)
|
||||
{
|
||||
prefix_opcd_indices[seg] = idx;
|
||||
for (; idx < prefix_num_opcodes; idx++)
|
||||
if (seg < PPC_PREFIX_SEG (prefix_opcodes[idx].opcode))
|
||||
break;
|
||||
}
|
||||
|
||||
/* VLE opcodes */
|
||||
for (seg = 0, idx = 0; seg <= VLE_OPCD_SEGS; seg++)
|
||||
{
|
||||
|
|
@ -556,6 +572,57 @@ lookup_powerpc (uint64_t insn, ppc_cpu_t dialect)
|
|||
return last;
|
||||
}
|
||||
|
||||
/* Find a match for INSN in the PREFIX opcode table. */
|
||||
|
||||
static const struct powerpc_opcode *
|
||||
lookup_prefix (uint64_t insn, ppc_cpu_t dialect)
|
||||
{
|
||||
const struct powerpc_opcode *opcode, *opcode_end, *last;
|
||||
unsigned long seg;
|
||||
|
||||
/* Get the opcode segment of the instruction. */
|
||||
seg = PPC_PREFIX_SEG (insn);
|
||||
|
||||
/* Find the first match in the opcode table for this major opcode. */
|
||||
opcode_end = prefix_opcodes + prefix_opcd_indices[seg + 1];
|
||||
last = NULL;
|
||||
for (opcode = prefix_opcodes + prefix_opcd_indices[seg];
|
||||
opcode < opcode_end;
|
||||
++opcode)
|
||||
{
|
||||
const unsigned char *opindex;
|
||||
const struct powerpc_operand *operand;
|
||||
int invalid;
|
||||
|
||||
if ((insn & opcode->mask) != opcode->opcode
|
||||
|| ((dialect & PPC_OPCODE_ANY) == 0
|
||||
&& ((opcode->flags & dialect) == 0
|
||||
|| (opcode->deprecated & dialect) != 0)))
|
||||
continue;
|
||||
|
||||
/* Check validity of operands. */
|
||||
invalid = 0;
|
||||
for (opindex = opcode->operands; *opindex != 0; opindex++)
|
||||
{
|
||||
operand = powerpc_operands + *opindex;
|
||||
if (operand->extract)
|
||||
(*operand->extract) (insn, dialect, &invalid);
|
||||
}
|
||||
if (invalid)
|
||||
continue;
|
||||
|
||||
if ((dialect & PPC_OPCODE_RAW) == 0)
|
||||
return opcode;
|
||||
|
||||
/* The raw machine insn is one that is not a specialization. */
|
||||
if (last == NULL
|
||||
|| (last->mask & ~opcode->mask) != 0)
|
||||
last = opcode;
|
||||
}
|
||||
|
||||
return last;
|
||||
}
|
||||
|
||||
/* Find a match for INSN in the VLE opcode table. */
|
||||
|
||||
static const struct powerpc_opcode *
|
||||
|
|
@ -699,7 +766,31 @@ print_insn_powerpc (bfd_vma memaddr,
|
|||
|
||||
/* Get the major opcode of the insn. */
|
||||
opcode = NULL;
|
||||
if ((dialect & PPC_OPCODE_VLE) != 0)
|
||||
if ((dialect & PPC_OPCODE_POWERXX) != 0
|
||||
&& PPC_OP (insn) == 0x1)
|
||||
{
|
||||
uint64_t temp_insn, suffix;
|
||||
status = (*info->read_memory_func) (memaddr + 4, buffer, 4, info);
|
||||
if (status == 0)
|
||||
{
|
||||
if (bigendian)
|
||||
suffix = bfd_getb32 (buffer);
|
||||
else
|
||||
suffix = bfd_getl32 (buffer);
|
||||
temp_insn = (insn << 32) | suffix;
|
||||
opcode = lookup_prefix (temp_insn, dialect & ~PPC_OPCODE_ANY);
|
||||
if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
|
||||
opcode = lookup_prefix (temp_insn, dialect);
|
||||
if (opcode != NULL)
|
||||
{
|
||||
insn = temp_insn;
|
||||
insn_length = 8;
|
||||
if ((info->flags & WIDE_OUTPUT) != 0)
|
||||
info->bytes_per_line = 8;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (opcode == NULL && (dialect & PPC_OPCODE_VLE) != 0)
|
||||
{
|
||||
opcode = lookup_vle (insn);
|
||||
if (opcode != NULL && PPC_OP_SE_VLE (opcode->mask))
|
||||
|
|
|
|||
|
|
@ -2721,6 +2721,18 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
|
|||
#define OP(x) ((((uint64_t)(x)) & 0x3f) << 26)
|
||||
#define OP_MASK OP (0x3f)
|
||||
|
||||
/* The prefix opcode. */
|
||||
#define PREFIX_OP (1ULL << 58)
|
||||
|
||||
/* The 2-bit prefix form. */
|
||||
#define PREFIX_FORM(x) ((x & 3ULL) << 56)
|
||||
|
||||
#define SUFFIX_MASK ((1ULL << 32) - 1)
|
||||
#define PREFIX_MASK (SUFFIX_MASK << 32)
|
||||
|
||||
/* Prefix insn, modified register to register form MRR. */
|
||||
#define PMRR (PREFIX_OP | PREFIX_FORM (3))
|
||||
|
||||
/* The main opcode combined with a trap code in the TO field of a D
|
||||
form instruction. Used for extended mnemonics for the trap
|
||||
instructions. */
|
||||
|
|
@ -3547,6 +3559,7 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
|
|||
#define POWER7 PPC_OPCODE_POWER7
|
||||
#define POWER8 PPC_OPCODE_POWER8
|
||||
#define POWER9 PPC_OPCODE_POWER9
|
||||
#define POWERXX PPC_OPCODE_POWERXX
|
||||
#define CELL PPC_OPCODE_CELL
|
||||
#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
|
||||
#define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \
|
||||
|
|
@ -7796,6 +7809,17 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
const unsigned int powerpc_num_opcodes =
|
||||
sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
|
||||
|
||||
/* The opcode table for 8-byte prefix instructions.
|
||||
|
||||
The format of this opcode table is the same as the main opcode table. */
|
||||
|
||||
const struct powerpc_opcode prefix_opcodes[] = {
|
||||
{"pnop", PMRR, PREFIX_MASK, POWERXX, 0, {0}},
|
||||
};
|
||||
|
||||
const unsigned int prefix_num_opcodes =
|
||||
sizeof (prefix_opcodes) / sizeof (prefix_opcodes[0]);
|
||||
|
||||
/* The VLE opcode table.
|
||||
|
||||
The format of this opcode table is the same as the main opcode table. */
|
||||
|
|
|
|||
Loading…
Reference in New Issue