* config/tc-mips.c: Remove all the mips_NNNN variables; just use
mips_cpu instead. (mips_4650, mips_4010, mips_4100): Variables removed. start-sanitize-vr4xxx (mips_4121): Variable removed. end-sanitize-vr4xxx start-sanitize-vr4320 (mips_4320): Variable removed. end-sanitize-vr4320 start-sanitize-cygnus (mips_5400): Variable removed. end-sanitize-cygnus start-sanitize-r5900 (mips_5900): Variable removed. end-sanitize-r5900 start-sanitize-tx49 (mips_4900): Variable removed. end-sanitize-tx49 (hilo_interlocks, gpr_interlocks, append_insn, macro_build, macro, macro2, mips16_macro, mips_ip): Test mips_cpu, not the mips_NNNN variables. (md_begin): Don't bother initializing the mips_NNNN variables; mips_cpu is set, and that's good enough now. (md_parse_option): Have the -mNNNN options set mips_cpu instead of the mips_NNNN variable. The -no-mNNNN flags are now no-ops. (show): New function, to handle wrapping in the CPU lists. (md_show_usage): Update lists of -mcpu and -mNNNN switches.
This commit is contained in:
parent
adfdbe9083
commit
de484a066b
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@ -140,11 +140,7 @@ mips_target_format ()
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/* This is the set of options which may be modified by the .set
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pseudo-op. We use a struct so that .set push and .set pop are more
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reliable.
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FIXME: The CPU specific variables (mips_4010, et. al.) should
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probably be in here as well, and there should probably be some way
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to set them. */
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reliable. */
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struct mips_set_options
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{
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@ -204,71 +200,43 @@ static char* mips_abi_string = 0;
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/* Wether we should mark the file EABI64 or EABI32. */
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static int mips_eabi64 = 0;
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/* Whether the 4650 instructions (mad/madu) are permitted. */
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static int mips_4650 = -1;
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/* Whether the 4010 instructions are permitted. */
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static int mips_4010 = -1;
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/* Whether the 4100 MADD16 and DMADD16 are permitted. */
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static int mips_4100 = -1;
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/* start-sanitize-vr4xxx */
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/* Whether NEC 4121 instructions are permitted. */
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static int mips_4121 = -1;
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/* end-sanitize-vr4xxx */
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/* start-sanitize-vr4320 */
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/* Whether NEC vr4320 instructions are permitted. */
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static int mips_4320 = -1;
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/* end-sanitize-vr4320 */
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/* start-sanitize-cygnus */
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/* Whether NEC vr5400 instructions are permitted. */
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static int mips_5400 = -1;
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/* end-sanitize-cygnus */
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/* start-sanitize-r5900 */
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/* Whether Toshiba r5900 instructions are permitted. */
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static int mips_5900 = -1;
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/* end-sanitize-r5900 */
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/* Whether Toshiba r3900 instructions are permitted. */
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static int mips_3900 = -1;
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/* start-sanitize-tx49 */
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/* Whether Toshiba r4900 instructions are permitted. */
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static int mips_4900 = -1;
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/* end-sanitize-tx49 */
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/* start-sanitize-tx19 */
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/* The tx19 (r1900) is a mips16 decoder with a tx39(r3900) behind it.
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The tx19 related options and configuration bits are handled by
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the tx39 flags. */
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/* end-sanitize-tx19 */
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/* Whether the processor uses hardware interlocks to protect
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reads from the HI and LO registers, and thus does not
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require nops to be inserted.
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FIXME: We really should not be checking mips_cpu here. The -mcpu=
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option is documented to not do anything special. In gcc, the
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-mcpu= option only affects scheduling, and does not affect code
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generation. Each test of -mcpu= here should actually be testing a
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specific variable, such as mips_4010, and each such variable should
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have a command line option to set it. The -mcpu= option may be
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used to set the default value of these options, as is the case for
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mips_4010. */
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FIXME: GCC makes a distinction between -mcpu=FOO and -mFOO:
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-mcpu=FOO schedules for FOO, but still produces code that meets the
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requirements of MIPS ISA I. For example, it won't generate any
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FOO-specific instructions, and it will still assume that any
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scheduling hazards described in MIPS ISA I are there, even if FOO
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has interlocks. -mFOO gives GCC permission to generate code that
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will only run on a FOO; it will generate FOO-specific instructions,
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and assume interlocks provided by a FOO.
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#define hilo_interlocks (mips_4010 \
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However, GAS currently doesn't make this distinction; before Jan 28
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1999, GAS's -mcpu=FOO implied -mFOO, which violates GCC's
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assumptions. The GCC driver passes these flags through to GAS, so
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if GAS actually does anything that doesn't meet MIPS ISA I with
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-mFOO, then GCC's -mcpu=FOO flag isn't going to work.
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And furthermore, it did not assume that -mFOO implied -mcpu=FOO,
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which seems senseless --- why generate code which will only run on
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a FOO, but schedule for something else?
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So now, at least, -mcpu=FOO and -mFOO are exactly equivalent.
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-- Jim Blandy <jimb@cygnus.com> */
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#define hilo_interlocks (mips_cpu == 4010 \
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/* start-sanitize-tx49 */ \
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|| mips_cpu == 4900 || mips_4900 \
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|| mips_cpu == 4900 \
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/* end-sanitize-tx49 */ \
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/* start-sanitize-vr4320 */ \
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|| mips_cpu == 4320 \
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/* end-sanitize-vr4320 */ \
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/* start-sanitize-r5900 */ \
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|| mips_5900 \
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|| mips_cpu == 5900 \
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/* end-sanitize-r5900 */ \
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)
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#define gpr_interlocks \
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(mips_opts.isa >= 2 \
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/* start-sanitize-cygnus */ \
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|| mips_5400 \
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|| mips_cpu == 5400 \
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/* end-sanitize-cygnus */ \
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/* start-sanitize-r5900 */ \
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|| mips_5900 \
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|| mips_cpu == 5900 \
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/* end-sanitize-r5900 */ \
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|| mips_3900)
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|| mips_cpu == 3900)
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/* As with other "interlocks" this is used by hardware that has FP
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(co-processor) interlocks. */
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@ -1053,48 +1021,6 @@ md_begin ()
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mips_opts.mips16 = 0;
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}
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if (mips_4650 < 0)
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mips_4650 = (mips_cpu == 4650);
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if (mips_4010 < 0)
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mips_4010 = (mips_cpu == 4010);
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if (mips_4100 < 0)
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mips_4100 = (mips_cpu == 4100
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/* start-sanitize-vr4xxx */
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|| mips_cpu == 4111
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/* end-sanitize-vr4xxx */
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);
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/* start-sanitize-vr4xxx */
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if (mips_4121 < 0)
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mips_4121 = (mips_cpu == 4121);
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/* end-sanitize-vr4xxx */
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/* start-sanitize-vr4320 */
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if (mips_4320 < 0)
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mips_4320 = (mips_cpu == 4320);
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/* end-sanitize-vr4320 */
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/* start-sanitize-cygnus */
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if (mips_5400 < 0)
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mips_5400 = (mips_cpu == 5400);
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/* end-sanitize-cygnus */
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/* start-sanitize-r5900 */
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if (mips_5900 < 0)
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mips_5900 = (mips_cpu == 5900);
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/* end-sanitize-r5900 */
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if (mips_3900 < 0)
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mips_3900 = (mips_cpu == 3900);
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/* start-sanitize-tx49 */
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if (mips_4900 < 0)
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mips_4900 = (mips_cpu == 4900);
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/* end-sanitize-tx49 */
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/* End of TARGET_CPU processing, get rid of malloced memory
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if necessary. */
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cpu = NULL;
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though the tx39's divide insns still do require the
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delay. */
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if (! (hilo_interlocks
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|| (mips_3900 && (pinfo & INSN_MULT)))
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|| (mips_cpu == 3900 && (pinfo & INSN_MULT)))
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&& (mips_optimize == 0
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|| (pinfo & INSN_WRITE_LO)))
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nops += 2;
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insert a NOP. Some newer processors have interlocks.
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Also the note tx39's multiply above. */
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if (! (hilo_interlocks
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|| (mips_3900 && (pinfo & INSN_MULT)))
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|| (mips_cpu == 3900 && (pinfo & INSN_MULT)))
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&& (mips_optimize == 0
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|| (pinfo & INSN_WRITE_HI)))
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nops += 2;
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@ -1746,11 +1672,11 @@ append_insn (place, ip, address_expr, reloc_type, unmatched_hi)
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|| ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
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&& (pinfo & INSN_WRITE_LO)
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&& ! (hilo_interlocks
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|| (mips_3900 && (pinfo & INSN_MULT))))
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|| (mips_cpu == 3900 && (pinfo & INSN_MULT))))
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|| ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
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&& (pinfo & INSN_WRITE_HI)
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&& ! (hilo_interlocks
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|| (mips_3900 && (pinfo & INSN_MULT)))))
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|| (mips_cpu == 3900 && (pinfo & INSN_MULT)))))
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prev_prev_nop = 1;
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else
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prev_prev_nop = 0;
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& (INSN_LOAD_COPROC_DELAY
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| INSN_COPROC_MOVE_DELAY
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| INSN_WRITE_COND_CODE)))
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|| (! (hilo_interlocks || (mips_3900 && (pinfo & INSN_MULT)))
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|| (! (hilo_interlocks
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|| (mips_cpu == 3900 && (pinfo & INSN_MULT)))
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&& (prev_pinfo
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& (INSN_READ_LO
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| INSN_READ_HI)))
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if (strcmp (fmt, insn.insn_mo->args) == 0
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&& insn.insn_mo->pinfo != INSN_MACRO
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&& (insn_isa <= mips_opts.isa
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|| (mips_4650
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|| (mips_cpu == 4650
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&& (insn.insn_mo->membership & INSN_4650) != 0)
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|| (mips_4010
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|| (mips_cpu == 4010
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&& (insn.insn_mo->membership & INSN_4010) != 0)
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|| (mips_4100
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|| ((mips_cpu == 4100
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/* start-sanitize-vr4xxx */
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|| mips_cpu == 4111
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/* end-sanitize-vr4xxx */
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)
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&& (insn.insn_mo->membership & INSN_4100) != 0)
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/* start-sanitize-vr4xxx */
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|| (mips_4121
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|| (mips_cpu == 4121
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&& (insn.insn_mo->membership & INSN_4121) != 0)
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/* end-sanitize-vr4xxx */
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/* start-sanitize-vr4320 */
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|| (mips_4320
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|| (mips_cpu == 4320
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&& (insn.insn_mo->membership & INSN_4320) != 0)
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/* end-sanitize-vr4320 */
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/* start-sanitize-tx49 */
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|| (mips_4900
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|| (mips_cpu == 4900
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&& (insn.insn_mo->membership & INSN_4900) != 0)
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/* end-sanitize-tx49 */
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/* start-sanitize-r5900 */
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|| (mips_5900
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|| (mips_cpu == 5900
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&& (insn.insn_mo->membership & INSN_5900) != 0)
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/* end-sanitize-r5900 */
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/* start-sanitize-cygnus */
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|| (mips_5400
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|| (mips_cpu == 5400
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&& (insn.insn_mo->membership & INSN_5400) != 0)
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/* end-sanitize-cygnus */
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|| (mips_3900
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|| (mips_cpu == 3900
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&& (insn.insn_mo->membership & INSN_3900) != 0))
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/* start-sanitize-r5900 */
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&& (! mips_5900 || (insn.insn_mo->pinfo & FP_D) == 0)
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&& (mips_cpu != 5900 || (insn.insn_mo->pinfo & FP_D) == 0)
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/* end-sanitize-r5900 */
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&& (! mips_4650 || (insn.insn_mo->pinfo & FP_D) == 0))
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&& (mips_cpu != 4650 || (insn.insn_mo->pinfo & FP_D) == 0))
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break;
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++insn.insn_mo;
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@ -4121,7 +4052,7 @@ macro (ip)
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macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0);
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else
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/* start-sanitize-r5900 */
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if (mips_5900)
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if (mips_cpu == 5900)
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macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7);
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else
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/* end-sanitize-r5900 */
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@ -4147,7 +4078,7 @@ macro (ip)
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dbl ? "ddiv" : "div",
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"z,s,t", sreg, treg);
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/* start-sanitize-r5900 */
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if (mips_5900)
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if (mips_cpu == 5900)
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macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7);
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else
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/* end-sanitize-r5900 */
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@ -4191,7 +4122,7 @@ macro (ip)
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--mips_opts.noreorder;
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/* start-sanitize-r5900 */
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if (mips_5900)
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if (mips_cpu == 5900)
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macro_build ((char *) NULL, &icnt, NULL, "break", "B", 6);
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else
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/* end-sanitize-r5900 */
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|
@ -4243,7 +4174,7 @@ macro (ip)
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macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0);
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else
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/* start-sanitize-r5900 */
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if (mips_5900)
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if (mips_cpu == 5900)
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macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7);
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else
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/* end-sanitize-r5900 */
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|
@ -4319,7 +4250,7 @@ macro (ip)
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that later insns are available for delay slot filling. */
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--mips_opts.noreorder;
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/* start-sanitize-r5900 */
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if (mips_5900)
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if (mips_cpu == 5900)
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macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7);
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else
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/* end-sanitize-r5900 */
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|
@ -5019,7 +4950,7 @@ macro (ip)
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lr = 1;
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goto ld;
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case M_LDC1_AB:
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if (mips_4650)
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if (mips_cpu == 4650)
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{
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as_bad (_("opcode not supported on this processor"));
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return;
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|
@ -5108,7 +5039,7 @@ macro (ip)
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s = "scd";
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goto st;
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case M_SDC1_AB:
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if (mips_4650)
|
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if (mips_cpu == 4650)
|
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{
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as_bad (_("opcode not supported on this processor"));
|
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return;
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|
@ -5596,7 +5527,7 @@ macro (ip)
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|||
}
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|
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case M_L_DOB:
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if (mips_4650)
|
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if (mips_cpu == 4650)
|
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{
|
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as_bad (_("opcode not supported on this processor"));
|
||||
return;
|
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|
@ -5637,7 +5568,7 @@ macro (ip)
|
|||
* But, the resulting address is the same after relocation so why
|
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* generate the extra instruction?
|
||||
*/
|
||||
if (mips_4650)
|
||||
if (mips_cpu == 4650)
|
||||
{
|
||||
as_bad (_("opcode not supported on this processor"));
|
||||
return;
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||||
|
@ -5655,7 +5586,7 @@ macro (ip)
|
|||
goto ldd_std;
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||||
|
||||
case M_S_DAB:
|
||||
if (mips_4650)
|
||||
if (mips_cpu == 4650)
|
||||
{
|
||||
as_bad (_("opcode not supported on this processor"));
|
||||
return;
|
||||
|
@ -6209,7 +6140,7 @@ macro2 (ip)
|
|||
macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT);
|
||||
macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0);
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||||
/* start-sanitize-r5900 */
|
||||
if (mips_5900)
|
||||
if (mips_cpu == 5900)
|
||||
macro_build ((char *) NULL, &icnt, NULL, "break", "B", 6);
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||||
else
|
||||
/* end-sanitize-r5900 */
|
||||
|
@ -6247,7 +6178,7 @@ macro2 (ip)
|
|||
macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0);
|
||||
macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0);
|
||||
/* start-sanitize-r5900 */
|
||||
if (mips_5900)
|
||||
if (mips_cpu == 5900)
|
||||
macro_build ((char *) NULL, &icnt, NULL, "break", "B", 6);
|
||||
else
|
||||
/* end-sanitize-r5900 */
|
||||
|
@ -6293,7 +6224,7 @@ macro2 (ip)
|
|||
break;
|
||||
|
||||
case M_S_DOB:
|
||||
if (mips_4650)
|
||||
if (mips_cpu == 4650)
|
||||
{
|
||||
as_bad (_("opcode not supported on this processor"));
|
||||
return;
|
||||
|
@ -6905,7 +6836,7 @@ mips16_macro (ip)
|
|||
expr1.X_add_number = 2;
|
||||
macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
|
||||
/* start-sanitize-r5900 */
|
||||
if (mips_5900)
|
||||
if (mips_cpu == 5900)
|
||||
macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7);
|
||||
else
|
||||
/* end-sanitize-r5900 */
|
||||
|
@ -6942,7 +6873,7 @@ mips16_macro (ip)
|
|||
expr1.X_add_number = 2;
|
||||
macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
|
||||
/* start-sanitize-r5900 */
|
||||
if (mips_5900)
|
||||
if (mips_cpu == 5900)
|
||||
macro_build ((char *) NULL, &icnt, NULL, "break", "B", 7);
|
||||
else
|
||||
/* end-sanitize-r5900 */
|
||||
|
@ -7323,35 +7254,40 @@ mips_ip (str, ip)
|
|||
ok = true;
|
||||
else if (insn->pinfo == INSN_MACRO)
|
||||
ok = false;
|
||||
else if ((mips_4650 && (insn->membership & INSN_4650) != 0)
|
||||
|| (mips_4010 && (insn->membership & INSN_4010) != 0)
|
||||
|| (mips_4100 && (insn->membership & INSN_4100) != 0)
|
||||
else if ((mips_cpu == 4650 && (insn->membership & INSN_4650) != 0)
|
||||
|| (mips_cpu == 4010 && (insn->membership & INSN_4010) != 0)
|
||||
|| ((mips_cpu == 4100
|
||||
/* start-sanitize-vr4xxx */
|
||||
|| mips_cpu == 4111
|
||||
/* end-sanitize-vr4xxx */
|
||||
)
|
||||
&& (insn->membership & INSN_4100) != 0)
|
||||
/* start-sanitize-vr4xxx */
|
||||
|| (mips_4121 && (insn->membership & INSN_4121) != 0)
|
||||
|| (mips_cpu == 4121 && (insn->membership & INSN_4121) != 0)
|
||||
/* end-sanitize-vr4xxx */
|
||||
/* start-sanitize-vr4320 */
|
||||
|| (mips_4320 && (insn->membership & INSN_4320) != 0)
|
||||
|| (mips_cpu == 4320 && (insn->membership & INSN_4320) != 0)
|
||||
/* end-sanitize-vr4320 */
|
||||
/* start-sanitize-tx49 */
|
||||
|| (mips_4900 && (insn->membership & INSN_4900) != 0)
|
||||
|| (mips_cpu == 4900 && (insn->membership & INSN_4900) != 0)
|
||||
/* end-sanitize-tx49 */
|
||||
/* start-sanitize-r5900 */
|
||||
|| (mips_5900 && (insn->membership & INSN_5900) != 0)
|
||||
|| (mips_cpu == 5900 && (insn->membership & INSN_5900) != 0)
|
||||
/* end-sanitize-r5900 */
|
||||
/* start-sanitize-cygnus */
|
||||
|| (mips_5400 && (insn->membership & INSN_5400) != 0)
|
||||
|| (mips_cpu == 5400 && (insn->membership & INSN_5400) != 0)
|
||||
/* end-sanitize-cygnus */
|
||||
|| (mips_3900 && (insn->membership & INSN_3900) != 0))
|
||||
|| (mips_cpu == 3900 && (insn->membership & INSN_3900) != 0))
|
||||
ok = true;
|
||||
else
|
||||
ok = false;
|
||||
|
||||
if (insn->pinfo != INSN_MACRO)
|
||||
{
|
||||
if (mips_4650 && (insn->pinfo & FP_D) != 0)
|
||||
if (mips_cpu == 4650 && (insn->pinfo & FP_D) != 0)
|
||||
ok = false;
|
||||
/* start-sanitize-r5900 */
|
||||
if (mips_5900 && (insn->pinfo & FP_D) != 0)
|
||||
if (mips_cpu == 5900 && (insn->pinfo & FP_D) != 0)
|
||||
ok = false;
|
||||
/* end-sanitize-r5900 */
|
||||
}
|
||||
|
@ -7735,7 +7671,7 @@ mips_ip (str, ip)
|
|||
{
|
||||
/* start-sanitize-r5900 */
|
||||
/* Allow "$viNN" as coprocessor register name */
|
||||
if (mips_5900
|
||||
if (mips_cpu == 5900
|
||||
&& *args == 'G'
|
||||
&& s[1] == 'v'
|
||||
&& s[2] == 'i')
|
||||
|
@ -9727,84 +9663,75 @@ md_parse_option (c, arg)
|
|||
break;
|
||||
|
||||
case OPTION_M4650:
|
||||
mips_4650 = 1;
|
||||
mips_cpu = 4650;
|
||||
break;
|
||||
|
||||
case OPTION_NO_M4650:
|
||||
mips_4650 = 0;
|
||||
break;
|
||||
|
||||
case OPTION_M4010:
|
||||
mips_4010 = 1;
|
||||
mips_cpu = 4010;
|
||||
break;
|
||||
|
||||
case OPTION_NO_M4010:
|
||||
mips_4010 = 0;
|
||||
break;
|
||||
|
||||
case OPTION_M4100:
|
||||
mips_4100 = 1;
|
||||
mips_cpu = 4100;
|
||||
break;
|
||||
|
||||
case OPTION_NO_M4100:
|
||||
mips_4100 = 0;
|
||||
break;
|
||||
|
||||
/* start-sanitize-vr4xxx */
|
||||
case OPTION_M4121:
|
||||
mips_4121 = 1;
|
||||
mips_cpu = 4121;
|
||||
break;
|
||||
|
||||
case OPTION_NO_M4121:
|
||||
mips_4121 = 0;
|
||||
break;
|
||||
|
||||
/* end-sanitize-vr4xxx */
|
||||
/* start-sanitize-r5900 */
|
||||
case OPTION_M5900:
|
||||
mips_5900 = 1;
|
||||
mips_cpu = 5900;
|
||||
break;
|
||||
|
||||
case OPTION_NO_M5900:
|
||||
mips_5900 = 0;
|
||||
break;
|
||||
/* end-sanitize-r5900 */
|
||||
|
||||
/* start-sanitize-vr4320 */
|
||||
case OPTION_M4320:
|
||||
mips_4320 = 1;
|
||||
mips_cpu = 4320;
|
||||
break;
|
||||
|
||||
case OPTION_NO_M4320:
|
||||
mips_4320 = 0;
|
||||
break;
|
||||
|
||||
/* end-sanitize-vr4320 */
|
||||
/* start-sanitize-cygnus */
|
||||
case OPTION_M5400:
|
||||
mips_5400 = 1;
|
||||
mips_cpu = 5400;
|
||||
break;
|
||||
|
||||
case OPTION_NO_M5400:
|
||||
mips_5400 = 0;
|
||||
break;
|
||||
|
||||
/* end-sanitize-cygnus */
|
||||
case OPTION_M3900:
|
||||
mips_3900 = 1;
|
||||
mips_cpu = 3900;
|
||||
break;
|
||||
|
||||
case OPTION_NO_M3900:
|
||||
mips_3900 = 0;
|
||||
break;
|
||||
|
||||
/* start-sanitize-tx49 */
|
||||
case OPTION_M4900:
|
||||
mips_4900 = 1;
|
||||
mips_cpu = 4900;
|
||||
break;
|
||||
|
||||
case OPTION_NO_M4900:
|
||||
mips_4900 = 0;
|
||||
break;
|
||||
|
||||
/* end-sanitize-tx49 */
|
||||
|
@ -9927,10 +9854,44 @@ md_parse_option (c, arg)
|
|||
return 1;
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
show (stream, string, col_p, first_p)
|
||||
FILE *stream;
|
||||
char *string;
|
||||
int *col_p;
|
||||
int *first_p;
|
||||
{
|
||||
if (*first_p)
|
||||
{
|
||||
fprintf (stream, "%24s", "");
|
||||
*col_p = 24;
|
||||
}
|
||||
else
|
||||
{
|
||||
fprintf (stream, ", ");
|
||||
*col_p += 2;
|
||||
}
|
||||
|
||||
if (*col_p + strlen (string) > 72)
|
||||
{
|
||||
fprintf (stream, "\n%24s", "");
|
||||
*col_p = 24;
|
||||
}
|
||||
|
||||
fprintf (stream, "%s", string);
|
||||
*col_p += strlen (string);
|
||||
|
||||
*first_p = 0;
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
md_show_usage (stream)
|
||||
FILE *stream;
|
||||
{
|
||||
int column, first;
|
||||
|
||||
fprintf(stream, _("\
|
||||
MIPS options:\n\
|
||||
-membedded-pic generate embedded position independent code\n\
|
||||
|
@ -9944,22 +9905,76 @@ MIPS options:\n\
|
|||
-mips2 generate MIPS ISA II instructions\n\
|
||||
-mips3 generate MIPS ISA III instructions\n\
|
||||
-mips4 generate MIPS ISA IV instructions\n\
|
||||
-mcpu=vr4300 generate code for vr4300\n\
|
||||
-mcpu=vr4100 generate code for vr4100\n\
|
||||
-m4650 permit R4650 instructions\n\
|
||||
-no-m4650 do not permit R4650 instructions\n\
|
||||
-m4010 permit R4010 instructions\n\
|
||||
-no-m4010 do not permit R4010 instructions\n\
|
||||
-m4100 permit VR4100 instructions\n\
|
||||
-no-m4100 do not permit VR4100 instructions\n"));
|
||||
-mcpu=CPU generate code for CPU, where CPU is one of:\n"));
|
||||
|
||||
first = 1;
|
||||
|
||||
/* start-sanitize-tx19 */
|
||||
show (stream, "1900", &column, &first);
|
||||
/* end-sanitize-tx19 */
|
||||
show (stream, "2000", &column, &first);
|
||||
show (stream, "3000", &column, &first);
|
||||
show (stream, "3900", &column, &first);
|
||||
show (stream, "4000", &column, &first);
|
||||
show (stream, "4010", &column, &first);
|
||||
show (stream, "4100", &column, &first);
|
||||
/* start-sanitize-vr4xxx */
|
||||
fprintf(stream, _("\
|
||||
-mcpu=vr4111 generate code for vr4111\n"));
|
||||
fprintf(stream, _("\
|
||||
-mcpu=vr4121 generate code for vr4121\n\
|
||||
-m4121 permit VR4121 instructions\n\
|
||||
-no-m4121 do not permit VR4121 instructions\n"));
|
||||
show (stream, "4111", &column, &first);
|
||||
show (stream, "4121", &column, &first);
|
||||
/* end-sanitize-vr4xxx */
|
||||
show (stream, "4300", &column, &first);
|
||||
/* start-sanitize-vr4320 */
|
||||
show (stream, "4320", &column, &first);
|
||||
/* end-sanitize-vr4320 */
|
||||
show (stream, "4400", &column, &first);
|
||||
show (stream, "4600", &column, &first);
|
||||
show (stream, "4650", &column, &first);
|
||||
/* start-sanitize-tx49 */
|
||||
show (stream, "4900", &column, &first);
|
||||
/* end-sanitize-tx49 */
|
||||
show (stream, "5000", &column, &first);
|
||||
/* start-sanitize-cygnus */
|
||||
show (stream, "5400", &column, &first);
|
||||
/* end-sanitize-cygnus */
|
||||
/* start-sanitize-r5900 */
|
||||
show (stream, "5900", &column, &first);
|
||||
/* end-sanitize-r5900 */
|
||||
show (stream, "6000", &column, &first);
|
||||
show (stream, "8000", &column, &first);
|
||||
show (stream, "10000", &column, &first);
|
||||
fputc ('\n', stream);
|
||||
|
||||
fprintf (stream, _("\
|
||||
-mCPU equivalent to -mcpu=CPU.\n\
|
||||
-no-mCPU don't generate code for CPU.\n\
|
||||
For -mCPU and -no-mCPU, CPU must be one of:\n"));
|
||||
|
||||
first = 1;
|
||||
|
||||
/* start-sanitize-tx19 */
|
||||
show (stream, "1900", &column, &first);
|
||||
/* end-sanitize-tx19 */
|
||||
show (stream, "3900", &column, &first);
|
||||
show (stream, "4010", &column, &first);
|
||||
show (stream, "4100", &column, &first);
|
||||
/* start-sanitize-vr4xxx */
|
||||
show (stream, "4121", &column, &first);
|
||||
/* end-sanitize-vr4xxx */
|
||||
/* start-sanitize-vr4320 */
|
||||
show (stream, "4320", &column, &first);
|
||||
/* end-sanitize-vr4320 */
|
||||
show (stream, "4650", &column, &first);
|
||||
/* start-sanitize-tx49 */
|
||||
show (stream, "4900", &column, &first);
|
||||
/* end-sanitize-tx49 */
|
||||
/* start-sanitize-cygnus */
|
||||
show (stream, "5400", &column, &first);
|
||||
/* end-sanitize-cygnus */
|
||||
/* start-sanitize-r5900 */
|
||||
show (stream, "5900", &column, &first);
|
||||
/* end-sanitize-r5900 */
|
||||
fputc ('\n', stream);
|
||||
|
||||
fprintf(stream, _("\
|
||||
-mips16 generate mips16 instructions\n\
|
||||
-no-mips16 do not generate mips16 instructions\n"));
|
||||
|
@ -10125,9 +10140,12 @@ mips_frob_file ()
|
|||
if (f != NULL)
|
||||
break;
|
||||
|
||||
#if 0 /* GCC code motion plus incomplete dead code elimination
|
||||
can leave a %hi without a %lo. */
|
||||
if (pass == 1)
|
||||
as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
|
||||
_("Unmatched %%hi reloc"));
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue