RISC-V: Add description for RISC-V Modifiers to as doc.
gas/ * doc/c-riscv.texi (relocation modifiers): Add documentation. (RISC-V-Formats): Update the section name from "Instruction Formats" to "RISC-V Instruction Formats".
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Nelson Chu
Jim Wilson
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2020-03-04 Nelson Chu <nelson.chu@sifive.com>
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* doc/c-riscv.texi (relocation modifiers): Add documentation.
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(RISC-V-Formats): Update the section name from "Instruction Formats"
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to "RISC-V Instruction Formats".
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2020-03-04 Alexandre Oliva <oliva@adacore.com>
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* config/tc-arm.c (md_apply_fix): Warn if a PC-relative load is
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@ -17,6 +17,7 @@
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@menu
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* RISC-V-Options:: RISC-V Options
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* RISC-V-Directives:: RISC-V Directives
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* RISC-V-Modifiers:: RISC-V Assembler Modifiers
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* RISC-V-Formats:: RISC-V Instruction Formats
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* RISC-V-ATTRIBUTE:: RISC-V Object Attribute
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@end menu
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@ -207,8 +208,117 @@ The @var{tag} is either an attribute number, or one of the following:
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@end table
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@node RISC-V-Modifiers
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@section RISC-V Assembler Modifiers
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The RISC-V assembler supports following modifiers for relocatable addresses
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used in RISC-V instruction operands. However, we also support some pseudo
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instructions that are easier to use than these modifiers.
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@table @code
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@item %lo(@var{symbol})
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The low 12 bits of absolute address for @var{symbol}.
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@item %hi(@var{symbol})
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The high 20 bits of absolute address for @var{symbol}. This is usually
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used with the %lo modifier to represent a 32-bit absolute address.
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@smallexample
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lui a0, %hi(@var{symbol}) // R_RISCV_HI20
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addi a0, a0, %lo(@var{symbol}) // R_RISCV_LO12_I
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lui a0, %hi(@var{symbol}) // R_RISCV_HI20
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load/store a0, %lo(@var{symbol})(a0) // R_RISCV_LO12_I/S
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@end smallexample
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@item %pcrel_lo(@var{label})
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The low 12 bits of relative address between pc and @var{symbol}.
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The @var{symbol} is related to the high part instruction which is marked
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by @var{label}.
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@item %pcrel_hi(@var{symbol})
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The high 20 bits of relative address between pc and @var{symbol}.
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This is usually used with the %pcrel_lo modifier to represent a +/-2GB
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pc-relative range.
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@smallexample
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@var{label}:
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auipc a0, %pcrel_hi(@var{symbol}) // R_RISCV_PCREL_HI20
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addi a0, a0, %pcrel_lo(@var{label}) // R_RISCV_PCREL_LO12_I
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@var{label}:
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auipc a0, %pcrel_hi(@var{symbol}) // R_RISCV_PCREL_HI20
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load/store a0, %pcrel_lo(@var{label})(a0) // R_RISCV_PCREL_LO12_I/S
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@end smallexample
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Or you can use the pseudo lla/lw/sw/... instruction to do this.
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@smallexample
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lla a0, @var{symbol}
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@end smallexample
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@item %tprel_add(@var{symbol})
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This is used purely to associate the R_RISCV_TPREL_ADD relocation for
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TLS relaxation. This one is only valid as the fourth operand to the normally
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3 operand add instruction.
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@item %tprel_lo(@var{symbol})
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The low 12 bits of relative address between tp and @var{symbol}.
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@item %tprel_hi(@var{symbol})
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The high 20 bits of relative address between tp and @var{symbol}. This is
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usually used with the %tprel_lo and %tprel_add modifiers to access the thread
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local variable @var{symbol} in TLS Local Exec.
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@smallexample
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lui a5, %tprel_hi(@var{symbol}) // R_RISCV_TPREL_HI20
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add a5, a5, tp, %tprel_add(@var{symbol}) // R_RISCV_TPREL_ADD
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load/store t0, %tprel_lo(@var{symbol})(a5) // R_RISCV_TPREL_LO12_I/S
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@end smallexample
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@item %tls_ie_pcrel_hi(@var{symbol})
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The high 20 bits of relative address between pc and GOT entry. It is
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usually used with the %pcrel_lo modifier to access the thread local
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variable @var{symbol} in TLS Initial Exec.
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@smallexample
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la.tls.ie a5, @var{symbol}
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add a5, a5, tp
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load/store t0, 0(a5)
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@end smallexample
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The pseudo la.tls.ie instruction can be expended to
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@smallexample
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@var{label}:
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auipc a5, %tls_ie_pcrel_hi(@var{symbol}) // R_RISCV_TLS_GOT_HI20
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load a5, %pcrel_lo(@var{label})(a5) // R_RISCV_PCREL_LO12_I
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@end smallexample
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@item %tls_gd_pcrel_hi(@var{symbol})
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The high 20 bits of relative address between pc and GOT entry. It is
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usually used with the %pcrel_lo modifier to access the thread local variable
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@var{symbol} in TLS Global Dynamic.
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@smallexample
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la.tls.gd a0, @var{symbol}
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call __tls_get_addr@@plt
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mv a5, a0
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load/store t0, 0(a5)
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@end smallexample
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The pseudo la.tls.gd instruction can be expended to
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@smallexample
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@var{label}:
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auipc a0, %tls_gd_pcrel_hi(@var{symbol}) // R_RISCV_TLS_GD_HI20
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addi a0, a0, %pcrel_lo(@var{label}) // R_RISCV_PCREL_LO12_I
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@end smallexample
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@end table
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@node RISC-V-Formats
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@section Instruction Formats
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@section RISC-V Instruction Formats
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@cindex instruction formats, risc-v
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@cindex RISC-V instruction formats
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