Thu Dec 17 17:18:43 1998 Dave Brolley <brolley@cygnus.com>
* sim/fr30/testutils.inc (take_branch{_d},no_branch{_d}): New macros.
* sim/fr30/ret.cgs: Add tests fir ret:d.
* sim/fr30/inte.cgs: New testcase.
* sim/fr30/reti.cgs: New testcase.
* sim/fr30/bra.cgs: New testcase.
* sim/fr30/bno.cgs: New testcase.
* sim/fr30/beq.cgs: New testcase.
* sim/fr30/bne.cgs: New testcase.
* sim/fr30/bc.cgs: New testcase.
* sim/fr30/bnc.cgs: New testcase.
* sim/fr30/bn.cgs: New testcase.
* sim/fr30/bp.cgs: New testcase.
* sim/fr30/bv.cgs: New testcase.
* sim/fr30/bnv.cgs: New testcase.
* sim/fr30/blt.cgs: New testcase.
* sim/fr30/bge.cgs: New testcase.
* sim/fr30/ble.cgs: New testcase.
* sim/fr30/bgt.cgs: New testcase.
* sim/fr30/bls.cgs: New testcase.
* sim/fr30/bhi.cgs: New testcase.
This commit is contained in:
Dave Brolley
parent
f7fb02ba10
commit
de6fb7e775
109
sim/testsuite/sim/fr30/bc.cgs
Normal file
109
sim/testsuite/sim/fr30/bc.cgs
Normal file
@ -0,0 +1,109 @@
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# fr30 testcase for bc $label9
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# mach(): fr30
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.include "testutils.inc"
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START
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.text
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.global bc
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bc:
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; Test bc $label9
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set_cc 0x0f ; condition codes are irrelevent
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take_branch bc
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set_cc 0x0e ; condition codes are irrelevent
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no_branch bc
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set_cc 0x0d ; condition codes are irrelevent
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take_branch bc
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set_cc 0x0c ; condition codes are irrelevent
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no_branch bc
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set_cc 0x0b ; condition codes are irrelevent
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take_branch bc
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set_cc 0x0a ; condition codes are irrelevent
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no_branch bc
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set_cc 0x09 ; condition codes are irrelevent
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take_branch bc
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set_cc 0x08 ; condition codes are irrelevent
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no_branch bc
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set_cc 0x07 ; condition codes are irrelevent
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take_branch bc
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set_cc 0x06 ; condition codes are irrelevent
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no_branch bc
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set_cc 0x05 ; condition codes are irrelevent
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take_branch bc
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set_cc 0x04 ; condition codes are irrelevent
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no_branch bc
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set_cc 0x03 ; condition codes are irrelevent
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take_branch bc
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set_cc 0x02 ; condition codes are irrelevent
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no_branch bc
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set_cc 0x01 ; condition codes are irrelevent
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take_branch bc
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set_cc 0x00 ; condition codes are irrelevent
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no_branch bc
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; Test bc:d label9
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set_cc 0x0f ; condition codes are irrelevent
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take_branch_d bc:d 0xf
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set_cc 0x0e ; condition codes are irrelevent
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no_branch_d bc:d 0xe
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set_cc 0x0d ; condition codes are irrelevent
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take_branch_d bc:d 0xd
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set_cc 0x0c ; condition codes are irrelevent
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no_branch_d bc:d 0xc
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set_cc 0x0b ; condition codes are irrelevent
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take_branch_d bc:d 0xb
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set_cc 0x0a ; condition codes are irrelevent
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no_branch_d bc:d 0xa
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set_cc 0x09 ; condition codes are irrelevent
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take_branch_d bc:d 0x9
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set_cc 0x08 ; condition codes are irrelevent
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no_branch_d bc:d 0x8
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set_cc 0x07 ; condition codes are irrelevent
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take_branch_d bc:d 0x7
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set_cc 0x06 ; condition codes are irrelevent
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no_branch_d bc:d 0x6
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set_cc 0x05 ; condition codes are irrelevent
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take_branch_d bc:d 0x5
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set_cc 0x04 ; condition codes are irrelevent
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no_branch_d bc:d 0x4
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set_cc 0x03 ; condition codes are irrelevent
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take_branch_d bc:d 0x3
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set_cc 0x02 ; condition codes are irrelevent
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no_branch_d bc:d 0x2
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set_cc 0x01 ; condition codes are irrelevent
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take_branch_d bc:d 0x1
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set_cc 0x00 ; condition codes are irrelevent
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no_branch_d bc:d 0x0
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pass
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109
sim/testsuite/sim/fr30/beq.cgs
Normal file
109
sim/testsuite/sim/fr30/beq.cgs
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# fr30 testcase for beq $label9
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# mach(): fr30
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.include "testutils.inc"
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START
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.text
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.global beq
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beq:
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; Test beq $label9
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set_cc 0x0f ; condition codes are irrelevent
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take_branch beq
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set_cc 0x0e ; condition codes are irrelevent
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take_branch beq
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set_cc 0x0d ; condition codes are irrelevent
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take_branch beq
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set_cc 0x0c ; condition codes are irrelevent
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take_branch beq
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set_cc 0x0b ; condition codes are irrelevent
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no_branch beq
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set_cc 0x0a ; condition codes are irrelevent
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no_branch beq
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set_cc 0x09 ; condition codes are irrelevent
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no_branch beq
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set_cc 0x08 ; condition codes are irrelevent
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no_branch beq
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set_cc 0x07 ; condition codes are irrelevent
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take_branch beq
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set_cc 0x06 ; condition codes are irrelevent
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take_branch beq
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set_cc 0x05 ; condition codes are irrelevent
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take_branch beq
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set_cc 0x04 ; condition codes are irrelevent
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take_branch beq
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set_cc 0x03 ; condition codes are irrelevent
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no_branch beq
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set_cc 0x02 ; condition codes are irrelevent
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no_branch beq
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set_cc 0x01 ; condition codes are irrelevent
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no_branch beq
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set_cc 0x00 ; condition codes are irrelevent
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no_branch beq
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; Test beq:d label9
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set_cc 0x0f ; condition codes are irrelevent
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take_branch_d beq:d 0xf
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set_cc 0x0e ; condition codes are irrelevent
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take_branch_d beq:d 0xe
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set_cc 0x0d ; condition codes are irrelevent
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take_branch_d beq:d 0xd
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set_cc 0x0c ; condition codes are irrelevent
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take_branch_d beq:d 0xc
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set_cc 0x0b ; condition codes are irrelevent
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no_branch_d beq:d 0xb
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set_cc 0x0a ; condition codes are irrelevent
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no_branch_d beq:d 0xa
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set_cc 0x09 ; condition codes are irrelevent
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no_branch_d beq:d 0x9
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set_cc 0x08 ; condition codes are irrelevent
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no_branch_d beq:d 0x8
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set_cc 0x07 ; condition codes are irrelevent
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take_branch_d beq:d 0x7
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set_cc 0x06 ; condition codes are irrelevent
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take_branch_d beq:d 0x6
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set_cc 0x05 ; condition codes are irrelevent
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take_branch_d beq:d 0x5
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set_cc 0x04 ; condition codes are irrelevent
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take_branch_d beq:d 0x4
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set_cc 0x03 ; condition codes are irrelevent
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no_branch_d beq:d 0x3
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set_cc 0x02 ; condition codes are irrelevent
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no_branch_d beq:d 0x2
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set_cc 0x01 ; condition codes are irrelevent
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no_branch_d beq:d 0x1
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set_cc 0x00 ; condition codes are irrelevent
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no_branch_d beq:d 0x0
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pass
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109
sim/testsuite/sim/fr30/bge.cgs
Normal file
109
sim/testsuite/sim/fr30/bge.cgs
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@ -0,0 +1,109 @@
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# fr30 testcase for bge $label9
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# mach(): fr30
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.include "testutils.inc"
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START
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.text
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.global bge
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bge:
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; Test bge $label9
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set_cc 0x0f ; condition codes are irrelevent
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take_branch bge
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set_cc 0x0e ; condition codes are irrelevent
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take_branch bge
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set_cc 0x0d ; condition codes are irrelevent
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no_branch bge
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set_cc 0x0c ; condition codes are irrelevent
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no_branch bge
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set_cc 0x0b ; condition codes are irrelevent
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take_branch bge
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set_cc 0x0a ; condition codes are irrelevent
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take_branch bge
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set_cc 0x09 ; condition codes are irrelevent
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no_branch bge
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set_cc 0x08 ; condition codes are irrelevent
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no_branch bge
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set_cc 0x07 ; condition codes are irrelevent
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no_branch bge
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set_cc 0x06 ; condition codes are irrelevent
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no_branch bge
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set_cc 0x05 ; condition codes are irrelevent
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take_branch bge
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set_cc 0x04 ; condition codes are irrelevent
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take_branch bge
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set_cc 0x03 ; condition codes are irrelevent
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no_branch bge
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set_cc 0x02 ; condition codes are irrelevent
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no_branch bge
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set_cc 0x01 ; condition codes are irrelevent
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take_branch bge
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set_cc 0x00 ; condition codes are irrelevent
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take_branch bge
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; Test bge:d label9
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set_cc 0x0f ; condition codes are irrelevent
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take_branch_d bge:d 0xf
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set_cc 0x0e ; condition codes are irrelevent
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take_branch_d bge:d 0xe
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set_cc 0x0d ; condition codes are irrelevent
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no_branch_d bge:d 0xd
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set_cc 0x0c ; condition codes are irrelevent
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no_branch_d bge:d 0xc
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set_cc 0x0b ; condition codes are irrelevent
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take_branch_d bge:d 0xb
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set_cc 0x0a ; condition codes are irrelevent
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take_branch_d bge:d 0xa
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set_cc 0x09 ; condition codes are irrelevent
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no_branch_d bge:d 0x9
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set_cc 0x08 ; condition codes are irrelevent
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no_branch_d bge:d 0x8
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set_cc 0x07 ; condition codes are irrelevent
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no_branch_d bge:d 0x7
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set_cc 0x06 ; condition codes are irrelevent
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no_branch_d bge:d 0x6
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set_cc 0x05 ; condition codes are irrelevent
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take_branch_d bge:d 0x5
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set_cc 0x04 ; condition codes are irrelevent
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take_branch_d bge:d 0x4
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set_cc 0x03 ; condition codes are irrelevent
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no_branch_d bge:d 0x3
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set_cc 0x02 ; condition codes are irrelevent
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no_branch_d bge:d 0x2
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set_cc 0x01 ; condition codes are irrelevent
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take_branch_d bge:d 0x1
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set_cc 0x00 ; condition codes are irrelevent
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take_branch_d bge:d 0x0
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pass
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109
sim/testsuite/sim/fr30/bgt.cgs
Normal file
109
sim/testsuite/sim/fr30/bgt.cgs
Normal file
@ -0,0 +1,109 @@
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# fr30 testcase for bgt $label9
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# mach(): fr30
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.include "testutils.inc"
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START
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.text
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.global bgt
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bgt:
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; Test bgt $label9
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set_cc 0x0f ; condition codes are irrelevent
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no_branch bgt
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set_cc 0x0e ; condition codes are irrelevent
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no_branch bgt
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set_cc 0x0d ; condition codes are irrelevent
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no_branch bgt
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set_cc 0x0c ; condition codes are irrelevent
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no_branch bgt
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set_cc 0x0b ; condition codes are irrelevent
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take_branch bgt
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set_cc 0x0a ; condition codes are irrelevent
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take_branch bgt
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set_cc 0x09 ; condition codes are irrelevent
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no_branch bgt
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set_cc 0x08 ; condition codes are irrelevent
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no_branch bgt
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set_cc 0x07 ; condition codes are irrelevent
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no_branch bgt
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set_cc 0x06 ; condition codes are irrelevent
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no_branch bgt
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set_cc 0x05 ; condition codes are irrelevent
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no_branch bgt
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set_cc 0x04 ; condition codes are irrelevent
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no_branch bgt
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set_cc 0x03 ; condition codes are irrelevent
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no_branch bgt
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set_cc 0x02 ; condition codes are irrelevent
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no_branch bgt
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set_cc 0x01 ; condition codes are irrelevent
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take_branch bgt
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set_cc 0x00 ; condition codes are irrelevent
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take_branch bgt
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; Test bgt:d label9
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set_cc 0x0f ; condition codes are irrelevent
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no_branch_d bgt:d 0xf
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set_cc 0x0e ; condition codes are irrelevent
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no_branch_d bgt:d 0xe
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set_cc 0x0d ; condition codes are irrelevent
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no_branch_d bgt:d 0xd
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set_cc 0x0c ; condition codes are irrelevent
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no_branch_d bgt:d 0xc
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set_cc 0x0b ; condition codes are irrelevent
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take_branch_d bgt:d 0xb
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set_cc 0x0a ; condition codes are irrelevent
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take_branch_d bgt:d 0xa
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set_cc 0x09 ; condition codes are irrelevent
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no_branch_d bgt:d 0x9
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set_cc 0x08 ; condition codes are irrelevent
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no_branch_d bgt:d 0x8
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set_cc 0x07 ; condition codes are irrelevent
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no_branch_d bgt:d 0x7
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set_cc 0x06 ; condition codes are irrelevent
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no_branch_d bgt:d 0x6
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set_cc 0x05 ; condition codes are irrelevent
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no_branch_d bgt:d 0x5
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set_cc 0x04 ; condition codes are irrelevent
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no_branch_d bgt:d 0x4
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set_cc 0x03 ; condition codes are irrelevent
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no_branch_d bgt:d 0x3
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set_cc 0x02 ; condition codes are irrelevent
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no_branch_d bgt:d 0x2
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set_cc 0x01 ; condition codes are irrelevent
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take_branch_d bgt:d 0x1
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set_cc 0x00 ; condition codes are irrelevent
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take_branch_d bgt:d 0x0
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pass
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109
sim/testsuite/sim/fr30/bhi.cgs
Normal file
109
sim/testsuite/sim/fr30/bhi.cgs
Normal file
@ -0,0 +1,109 @@
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# fr30 testcase for bhi $label9
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# mach(): fr30
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.include "testutils.inc"
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START
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.text
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.global bhi
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bhi:
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; Test bhi $label9
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set_cc 0x0f ; condition codes are irrelevent
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no_branch bhi
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set_cc 0x0e ; condition codes are irrelevent
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no_branch bhi
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set_cc 0x0d ; condition codes are irrelevent
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no_branch bhi
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set_cc 0x0c ; condition codes are irrelevent
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no_branch bhi
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set_cc 0x0b ; condition codes are irrelevent
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no_branch bhi
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set_cc 0x0a ; condition codes are irrelevent
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take_branch bhi
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set_cc 0x09 ; condition codes are irrelevent
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no_branch bhi
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set_cc 0x08 ; condition codes are irrelevent
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take_branch bhi
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set_cc 0x07 ; condition codes are irrelevent
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no_branch bhi
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set_cc 0x06 ; condition codes are irrelevent
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no_branch bhi
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set_cc 0x05 ; condition codes are irrelevent
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no_branch bhi
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set_cc 0x04 ; condition codes are irrelevent
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no_branch bhi
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set_cc 0x03 ; condition codes are irrelevent
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no_branch bhi
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set_cc 0x02 ; condition codes are irrelevent
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take_branch bhi
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set_cc 0x01 ; condition codes are irrelevent
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no_branch bhi
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set_cc 0x00 ; condition codes are irrelevent
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take_branch bhi
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; Test bhi:d label9
|
||||
set_cc 0x0f ; condition codes are irrelevent
|
||||
no_branch_d bhi:d 0xf
|
||||
|
||||
set_cc 0x0e ; condition codes are irrelevent
|
||||
no_branch_d bhi:d 0xe
|
||||
|
||||
set_cc 0x0d ; condition codes are irrelevent
|
||||
no_branch_d bhi:d 0xd
|
||||
|
||||
set_cc 0x0c ; condition codes are irrelevent
|
||||
no_branch_d bhi:d 0xc
|
||||
|
||||
set_cc 0x0b ; condition codes are irrelevent
|
||||
no_branch_d bhi:d 0xb
|
||||
|
||||
set_cc 0x0a ; condition codes are irrelevent
|
||||
take_branch_d bhi:d 0xa
|
||||
|
||||
set_cc 0x09 ; condition codes are irrelevent
|
||||
no_branch_d bhi:d 0x9
|
||||
|
||||
set_cc 0x08 ; condition codes are irrelevent
|
||||
take_branch_d bhi:d 0x8
|
||||
|
||||
set_cc 0x07 ; condition codes are irrelevent
|
||||
no_branch_d bhi:d 0x7
|
||||
|
||||
set_cc 0x06 ; condition codes are irrelevent
|
||||
no_branch_d bhi:d 0x6
|
||||
|
||||
set_cc 0x05 ; condition codes are irrelevent
|
||||
no_branch_d bhi:d 0x5
|
||||
|
||||
set_cc 0x04 ; condition codes are irrelevent
|
||||
no_branch_d bhi:d 0x4
|
||||
|
||||
set_cc 0x03 ; condition codes are irrelevent
|
||||
no_branch_d bhi:d 0x3
|
||||
|
||||
set_cc 0x02 ; condition codes are irrelevent
|
||||
take_branch_d bhi:d 0x2
|
||||
|
||||
set_cc 0x01 ; condition codes are irrelevent
|
||||
no_branch_d bhi:d 0x1
|
||||
|
||||
set_cc 0x00 ; condition codes are irrelevent
|
||||
take_branch_d bhi:d 0x0
|
||||
|
||||
pass
|
||||
109
sim/testsuite/sim/fr30/ble.cgs
Normal file
109
sim/testsuite/sim/fr30/ble.cgs
Normal file
@ -0,0 +1,109 @@
|
||||
# fr30 testcase for ble $label9
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global ble
|
||||
ble:
|
||||
; Test ble $label9
|
||||
set_cc 0x0f ; condition codes are irrelevent
|
||||
take_branch ble
|
||||
|
||||
set_cc 0x0e ; condition codes are irrelevent
|
||||
take_branch ble
|
||||
|
||||
set_cc 0x0d ; condition codes are irrelevent
|
||||
take_branch ble
|
||||
|
||||
set_cc 0x0c ; condition codes are irrelevent
|
||||
take_branch ble
|
||||
|
||||
set_cc 0x0b ; condition codes are irrelevent
|
||||
no_branch ble
|
||||
|
||||
set_cc 0x0a ; condition codes are irrelevent
|
||||
no_branch ble
|
||||
|
||||
set_cc 0x09 ; condition codes are irrelevent
|
||||
take_branch ble
|
||||
|
||||
set_cc 0x08 ; condition codes are irrelevent
|
||||
take_branch ble
|
||||
|
||||
set_cc 0x07 ; condition codes are irrelevent
|
||||
take_branch ble
|
||||
|
||||
set_cc 0x06 ; condition codes are irrelevent
|
||||
take_branch ble
|
||||
|
||||
set_cc 0x05 ; condition codes are irrelevent
|
||||
take_branch ble
|
||||
|
||||
set_cc 0x04 ; condition codes are irrelevent
|
||||
take_branch ble
|
||||
|
||||
set_cc 0x03 ; condition codes are irrelevent
|
||||
take_branch ble
|
||||
|
||||
set_cc 0x02 ; condition codes are irrelevent
|
||||
take_branch ble
|
||||
|
||||
set_cc 0x01 ; condition codes are irrelevent
|
||||
no_branch ble
|
||||
|
||||
set_cc 0x00 ; condition codes are irrelevent
|
||||
no_branch ble
|
||||
|
||||
; Test ble:d label9
|
||||
set_cc 0x0f ; condition codes are irrelevent
|
||||
take_branch_d ble:d 0xf
|
||||
|
||||
set_cc 0x0e ; condition codes are irrelevent
|
||||
take_branch_d ble:d 0xe
|
||||
|
||||
set_cc 0x0d ; condition codes are irrelevent
|
||||
take_branch_d ble:d 0xd
|
||||
|
||||
set_cc 0x0c ; condition codes are irrelevent
|
||||
take_branch_d ble:d 0xc
|
||||
|
||||
set_cc 0x0b ; condition codes are irrelevent
|
||||
no_branch_d ble:d 0xb
|
||||
|
||||
set_cc 0x0a ; condition codes are irrelevent
|
||||
no_branch_d ble:d 0xa
|
||||
|
||||
set_cc 0x09 ; condition codes are irrelevent
|
||||
take_branch_d ble:d 0x9
|
||||
|
||||
set_cc 0x08 ; condition codes are irrelevent
|
||||
take_branch_d ble:d 0x8
|
||||
|
||||
set_cc 0x07 ; condition codes are irrelevent
|
||||
take_branch_d ble:d 0x7
|
||||
|
||||
set_cc 0x06 ; condition codes are irrelevent
|
||||
take_branch_d ble:d 0x6
|
||||
|
||||
set_cc 0x05 ; condition codes are irrelevent
|
||||
take_branch_d ble:d 0x5
|
||||
|
||||
set_cc 0x04 ; condition codes are irrelevent
|
||||
take_branch_d ble:d 0x4
|
||||
|
||||
set_cc 0x03 ; condition codes are irrelevent
|
||||
take_branch_d ble:d 0x3
|
||||
|
||||
set_cc 0x02 ; condition codes are irrelevent
|
||||
take_branch_d ble:d 0x2
|
||||
|
||||
set_cc 0x01 ; condition codes are irrelevent
|
||||
no_branch_d ble:d 0x1
|
||||
|
||||
set_cc 0x00 ; condition codes are irrelevent
|
||||
no_branch_d ble:d 0x0
|
||||
|
||||
pass
|
||||
109
sim/testsuite/sim/fr30/bls.cgs
Normal file
109
sim/testsuite/sim/fr30/bls.cgs
Normal file
@ -0,0 +1,109 @@
|
||||
# fr30 testcase for bls $label9
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global bls
|
||||
bls:
|
||||
; Test bls $label9
|
||||
set_cc 0x0f ; condition codes are irrelevent
|
||||
take_branch bls
|
||||
|
||||
set_cc 0x0e ; condition codes are irrelevent
|
||||
take_branch bls
|
||||
|
||||
set_cc 0x0d ; condition codes are irrelevent
|
||||
take_branch bls
|
||||
|
||||
set_cc 0x0c ; condition codes are irrelevent
|
||||
take_branch bls
|
||||
|
||||
set_cc 0x0b ; condition codes are irrelevent
|
||||
take_branch bls
|
||||
|
||||
set_cc 0x0a ; condition codes are irrelevent
|
||||
no_branch bls
|
||||
|
||||
set_cc 0x09 ; condition codes are irrelevent
|
||||
take_branch bls
|
||||
|
||||
set_cc 0x08 ; condition codes are irrelevent
|
||||
no_branch bls
|
||||
|
||||
set_cc 0x07 ; condition codes are irrelevent
|
||||
take_branch bls
|
||||
|
||||
set_cc 0x06 ; condition codes are irrelevent
|
||||
take_branch bls
|
||||
|
||||
set_cc 0x05 ; condition codes are irrelevent
|
||||
take_branch bls
|
||||
|
||||
set_cc 0x04 ; condition codes are irrelevent
|
||||
take_branch bls
|
||||
|
||||
set_cc 0x03 ; condition codes are irrelevent
|
||||
take_branch bls
|
||||
|
||||
set_cc 0x02 ; condition codes are irrelevent
|
||||
no_branch bls
|
||||
|
||||
set_cc 0x01 ; condition codes are irrelevent
|
||||
take_branch bls
|
||||
|
||||
set_cc 0x00 ; condition codes are irrelevent
|
||||
no_branch bls
|
||||
|
||||
; Test bls:d label9
|
||||
set_cc 0x0f ; condition codes are irrelevent
|
||||
take_branch_d bls:d 0xf
|
||||
|
||||
set_cc 0x0e ; condition codes are irrelevent
|
||||
take_branch_d bls:d 0xe
|
||||
|
||||
set_cc 0x0d ; condition codes are irrelevent
|
||||
take_branch_d bls:d 0xd
|
||||
|
||||
set_cc 0x0c ; condition codes are irrelevent
|
||||
take_branch_d bls:d 0xc
|
||||
|
||||
set_cc 0x0b ; condition codes are irrelevent
|
||||
take_branch_d bls:d 0xb
|
||||
|
||||
set_cc 0x0a ; condition codes are irrelevent
|
||||
no_branch_d bls:d 0xa
|
||||
|
||||
set_cc 0x09 ; condition codes are irrelevent
|
||||
take_branch_d bls:d 0x9
|
||||
|
||||
set_cc 0x08 ; condition codes are irrelevent
|
||||
no_branch_d bls:d 0x8
|
||||
|
||||
set_cc 0x07 ; condition codes are irrelevent
|
||||
take_branch_d bls:d 0x7
|
||||
|
||||
set_cc 0x06 ; condition codes are irrelevent
|
||||
take_branch_d bls:d 0x6
|
||||
|
||||
set_cc 0x05 ; condition codes are irrelevent
|
||||
take_branch_d bls:d 0x5
|
||||
|
||||
set_cc 0x04 ; condition codes are irrelevent
|
||||
take_branch_d bls:d 0x4
|
||||
|
||||
set_cc 0x03 ; condition codes are irrelevent
|
||||
take_branch_d bls:d 0x3
|
||||
|
||||
set_cc 0x02 ; condition codes are irrelevent
|
||||
no_branch_d bls:d 0x2
|
||||
|
||||
set_cc 0x01 ; condition codes are irrelevent
|
||||
take_branch_d bls:d 0x1
|
||||
|
||||
set_cc 0x00 ; condition codes are irrelevent
|
||||
no_branch_d bls:d 0x0
|
||||
|
||||
pass
|
||||
109
sim/testsuite/sim/fr30/blt.cgs
Normal file
109
sim/testsuite/sim/fr30/blt.cgs
Normal file
@ -0,0 +1,109 @@
|
||||
# fr30 testcase for blt $label9
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global blt
|
||||
blt:
|
||||
; Test blt $label9
|
||||
set_cc 0x0f ; condition codes are irrelevent
|
||||
no_branch blt
|
||||
|
||||
set_cc 0x0e ; condition codes are irrelevent
|
||||
no_branch blt
|
||||
|
||||
set_cc 0x0d ; condition codes are irrelevent
|
||||
take_branch blt
|
||||
|
||||
set_cc 0x0c ; condition codes are irrelevent
|
||||
take_branch blt
|
||||
|
||||
set_cc 0x0b ; condition codes are irrelevent
|
||||
no_branch blt
|
||||
|
||||
set_cc 0x0a ; condition codes are irrelevent
|
||||
no_branch blt
|
||||
|
||||
set_cc 0x09 ; condition codes are irrelevent
|
||||
take_branch blt
|
||||
|
||||
set_cc 0x08 ; condition codes are irrelevent
|
||||
take_branch blt
|
||||
|
||||
set_cc 0x07 ; condition codes are irrelevent
|
||||
take_branch blt
|
||||
|
||||
set_cc 0x06 ; condition codes are irrelevent
|
||||
take_branch blt
|
||||
|
||||
set_cc 0x05 ; condition codes are irrelevent
|
||||
no_branch blt
|
||||
|
||||
set_cc 0x04 ; condition codes are irrelevent
|
||||
no_branch blt
|
||||
|
||||
set_cc 0x03 ; condition codes are irrelevent
|
||||
take_branch blt
|
||||
|
||||
set_cc 0x02 ; condition codes are irrelevent
|
||||
take_branch blt
|
||||
|
||||
set_cc 0x01 ; condition codes are irrelevent
|
||||
no_branch blt
|
||||
|
||||
set_cc 0x00 ; condition codes are irrelevent
|
||||
no_branch blt
|
||||
|
||||
; Test blt:d label9
|
||||
set_cc 0x0f ; condition codes are irrelevent
|
||||
no_branch_d blt:d 0xf
|
||||
|
||||
set_cc 0x0e ; condition codes are irrelevent
|
||||
no_branch_d blt:d 0xe
|
||||
|
||||
set_cc 0x0d ; condition codes are irrelevent
|
||||
take_branch_d blt:d 0xd
|
||||
|
||||
set_cc 0x0c ; condition codes are irrelevent
|
||||
take_branch_d blt:d 0xc
|
||||
|
||||
set_cc 0x0b ; condition codes are irrelevent
|
||||
no_branch_d blt:d 0xb
|
||||
|
||||
set_cc 0x0a ; condition codes are irrelevent
|
||||
no_branch_d blt:d 0xa
|
||||
|
||||
set_cc 0x09 ; condition codes are irrelevent
|
||||
take_branch_d blt:d 0x9
|
||||
|
||||
set_cc 0x08 ; condition codes are irrelevent
|
||||
take_branch_d blt:d 0x8
|
||||
|
||||
set_cc 0x07 ; condition codes are irrelevent
|
||||
take_branch_d blt:d 0x7
|
||||
|
||||
set_cc 0x06 ; condition codes are irrelevent
|
||||
take_branch_d blt:d 0x6
|
||||
|
||||
set_cc 0x05 ; condition codes are irrelevent
|
||||
no_branch_d blt:d 0x5
|
||||
|
||||
set_cc 0x04 ; condition codes are irrelevent
|
||||
no_branch_d blt:d 0x4
|
||||
|
||||
set_cc 0x03 ; condition codes are irrelevent
|
||||
take_branch_d blt:d 0x3
|
||||
|
||||
set_cc 0x02 ; condition codes are irrelevent
|
||||
take_branch_d blt:d 0x2
|
||||
|
||||
set_cc 0x01 ; condition codes are irrelevent
|
||||
no_branch_d blt:d 0x1
|
||||
|
||||
set_cc 0x00 ; condition codes are irrelevent
|
||||
no_branch_d blt:d 0x0
|
||||
|
||||
pass
|
||||
109
sim/testsuite/sim/fr30/bn.cgs
Normal file
109
sim/testsuite/sim/fr30/bn.cgs
Normal file
@ -0,0 +1,109 @@
|
||||
# fr30 testcase for bn $label9
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global bn
|
||||
bn:
|
||||
; Test bn $label9
|
||||
set_cc 0x0f ; condition codes are irrelevent
|
||||
take_branch bn
|
||||
|
||||
set_cc 0x0e ; condition codes are irrelevent
|
||||
take_branch bn
|
||||
|
||||
set_cc 0x0d ; condition codes are irrelevent
|
||||
take_branch bn
|
||||
|
||||
set_cc 0x0c ; condition codes are irrelevent
|
||||
take_branch bn
|
||||
|
||||
set_cc 0x0b ; condition codes are irrelevent
|
||||
take_branch bn
|
||||
|
||||
set_cc 0x0a ; condition codes are irrelevent
|
||||
take_branch bn
|
||||
|
||||
set_cc 0x09 ; condition codes are irrelevent
|
||||
take_branch bn
|
||||
|
||||
set_cc 0x08 ; condition codes are irrelevent
|
||||
take_branch bn
|
||||
|
||||
set_cc 0x07 ; condition codes are irrelevent
|
||||
no_branch bn
|
||||
|
||||
set_cc 0x06 ; condition codes are irrelevent
|
||||
no_branch bn
|
||||
|
||||
set_cc 0x05 ; condition codes are irrelevent
|
||||
no_branch bn
|
||||
|
||||
set_cc 0x04 ; condition codes are irrelevent
|
||||
no_branch bn
|
||||
|
||||
set_cc 0x03 ; condition codes are irrelevent
|
||||
no_branch bn
|
||||
|
||||
set_cc 0x02 ; condition codes are irrelevent
|
||||
no_branch bn
|
||||
|
||||
set_cc 0x01 ; condition codes are irrelevent
|
||||
no_branch bn
|
||||
|
||||
set_cc 0x00 ; condition codes are irrelevent
|
||||
no_branch bn
|
||||
|
||||
; Test bn:d label9
|
||||
set_cc 0x0f ; condition codes are irrelevent
|
||||
take_branch_d bn:d 0xf
|
||||
|
||||
set_cc 0x0e ; condition codes are irrelevent
|
||||
take_branch_d bn:d 0xe
|
||||
|
||||
set_cc 0x0d ; condition codes are irrelevent
|
||||
take_branch_d bn:d 0xd
|
||||
|
||||
set_cc 0x0c ; condition codes are irrelevent
|
||||
take_branch_d bn:d 0xc
|
||||
|
||||
set_cc 0x0b ; condition codes are irrelevent
|
||||
take_branch_d bn:d 0xb
|
||||
|
||||
set_cc 0x0a ; condition codes are irrelevent
|
||||
take_branch_d bn:d 0xa
|
||||
|
||||
set_cc 0x09 ; condition codes are irrelevent
|
||||
take_branch_d bn:d 0x9
|
||||
|
||||
set_cc 0x08 ; condition codes are irrelevent
|
||||
take_branch_d bn:d 0x8
|
||||
|
||||
set_cc 0x07 ; condition codes are irrelevent
|
||||
no_branch_d bn:d 0x7
|
||||
|
||||
set_cc 0x06 ; condition codes are irrelevent
|
||||
no_branch_d bn:d 0x6
|
||||
|
||||
set_cc 0x05 ; condition codes are irrelevent
|
||||
no_branch_d bn:d 0x5
|
||||
|
||||
set_cc 0x04 ; condition codes are irrelevent
|
||||
no_branch_d bn:d 0x4
|
||||
|
||||
set_cc 0x03 ; condition codes are irrelevent
|
||||
no_branch_d bn:d 0x3
|
||||
|
||||
set_cc 0x02 ; condition codes are irrelevent
|
||||
no_branch_d bn:d 0x2
|
||||
|
||||
set_cc 0x01 ; condition codes are irrelevent
|
||||
no_branch_d bn:d 0x1
|
||||
|
||||
set_cc 0x00 ; condition codes are irrelevent
|
||||
no_branch_d bn:d 0x0
|
||||
|
||||
pass
|
||||
109
sim/testsuite/sim/fr30/bnc.cgs
Normal file
109
sim/testsuite/sim/fr30/bnc.cgs
Normal file
@ -0,0 +1,109 @@
|
||||
# fr30 testcase for bnc $label9
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global bnc
|
||||
bc:
|
||||
; Test bnc $label9
|
||||
set_cc 0x0f ; condition codes are irrelevent
|
||||
no_branch bnc
|
||||
|
||||
set_cc 0x0e ; condition codes are irrelevent
|
||||
take_branch bnc
|
||||
|
||||
set_cc 0x0d ; condition codes are irrelevent
|
||||
no_branch bnc
|
||||
|
||||
set_cc 0x0c ; condition codes are irrelevent
|
||||
take_branch bnc
|
||||
|
||||
set_cc 0x0b ; condition codes are irrelevent
|
||||
no_branch bnc
|
||||
|
||||
set_cc 0x0a ; condition codes are irrelevent
|
||||
take_branch bnc
|
||||
|
||||
set_cc 0x09 ; condition codes are irrelevent
|
||||
no_branch bnc
|
||||
|
||||
set_cc 0x08 ; condition codes are irrelevent
|
||||
take_branch bnc
|
||||
|
||||
set_cc 0x07 ; condition codes are irrelevent
|
||||
no_branch bnc
|
||||
|
||||
set_cc 0x06 ; condition codes are irrelevent
|
||||
take_branch bnc
|
||||
|
||||
set_cc 0x05 ; condition codes are irrelevent
|
||||
no_branch bnc
|
||||
|
||||
set_cc 0x04 ; condition codes are irrelevent
|
||||
take_branch bnc
|
||||
|
||||
set_cc 0x03 ; condition codes are irrelevent
|
||||
no_branch bnc
|
||||
|
||||
set_cc 0x02 ; condition codes are irrelevent
|
||||
take_branch bnc
|
||||
|
||||
set_cc 0x01 ; condition codes are irrelevent
|
||||
no_branch bnc
|
||||
|
||||
set_cc 0x00 ; condition codes are irrelevent
|
||||
take_branch bnc
|
||||
|
||||
; Test bnc:d label9
|
||||
set_cc 0x0f ; condition codes are irrelevent
|
||||
no_branch_d bnc:d 0xf
|
||||
|
||||
set_cc 0x0e ; condition codes are irrelevent
|
||||
take_branch_d bnc:d 0xe
|
||||
|
||||
set_cc 0x0d ; condition codes are irrelevent
|
||||
no_branch_d bnc:d 0xd
|
||||
|
||||
set_cc 0x0c ; condition codes are irrelevent
|
||||
take_branch_d bnc:d 0xc
|
||||
|
||||
set_cc 0x0b ; condition codes are irrelevent
|
||||
no_branch_d bnc:d 0xb
|
||||
|
||||
set_cc 0x0a ; condition codes are irrelevent
|
||||
take_branch_d bnc:d 0xa
|
||||
|
||||
set_cc 0x09 ; condition codes are irrelevent
|
||||
no_branch_d bnc:d 0x9
|
||||
|
||||
set_cc 0x08 ; condition codes are irrelevent
|
||||
take_branch_d bnc:d 0x8
|
||||
|
||||
set_cc 0x07 ; condition codes are irrelevent
|
||||
no_branch_d bnc:d 0x7
|
||||
|
||||
set_cc 0x06 ; condition codes are irrelevent
|
||||
take_branch_d bnc:d 0x6
|
||||
|
||||
set_cc 0x05 ; condition codes are irrelevent
|
||||
no_branch_d bnc:d 0x5
|
||||
|
||||
set_cc 0x04 ; condition codes are irrelevent
|
||||
take_branch_d bnc:d 0x4
|
||||
|
||||
set_cc 0x03 ; condition codes are irrelevent
|
||||
no_branch_d bnc:d 0x3
|
||||
|
||||
set_cc 0x02 ; condition codes are irrelevent
|
||||
take_branch_d bnc:d 0x2
|
||||
|
||||
set_cc 0x01 ; condition codes are irrelevent
|
||||
no_branch_d bnc:d 0x1
|
||||
|
||||
set_cc 0x00 ; condition codes are irrelevent
|
||||
take_branch_d bnc:d 0x0
|
||||
|
||||
pass
|
||||
109
sim/testsuite/sim/fr30/bne.cgs
Normal file
109
sim/testsuite/sim/fr30/bne.cgs
Normal file
@ -0,0 +1,109 @@
|
||||
# fr30 testcase for bne $label9
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global bne
|
||||
bne:
|
||||
; Test bne $label9
|
||||
set_cc 0x0f ; condition codes are irrelevent
|
||||
no_branch bne
|
||||
|
||||
set_cc 0x0e ; condition codes are irrelevent
|
||||
no_branch bne
|
||||
|
||||
set_cc 0x0d ; condition codes are irrelevent
|
||||
no_branch bne
|
||||
|
||||
set_cc 0x0c ; condition codes are irrelevent
|
||||
no_branch bne
|
||||
|
||||
set_cc 0x0b ; condition codes are irrelevent
|
||||
take_branch bne
|
||||
|
||||
set_cc 0x0a ; condition codes are irrelevent
|
||||
take_branch bne
|
||||
|
||||
set_cc 0x09 ; condition codes are irrelevent
|
||||
take_branch bne
|
||||
|
||||
set_cc 0x08 ; condition codes are irrelevent
|
||||
take_branch bne
|
||||
|
||||
set_cc 0x07 ; condition codes are irrelevent
|
||||
no_branch bne
|
||||
|
||||
set_cc 0x06 ; condition codes are irrelevent
|
||||
no_branch bne
|
||||
|
||||
set_cc 0x05 ; condition codes are irrelevent
|
||||
no_branch bne
|
||||
|
||||
set_cc 0x04 ; condition codes are irrelevent
|
||||
no_branch bne
|
||||
|
||||
set_cc 0x03 ; condition codes are irrelevent
|
||||
take_branch bne
|
||||
|
||||
set_cc 0x02 ; condition codes are irrelevent
|
||||
take_branch bne
|
||||
|
||||
set_cc 0x01 ; condition codes are irrelevent
|
||||
take_branch bne
|
||||
|
||||
set_cc 0x00 ; condition codes are irrelevent
|
||||
take_branch bne
|
||||
|
||||
; Test bne:d label9
|
||||
set_cc 0x0f ; condition codes are irrelevent
|
||||
no_branch_d bne:d 0xf
|
||||
|
||||
set_cc 0x0e ; condition codes are irrelevent
|
||||
no_branch_d bne:d 0xe
|
||||
|
||||
set_cc 0x0d ; condition codes are irrelevent
|
||||
no_branch_d bne:d 0xd
|
||||
|
||||
set_cc 0x0c ; condition codes are irrelevent
|
||||
no_branch_d bne:d 0xc
|
||||
|
||||
set_cc 0x0b ; condition codes are irrelevent
|
||||
take_branch_d bne:d 0xb
|
||||
|
||||
set_cc 0x0a ; condition codes are irrelevent
|
||||
take_branch_d bne:d 0xa
|
||||
|
||||
set_cc 0x09 ; condition codes are irrelevent
|
||||
take_branch_d bne:d 0x9
|
||||
|
||||
set_cc 0x08 ; condition codes are irrelevent
|
||||
take_branch_d bne:d 0x8
|
||||
|
||||
set_cc 0x07 ; condition codes are irrelevent
|
||||
no_branch_d bne:d 0x7
|
||||
|
||||
set_cc 0x06 ; condition codes are irrelevent
|
||||
no_branch_d bne:d 0x6
|
||||
|
||||
set_cc 0x05 ; condition codes are irrelevent
|
||||
no_branch_d bne:d 0x5
|
||||
|
||||
set_cc 0x04 ; condition codes are irrelevent
|
||||
no_branch_d bne:d 0x4
|
||||
|
||||
set_cc 0x03 ; condition codes are irrelevent
|
||||
take_branch_d bne:d 0x3
|
||||
|
||||
set_cc 0x02 ; condition codes are irrelevent
|
||||
take_branch_d bne:d 0x2
|
||||
|
||||
set_cc 0x01 ; condition codes are irrelevent
|
||||
take_branch_d bne:d 0x1
|
||||
|
||||
set_cc 0x00 ; condition codes are irrelevent
|
||||
take_branch_d bne:d 0x0
|
||||
|
||||
pass
|
||||
109
sim/testsuite/sim/fr30/bno.cgs
Normal file
109
sim/testsuite/sim/fr30/bno.cgs
Normal file
@ -0,0 +1,109 @@
|
||||
# fr30 testcase for bno $label9
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global bno
|
||||
bno:
|
||||
; Test bno $label9
|
||||
set_cc 0x0f ; condition codes are irrelevent
|
||||
no_branch bno
|
||||
|
||||
set_cc 0x0e ; condition codes are irrelevent
|
||||
no_branch bno
|
||||
|
||||
set_cc 0x0d ; condition codes are irrelevent
|
||||
no_branch bno
|
||||
|
||||
set_cc 0x0c ; condition codes are irrelevent
|
||||
no_branch bno
|
||||
|
||||
set_cc 0x0b ; condition codes are irrelevent
|
||||
no_branch bno
|
||||
|
||||
set_cc 0x0a ; condition codes are irrelevent
|
||||
no_branch bno
|
||||
|
||||
set_cc 0x09 ; condition codes are irrelevent
|
||||
no_branch bno
|
||||
|
||||
set_cc 0x08 ; condition codes are irrelevent
|
||||
no_branch bno
|
||||
|
||||
set_cc 0x07 ; condition codes are irrelevent
|
||||
no_branch bno
|
||||
|
||||
set_cc 0x06 ; condition codes are irrelevent
|
||||
no_branch bno
|
||||
|
||||
set_cc 0x05 ; condition codes are irrelevent
|
||||
no_branch bno
|
||||
|
||||
set_cc 0x04 ; condition codes are irrelevent
|
||||
no_branch bno
|
||||
|
||||
set_cc 0x03 ; condition codes are irrelevent
|
||||
no_branch bno
|
||||
|
||||
set_cc 0x02 ; condition codes are irrelevent
|
||||
no_branch bno
|
||||
|
||||
set_cc 0x01 ; condition codes are irrelevent
|
||||
no_branch bno
|
||||
|
||||
set_cc 0x00 ; condition codes are irrelevent
|
||||
no_branch bno
|
||||
|
||||
; Test bno:d label9
|
||||
set_cc 0x0f ; condition codes are irrelevent
|
||||
no_branch_d bno:d 0xf
|
||||
|
||||
set_cc 0x0e ; condition codes are irrelevent
|
||||
no_branch_d bno:d 0xe
|
||||
|
||||
set_cc 0x0d ; condition codes are irrelevent
|
||||
no_branch_d bno:d 0xd
|
||||
|
||||
set_cc 0x0c ; condition codes are irrelevent
|
||||
no_branch_d bno:d 0xc
|
||||
|
||||
set_cc 0x0b ; condition codes are irrelevent
|
||||
no_branch_d bno:d 0xb
|
||||
|
||||
set_cc 0x0a ; condition codes are irrelevent
|
||||
no_branch_d bno:d 0xa
|
||||
|
||||
set_cc 0x09 ; condition codes are irrelevent
|
||||
no_branch_d bno:d 0x9
|
||||
|
||||
set_cc 0x08 ; condition codes are irrelevent
|
||||
no_branch_d bno:d 0x8
|
||||
|
||||
set_cc 0x07 ; condition codes are irrelevent
|
||||
no_branch_d bno:d 0x7
|
||||
|
||||
set_cc 0x06 ; condition codes are irrelevent
|
||||
no_branch_d bno:d 0x6
|
||||
|
||||
set_cc 0x05 ; condition codes are irrelevent
|
||||
no_branch_d bno:d 0x5
|
||||
|
||||
set_cc 0x04 ; condition codes are irrelevent
|
||||
no_branch_d bno:d 0x4
|
||||
|
||||
set_cc 0x03 ; condition codes are irrelevent
|
||||
no_branch_d bno:d 0x3
|
||||
|
||||
set_cc 0x02 ; condition codes are irrelevent
|
||||
no_branch_d bno:d 0x2
|
||||
|
||||
set_cc 0x01 ; condition codes are irrelevent
|
||||
no_branch_d bno:d 0x1
|
||||
|
||||
set_cc 0x00 ; condition codes are irrelevent
|
||||
no_branch_d bno:d 0x0
|
||||
|
||||
pass
|
||||
109
sim/testsuite/sim/fr30/bnv.cgs
Normal file
109
sim/testsuite/sim/fr30/bnv.cgs
Normal file
@ -0,0 +1,109 @@
|
||||
# fr30 testcase for bnv $label9
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global bnv
|
||||
bnv:
|
||||
; Test bnv $label9
|
||||
set_cc 0x0f ; condition codes are irrelevent
|
||||
no_branch bnv
|
||||
|
||||
set_cc 0x0e ; condition codes are irrelevent
|
||||
no_branch bnv
|
||||
|
||||
set_cc 0x0d ; condition codes are irrelevent
|
||||
take_branch bnv
|
||||
|
||||
set_cc 0x0c ; condition codes are irrelevent
|
||||
take_branch bnv
|
||||
|
||||
set_cc 0x0b ; condition codes are irrelevent
|
||||
no_branch bnv
|
||||
|
||||
set_cc 0x0a ; condition codes are irrelevent
|
||||
no_branch bnv
|
||||
|
||||
set_cc 0x09 ; condition codes are irrelevent
|
||||
take_branch bnv
|
||||
|
||||
set_cc 0x08 ; condition codes are irrelevent
|
||||
take_branch bnv
|
||||
|
||||
set_cc 0x07 ; condition codes are irrelevent
|
||||
no_branch bnv
|
||||
|
||||
set_cc 0x06 ; condition codes are irrelevent
|
||||
no_branch bnv
|
||||
|
||||
set_cc 0x05 ; condition codes are irrelevent
|
||||
take_branch bnv
|
||||
|
||||
set_cc 0x04 ; condition codes are irrelevent
|
||||
take_branch bnv
|
||||
|
||||
set_cc 0x03 ; condition codes are irrelevent
|
||||
no_branch bnv
|
||||
|
||||
set_cc 0x02 ; condition codes are irrelevent
|
||||
no_branch bnv
|
||||
|
||||
set_cc 0x01 ; condition codes are irrelevent
|
||||
take_branch bnv
|
||||
|
||||
set_cc 0x00 ; condition codes are irrelevent
|
||||
take_branch bnv
|
||||
|
||||
; Test bnv:d label9
|
||||
set_cc 0x0f ; condition codes are irrelevent
|
||||
no_branch_d bnv:d 0xf
|
||||
|
||||
set_cc 0x0e ; condition codes are irrelevent
|
||||
no_branch_d bnv:d 0xe
|
||||
|
||||
set_cc 0x0d ; condition codes are irrelevent
|
||||
take_branch_d bnv:d 0xd
|
||||
|
||||
set_cc 0x0c ; condition codes are irrelevent
|
||||
take_branch_d bnv:d 0xc
|
||||
|
||||
set_cc 0x0b ; condition codes are irrelevent
|
||||
no_branch_d bnv:d 0xb
|
||||
|
||||
set_cc 0x0a ; condition codes are irrelevent
|
||||
no_branch_d bnv:d 0xa
|
||||
|
||||
set_cc 0x09 ; condition codes are irrelevent
|
||||
take_branch_d bnv:d 0x9
|
||||
|
||||
set_cc 0x08 ; condition codes are irrelevent
|
||||
take_branch_d bnv:d 0x8
|
||||
|
||||
set_cc 0x07 ; condition codes are irrelevent
|
||||
no_branch_d bnv:d 0x7
|
||||
|
||||
set_cc 0x06 ; condition codes are irrelevent
|
||||
no_branch_d bnv:d 0x6
|
||||
|
||||
set_cc 0x05 ; condition codes are irrelevent
|
||||
take_branch_d bnv:d 0x5
|
||||
|
||||
set_cc 0x04 ; condition codes are irrelevent
|
||||
take_branch_d bnv:d 0x4
|
||||
|
||||
set_cc 0x03 ; condition codes are irrelevent
|
||||
no_branch_d bnv:d 0x3
|
||||
|
||||
set_cc 0x02 ; condition codes are irrelevent
|
||||
no_branch_d bnv:d 0x2
|
||||
|
||||
set_cc 0x01 ; condition codes are irrelevent
|
||||
take_branch_d bnv:d 0x1
|
||||
|
||||
set_cc 0x00 ; condition codes are irrelevent
|
||||
take_branch_d bnv:d 0x0
|
||||
|
||||
pass
|
||||
109
sim/testsuite/sim/fr30/bp.cgs
Normal file
109
sim/testsuite/sim/fr30/bp.cgs
Normal file
@ -0,0 +1,109 @@
|
||||
# fr30 testcase for bp $label9
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global bp
|
||||
bp:
|
||||
; Test bp $label9
|
||||
set_cc 0x0f ; condition codes are irrelevent
|
||||
no_branch bp
|
||||
|
||||
set_cc 0x0e ; condition codes are irrelevent
|
||||
no_branch bp
|
||||
|
||||
set_cc 0x0d ; condition codes are irrelevent
|
||||
no_branch bp
|
||||
|
||||
set_cc 0x0c ; condition codes are irrelevent
|
||||
no_branch bp
|
||||
|
||||
set_cc 0x0b ; condition codes are irrelevent
|
||||
no_branch bp
|
||||
|
||||
set_cc 0x0a ; condition codes are irrelevent
|
||||
no_branch bp
|
||||
|
||||
set_cc 0x09 ; condition codes are irrelevent
|
||||
no_branch bp
|
||||
|
||||
set_cc 0x08 ; condition codes are irrelevent
|
||||
no_branch bp
|
||||
|
||||
set_cc 0x07 ; condition codes are irrelevent
|
||||
take_branch bp
|
||||
|
||||
set_cc 0x06 ; condition codes are irrelevent
|
||||
take_branch bp
|
||||
|
||||
set_cc 0x05 ; condition codes are irrelevent
|
||||
take_branch bp
|
||||
|
||||
set_cc 0x04 ; condition codes are irrelevent
|
||||
take_branch bp
|
||||
|
||||
set_cc 0x03 ; condition codes are irrelevent
|
||||
take_branch bp
|
||||
|
||||
set_cc 0x02 ; condition codes are irrelevent
|
||||
take_branch bp
|
||||
|
||||
set_cc 0x01 ; condition codes are irrelevent
|
||||
take_branch bp
|
||||
|
||||
set_cc 0x00 ; condition codes are irrelevent
|
||||
take_branch bp
|
||||
|
||||
; Test bp:d label9
|
||||
set_cc 0x0f ; condition codes are irrelevent
|
||||
no_branch_d bp:d 0xf
|
||||
|
||||
set_cc 0x0e ; condition codes are irrelevent
|
||||
no_branch_d bp:d 0xe
|
||||
|
||||
set_cc 0x0d ; condition codes are irrelevent
|
||||
no_branch_d bp:d 0xd
|
||||
|
||||
set_cc 0x0c ; condition codes are irrelevent
|
||||
no_branch_d bp:d 0xc
|
||||
|
||||
set_cc 0x0b ; condition codes are irrelevent
|
||||
no_branch_d bp:d 0xb
|
||||
|
||||
set_cc 0x0a ; condition codes are irrelevent
|
||||
no_branch_d bp:d 0xa
|
||||
|
||||
set_cc 0x09 ; condition codes are irrelevent
|
||||
no_branch_d bp:d 0x9
|
||||
|
||||
set_cc 0x08 ; condition codes are irrelevent
|
||||
no_branch_d bp:d 0x8
|
||||
|
||||
set_cc 0x07 ; condition codes are irrelevent
|
||||
take_branch_d bp:d 0x7
|
||||
|
||||
set_cc 0x06 ; condition codes are irrelevent
|
||||
take_branch_d bp:d 0x6
|
||||
|
||||
set_cc 0x05 ; condition codes are irrelevent
|
||||
take_branch_d bp:d 0x5
|
||||
|
||||
set_cc 0x04 ; condition codes are irrelevent
|
||||
take_branch_d bp:d 0x4
|
||||
|
||||
set_cc 0x03 ; condition codes are irrelevent
|
||||
take_branch_d bp:d 0x3
|
||||
|
||||
set_cc 0x02 ; condition codes are irrelevent
|
||||
take_branch_d bp:d 0x2
|
||||
|
||||
set_cc 0x01 ; condition codes are irrelevent
|
||||
take_branch_d bp:d 0x1
|
||||
|
||||
set_cc 0x00 ; condition codes are irrelevent
|
||||
take_branch_d bp:d 0x0
|
||||
|
||||
pass
|
||||
109
sim/testsuite/sim/fr30/bra.cgs
Normal file
109
sim/testsuite/sim/fr30/bra.cgs
Normal file
@ -0,0 +1,109 @@
|
||||
# fr30 testcase for bra $label9
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global bra
|
||||
bra:
|
||||
; Test bra $label9
|
||||
set_cc 0x0f ; condition codes are irrelevent
|
||||
take_branch bra
|
||||
|
||||
set_cc 0x0e ; condition codes are irrelevent
|
||||
take_branch bra
|
||||
|
||||
set_cc 0x0d ; condition codes are irrelevent
|
||||
take_branch bra
|
||||
|
||||
set_cc 0x0c ; condition codes are irrelevent
|
||||
take_branch bra
|
||||
|
||||
set_cc 0x0b ; condition codes are irrelevent
|
||||
take_branch bra
|
||||
|
||||
set_cc 0x0a ; condition codes are irrelevent
|
||||
take_branch bra
|
||||
|
||||
set_cc 0x09 ; condition codes are irrelevent
|
||||
take_branch bra
|
||||
|
||||
set_cc 0x08 ; condition codes are irrelevent
|
||||
take_branch bra
|
||||
|
||||
set_cc 0x07 ; condition codes are irrelevent
|
||||
take_branch bra
|
||||
|
||||
set_cc 0x06 ; condition codes are irrelevent
|
||||
take_branch bra
|
||||
|
||||
set_cc 0x05 ; condition codes are irrelevent
|
||||
take_branch bra
|
||||
|
||||
set_cc 0x04 ; condition codes are irrelevent
|
||||
take_branch bra
|
||||
|
||||
set_cc 0x03 ; condition codes are irrelevent
|
||||
take_branch bra
|
||||
|
||||
set_cc 0x02 ; condition codes are irrelevent
|
||||
take_branch bra
|
||||
|
||||
set_cc 0x01 ; condition codes are irrelevent
|
||||
take_branch bra
|
||||
|
||||
set_cc 0x00 ; condition codes are irrelevent
|
||||
take_branch bra
|
||||
|
||||
; Test bra:d label9
|
||||
set_cc 0x0f ; condition codes are irrelevent
|
||||
take_branch_d bra:d 0xf
|
||||
|
||||
set_cc 0x0e ; condition codes are irrelevent
|
||||
take_branch_d bra:d 0xe
|
||||
|
||||
set_cc 0x0d ; condition codes are irrelevent
|
||||
take_branch_d bra:d 0xd
|
||||
|
||||
set_cc 0x0c ; condition codes are irrelevent
|
||||
take_branch_d bra:d 0xc
|
||||
|
||||
set_cc 0x0b ; condition codes are irrelevent
|
||||
take_branch_d bra:d 0xb
|
||||
|
||||
set_cc 0x0a ; condition codes are irrelevent
|
||||
take_branch_d bra:d 0xa
|
||||
|
||||
set_cc 0x09 ; condition codes are irrelevent
|
||||
take_branch_d bra:d 0x9
|
||||
|
||||
set_cc 0x08 ; condition codes are irrelevent
|
||||
take_branch_d bra:d 0x8
|
||||
|
||||
set_cc 0x07 ; condition codes are irrelevent
|
||||
take_branch_d bra:d 0x7
|
||||
|
||||
set_cc 0x06 ; condition codes are irrelevent
|
||||
take_branch_d bra:d 0x6
|
||||
|
||||
set_cc 0x05 ; condition codes are irrelevent
|
||||
take_branch_d bra:d 0x5
|
||||
|
||||
set_cc 0x04 ; condition codes are irrelevent
|
||||
take_branch_d bra:d 0x4
|
||||
|
||||
set_cc 0x03 ; condition codes are irrelevent
|
||||
take_branch_d bra:d 0x3
|
||||
|
||||
set_cc 0x02 ; condition codes are irrelevent
|
||||
take_branch_d bra:d 0x2
|
||||
|
||||
set_cc 0x01 ; condition codes are irrelevent
|
||||
take_branch_d bra:d 0x1
|
||||
|
||||
set_cc 0x00 ; condition codes are irrelevent
|
||||
take_branch_d bra:d 0x0
|
||||
|
||||
pass
|
||||
109
sim/testsuite/sim/fr30/bv.cgs
Normal file
109
sim/testsuite/sim/fr30/bv.cgs
Normal file
@ -0,0 +1,109 @@
|
||||
# fr30 testcase for bv $label9
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global bv
|
||||
bv:
|
||||
; Test bv $label9
|
||||
set_cc 0x0f ; condition codes are irrelevent
|
||||
take_branch bv
|
||||
|
||||
set_cc 0x0e ; condition codes are irrelevent
|
||||
take_branch bv
|
||||
|
||||
set_cc 0x0d ; condition codes are irrelevent
|
||||
no_branch bv
|
||||
|
||||
set_cc 0x0c ; condition codes are irrelevent
|
||||
no_branch bv
|
||||
|
||||
set_cc 0x0b ; condition codes are irrelevent
|
||||
take_branch bv
|
||||
|
||||
set_cc 0x0a ; condition codes are irrelevent
|
||||
take_branch bv
|
||||
|
||||
set_cc 0x09 ; condition codes are irrelevent
|
||||
no_branch bv
|
||||
|
||||
set_cc 0x08 ; condition codes are irrelevent
|
||||
no_branch bv
|
||||
|
||||
set_cc 0x07 ; condition codes are irrelevent
|
||||
take_branch bv
|
||||
|
||||
set_cc 0x06 ; condition codes are irrelevent
|
||||
take_branch bv
|
||||
|
||||
set_cc 0x05 ; condition codes are irrelevent
|
||||
no_branch bv
|
||||
|
||||
set_cc 0x04 ; condition codes are irrelevent
|
||||
no_branch bv
|
||||
|
||||
set_cc 0x03 ; condition codes are irrelevent
|
||||
take_branch bv
|
||||
|
||||
set_cc 0x02 ; condition codes are irrelevent
|
||||
take_branch bv
|
||||
|
||||
set_cc 0x01 ; condition codes are irrelevent
|
||||
no_branch bv
|
||||
|
||||
set_cc 0x00 ; condition codes are irrelevent
|
||||
no_branch bv
|
||||
|
||||
; Test bv:d label9
|
||||
set_cc 0x0f ; condition codes are irrelevent
|
||||
take_branch_d bv:d 0xf
|
||||
|
||||
set_cc 0x0e ; condition codes are irrelevent
|
||||
take_branch_d bv:d 0xe
|
||||
|
||||
set_cc 0x0d ; condition codes are irrelevent
|
||||
no_branch_d bv:d 0xd
|
||||
|
||||
set_cc 0x0c ; condition codes are irrelevent
|
||||
no_branch_d bv:d 0xc
|
||||
|
||||
set_cc 0x0b ; condition codes are irrelevent
|
||||
take_branch_d bv:d 0xb
|
||||
|
||||
set_cc 0x0a ; condition codes are irrelevent
|
||||
take_branch_d bv:d 0xa
|
||||
|
||||
set_cc 0x09 ; condition codes are irrelevent
|
||||
no_branch_d bv:d 0x9
|
||||
|
||||
set_cc 0x08 ; condition codes are irrelevent
|
||||
no_branch_d bv:d 0x8
|
||||
|
||||
set_cc 0x07 ; condition codes are irrelevent
|
||||
take_branch_d bv:d 0x7
|
||||
|
||||
set_cc 0x06 ; condition codes are irrelevent
|
||||
take_branch_d bv:d 0x6
|
||||
|
||||
set_cc 0x05 ; condition codes are irrelevent
|
||||
no_branch_d bv:d 0x5
|
||||
|
||||
set_cc 0x04 ; condition codes are irrelevent
|
||||
no_branch_d bv:d 0x4
|
||||
|
||||
set_cc 0x03 ; condition codes are irrelevent
|
||||
take_branch_d bv:d 0x3
|
||||
|
||||
set_cc 0x02 ; condition codes are irrelevent
|
||||
take_branch_d bv:d 0x2
|
||||
|
||||
set_cc 0x01 ; condition codes are irrelevent
|
||||
no_branch_d bv:d 0x1
|
||||
|
||||
set_cc 0x00 ; condition codes are irrelevent
|
||||
no_branch_d bv:d 0x0
|
||||
|
||||
pass
|
||||
36
sim/testsuite/sim/fr30/inte.cgs
Normal file
36
sim/testsuite/sim/fr30/inte.cgs
Normal file
@ -0,0 +1,36 @@
|
||||
# fr30 testcase for inte
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global inte
|
||||
inte:
|
||||
; Test inte which is essentially int #9
|
||||
mvr_h_gr tbr,r7
|
||||
inci_h_gr 0x3d8,r7
|
||||
mvi_h_mem pass,r7
|
||||
mvi_h_gr doint,r9
|
||||
inci_h_gr 2,r9
|
||||
mvr_h_gr ssp,r10
|
||||
set_cc 0x0f ; Condition codes should not change
|
||||
set_s_user ; Set opposite of expected
|
||||
set_i 1 ; Should not change
|
||||
mvr_h_gr ps,r8
|
||||
doint: inte
|
||||
fail
|
||||
|
||||
pass:
|
||||
test_cc 1 1 1 1
|
||||
test_ilm 4
|
||||
test_s_system
|
||||
test_i 1
|
||||
inci_h_gr -4,r10
|
||||
testr_h_mem r8,r10
|
||||
inci_h_gr -4,r10
|
||||
testr_h_mem r9,r10
|
||||
testr_h_dr r10,ssp
|
||||
|
||||
pass
|
||||
57
sim/testsuite/sim/fr30/reti.cgs
Normal file
57
sim/testsuite/sim/fr30/reti.cgs
Normal file
@ -0,0 +1,57 @@
|
||||
# fr30 testcase for reti
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global reti
|
||||
reti:
|
||||
; Test reti with low reset of ilm allowed
|
||||
mvr_h_gr sp,r8 ; Save stack pointer
|
||||
set_s_system
|
||||
set_i 1
|
||||
set_ilm 15 ; attempt reset of low range
|
||||
set_cc 0x0f ; Condition codes should not change
|
||||
save_ps
|
||||
inci_h_gr -4,sp
|
||||
mvi_h_mem ret1,sp
|
||||
set_i 0 ; Set opposite of expected
|
||||
set_ilm 0 ; attempt reset of low range
|
||||
set_cc 0x00 ; Set opposite of expected
|
||||
|
||||
reti
|
||||
fail
|
||||
|
||||
ret1:
|
||||
test_cc 1 1 1 1
|
||||
test_s_system
|
||||
test_i 1
|
||||
test_ilm 15
|
||||
testr_h_gr r8,sp
|
||||
|
||||
; Test reti with low reset of ilm not allowed
|
||||
mvr_h_gr sp,r8 ; Save stack pointer
|
||||
set_s_system
|
||||
set_i 0
|
||||
set_ilm 15 ; attempt reset of low range
|
||||
set_cc 0x0f ; Condition codes should not change
|
||||
save_ps
|
||||
inci_h_gr -4,sp
|
||||
mvi_h_mem ret2,sp
|
||||
set_i 0 ; Set opposite of expected
|
||||
set_ilm 16 ; disallow reset of low range
|
||||
set_cc 0x00 ; Set opposite of expected
|
||||
|
||||
reti
|
||||
fail
|
||||
|
||||
ret2:
|
||||
test_cc 1 1 1 1
|
||||
test_s_system
|
||||
test_i 0
|
||||
test_ilm 31
|
||||
testr_h_gr r8,sp
|
||||
|
||||
pass
|
||||
Loading…
Reference in New Issue
Block a user