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Power: Correct little-endian e500v2 GPR frame offsets

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This change corrects GPR frame offset calculation for the e500v2
processor.  On this target, featuring the SPE APU, GPRs are 64-bit and
are held in stack frames whole with the use of `evstdd' and `evldd'
instructions.  Their integer 32-bit part occupies the low-order word and
therefore its offset varies between the two endiannesses possible.

	* rs6000-tdep.c (rs6000_frame_cache): Correct little-endian GPR
	offset into SPE pseudo registers.
This commit is contained in:
Maciej W. Rozycki 2014-03-18 19:39:41 +00:00
parent 0c7e1a4602
commit dea80df099
2 changed files with 9 additions and 2 deletions
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5
gdb/ChangeLog
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@ -1,3 +1,8 @@
2014-03-18 Maciej W. Rozycki <macro@codesourcery.com>
* rs6000-tdep.c (rs6000_frame_cache): Correct little-endian GPR
offset into SPE pseudo registers.
2014-03-18 Pedro Alves <palves@redhat.com>
PR gdb/13860

4
gdb/rs6000-tdep.c
View File

@ -3257,10 +3257,12 @@ rs6000_frame_cache (struct frame_info *this_frame, void **this_cache)
{
int i;
CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
CORE_ADDR off = (byte_order == BFD_ENDIAN_BIG ? 4 : 0);
for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
{
cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + off;
ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
}
}