OpenE2K/binutils-gdb
12
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

* config/tc-m68k.c (mcf52235_ctrl): Add cache registers.

Browse Source 
(mcf5253_ctrl): Add RAMBAR, MBAR, MBAR2.
	(mcf5407_ctrl): New.
	(m68k_cpus): Adjust 5407 entry.
This commit is contained in:
Kazu Hirata 2007-08-28 13:43:06 +00:00
parent f75192f2d0
commit def8fc92cd
2 changed files with 19 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
gas/ChangeLog
View File

@ -1,3 +1,10 @@
2007-08-28 Nathan Sidwell <nathan@codesourcery.com>
* config/tc-m68k.c (mcf52235_ctrl): Add cache registers.
(mcf5253_ctrl): Add RAMBAR, MBAR, MBAR2.
(mcf5407_ctrl): New.
(m68k_cpus): Adjust 5407 entry.
2007-08-28 Maxim Kuvyrkov <maxim@codesourcery.com>
* config/tc-m68k.c (mcf51qe_ctrl): Define 51QE control registers.

15
gas/config/tc-m68k.c
View File

@ -205,7 +205,7 @@ static const enum m68k_register mcf52223_ctrl[] = {
0
};
static const enum m68k_register mcf52235_ctrl[] = {
VBR, FLASHBAR, RAMBAR, RAMBAR1,
VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
0
};
static const enum m68k_register mcf5225_ctrl[] = {
@ -225,7 +225,7 @@ static const enum m68k_register mcf5250_ctrl[] = {
0
};
static const enum m68k_register mcf5253_ctrl[] = {
VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, MBAR,
VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
0
};
static const enum m68k_register mcf5271_ctrl[] = {
@ -272,6 +272,15 @@ static const enum m68k_register mcfv4e_ctrl[] = {
ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
0
};
static const enum m68k_register mcf5407_ctrl[] = {
CACR, ASID, ACR0, ACR1, ACR2, ACR3,
VBR, PC, RAMBAR0, RAMBAR1, MBAR,
/* Legacy names */
TC /* ASID */,
ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
0
};
static const enum m68k_register mcf54455_ctrl[] = {
CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
VBR, PC, RAMBAR1, MBAR,
@ -632,7 +641,7 @@ static const struct m68k_cpu m68k_cpus[] =
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
{mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
{mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf_ctrl, "5407",0},
{mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0},
{mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1},
{mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1},