Fix some PowerPC VLE BFD issues and add some PowerPC VLE instructions.
bfd/
* elf32-ppc.c (is_branch_reloc): Recognise VLE branch relocations.
(ppc_elf_howto_raw): Fix dst_mask of R_PPC_VLE_REL15.
(ppc_elf_vle_split16): Clear field before inserting.
opcodes/
* ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
'e_cmplwi' to 'e_cmpli' instead.
(OPVUPRT, OPVUPRT_MASK): Define.
(powerpc_opcodes): Add E200Z4 insns.
(vle_opcodes): Add context save/restore insns.
include/
* opcode/ppc.h (PPC_OPCODE_E200Z4): New define.
This commit is contained in:
Andrew Jenner
parent
751b375e01
commit
dfdaec14b0
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@ -1,3 +1,10 @@
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2016-08-01 Andrew Jenner <andrew@codesourcery.com>
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Kwok Cheung Yeung <kcy@codesourcery.com>
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* elf32-ppc.c (is_branch_reloc): Recognise VLE branch relocations.
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(ppc_elf_howto_raw): Fix dst_mask of R_PPC_VLE_REL15.
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(ppc_elf_vle_split16): Clear field before inserting.
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2016-08-01 Nick Clifton <nickc@redhat.com>
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* po/sv.po: Updated Swedish translation.
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@ -1425,7 +1425,7 @@ static reloc_howto_type ppc_elf_howto_raw[] = {
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"R_PPC_VLE_REL15", /* name */
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FALSE, /* partial_inplace */
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0, /* src_mask */
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0xfe, /* dst_mask */
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0xfffe, /* dst_mask */
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TRUE), /* pcrel_offset */
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/* A relative 24 bit branch. */
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@ -3948,7 +3948,8 @@ is_branch_reloc (enum elf_ppc_reloc_type r_type)
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|| r_type == R_PPC_ADDR24
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|| r_type == R_PPC_ADDR14
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|| r_type == R_PPC_ADDR14_BRTAKEN
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|| r_type == R_PPC_ADDR14_BRNTAKEN);
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|| r_type == R_PPC_ADDR14_BRNTAKEN
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|| r_type == R_PPC_VLE_REL24);
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}
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static void
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@ -4899,6 +4900,7 @@ ppc_elf_vle_split16 (bfd *output_bfd, bfd_byte *loc,
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insn = bfd_get_32 (output_bfd, loc);
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top5 = value & 0xf800;
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top5 = top5 << (split16_format == split16a_type ? 9 : 5);
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insn &= (split16_format == split16a_type ? ~0x1f007ff : ~0x1f07ff);
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insn |= top5;
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insn |= value & 0x7ff;
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bfd_put_32 (output_bfd, insn, loc);
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@ -1,3 +1,7 @@
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2016-08-01 Andrew Jenner <andrew@codesourcery.com>
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* opcode/ppc.h (PPC_OPCODE_E200Z4): New define.
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2016-07-27 Graham Markall <graham.markall@embecosm.com>
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* opcode/arc.h: Add ARC_OPERAND_ADDRTYPE,
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@ -214,6 +214,9 @@ extern const int vle_num_opcodes;
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/* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08. */
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#define PPC_OPCODE_VSX3 0x40000000000ull
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/* Opcode is supported by e200z4. */
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#define PPC_OPCODE_E200Z4 0x80000000000ull
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/* A macro to extract the major opcode from an instruction. */
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#define PPC_OP(i) (((i) >> 26) & 0x3f)
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@ -1,3 +1,13 @@
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2016-07-25 Andrew Jenner <andrew@codesourcery.com>
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Kwok Cheung Yeung <kcy@codesourcery.com>
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opcodes/
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* ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
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'e_cmplwi' to 'e_cmpli' instead.
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(OPVUPRT, OPVUPRT_MASK): Define.
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(powerpc_opcodes): Add E200Z4 insns.
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(vle_opcodes): Add context save/restore insns.
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2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
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* micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
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@ -105,6 +105,11 @@ struct ppc_mopt ppc_opts[] = {
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0 },
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{ "com", PPC_OPCODE_COMMON,
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0 },
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{ "e200z4", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
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| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
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| PPC_OPCODE_E500 | PPC_OPCODE_E200Z4),
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PPC_OPCODE_VLE },
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{ "e300", PPC_OPCODE_PPC | PPC_OPCODE_E300,
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0 },
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{ "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
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@ -2374,6 +2374,12 @@ extract_vleil (unsigned long insn,
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#define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8))
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#define OPVUP_MASK OPVUP (0x3f, 0xff)
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/* The main opcode combined with an update code and the RT fields specified in
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D form instruction. Used for VLE volatile context save/restore
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instructions. */
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#define OPVUPRT(x,vup,rt) (OPVUP (x, vup) | ((((unsigned long)(rt)) & 0x1f) << 21))
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#define OPVUPRT_MASK OPVUPRT (0x3f, 0xff, 0x1f)
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/* An A form instruction. */
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#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
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#define A_MASK A (0x3f, 0x1f, 1)
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@ -3055,6 +3061,7 @@ extract_vleil (unsigned long insn,
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#define E6500 PPC_OPCODE_E6500
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#define PPCVLE PPC_OPCODE_VLE
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#define PPCHTM PPC_OPCODE_HTM
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#define E200Z4 PPC_OPCODE_E200Z4
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/* The list of embedded processors that use the embedded operand ordering
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for the 3 operand dcbt and dcbtst instructions. */
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#define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
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@ -5815,6 +5822,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}},
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{"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}},
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{"lbdx", X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}},
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{"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}},
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@ -5865,6 +5873,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}},
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{"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}},
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{"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}},
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{"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}},
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{"lvtrx", X(31,549), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
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@ -5888,6 +5897,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}},
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{"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}},
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{"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}},
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{"lvtlx", X(31,581), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
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@ -5938,6 +5948,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
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{"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}},
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{"stbdx", X(31,643), X_MASK, E500MC, 0, {RS, RA, RB}},
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{"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},
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@ -5975,6 +5986,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}},
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{"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},
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{"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}},
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{"sthdx", X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}},
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{"stvfrx", X(31,677), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
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@ -5992,6 +6004,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}},
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{"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}},
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{"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}},
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{"stwdx", X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}},
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{"stvflx", X(31,709), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
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@ -7070,7 +7083,9 @@ const struct powerpc_opcode vle_opcodes[] = {
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{"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
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{"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
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{"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
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{"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
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{"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
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{"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
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{"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
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{"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
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@ -7097,6 +7112,16 @@ const struct powerpc_opcode vle_opcodes[] = {
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{"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
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{"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
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{"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
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{"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
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{"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
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{"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
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{"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
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{"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
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{"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
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{"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
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{"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
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{"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
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{"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
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{"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}},
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{"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
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{"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}},
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@ -7144,10 +7169,8 @@ const struct powerpc_opcode vle_opcodes[] = {
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{"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
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{"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
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{"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
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{"e_cmplwi", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
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{"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
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{"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
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{"e_cmpwi", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
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{"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
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{"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
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{"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
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