gas/testsuite/
2008-01-02 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/arch-5.d: New file. * gas/i386/arch-5.s: Likewise. * gas/i386/arch-6.d: Likewise. * gas/i386/arch-6.s: Likewise. * gas/i386/arch-7.d: Likewise. * gas/i386/arch-7.s: Likewise. * gas/i386/arch-8.d: Likewise. * gas/i386/arch-8.s: Likewise. * gas/i386/i386.exp: Run arch-5, arch-6, arch-7 and arch-8. opcodes/ 2008-01-02 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and CPU_SSE5_FLAGS. (cpu_flags): Add CpuSSE4_2_Or_ABM. * i386-opc.h (CpuSSE4_2_Or_ABM): New. (CpuLM): Updated. (i386_cpu_flags): Add cpusse4_2_or_abm. * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of CpuABM|CpuSSE4_2 on popcnt. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
This commit is contained in:
H.J. Lu
parent
18a2244ddd
commit
e0329a2266
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@ -1,3 +1,16 @@
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2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/arch-5.d: New file.
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* gas/i386/arch-5.s: Likewise.
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* gas/i386/arch-6.d: Likewise.
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* gas/i386/arch-6.s: Likewise.
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* gas/i386/arch-7.d: Likewise.
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* gas/i386/arch-7.s: Likewise.
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* gas/i386/arch-8.d: Likewise.
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* gas/i386/arch-8.s: Likewise.
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* gas/i386/i386.exp: Run arch-5, arch-6, arch-7 and arch-8.
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2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/i386.s: Add tests for movq.
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@ -0,0 +1,11 @@
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#objdump: -dw
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#name: i386 arch 5
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.*: file format .*
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Disassembly of section .text:
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0+ <.text>:
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[ ]*[a-f0-9]+: f3 0f b8 d9 popcnt %ecx,%ebx
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[ ]*[a-f0-9]+: f2 0f 38 f1 d9 crc32l %ecx,%ebx
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#pass
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@ -0,0 +1,5 @@
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# Test .arch .sse4.2
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.arch generic32
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.arch .sse4.2
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popcnt %ecx,%ebx
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crc32 %ecx,%ebx
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@ -0,0 +1,11 @@
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#objdump: -dw
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#name: i386 arch 6
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.*: file format .*
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Disassembly of section .text:
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0+ <.text>:
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[ ]*[a-f0-9]+: f3 0f b8 d9 popcnt %ecx,%ebx
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[ ]*[a-f0-9]+: f2 0f 38 f1 d9 crc32l %ecx,%ebx
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#pass
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@ -0,0 +1,5 @@
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# Test .arch .sse4
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.arch generic32
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.arch .sse4
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popcnt %ecx,%ebx
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crc32 %ecx,%ebx
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@ -0,0 +1,11 @@
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#objdump: -dw
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#name: i386 arch 7
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.*: file format .*
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Disassembly of section .text:
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0+ <.text>:
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[ ]*[a-f0-9]+: f3 0f b8 d9 popcnt %ecx,%ebx
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[ ]*[a-f0-9]+: f3 0f bd d9 lzcnt %ecx,%ebx
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#pass
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@ -0,0 +1,5 @@
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# Test .arch .abm
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.arch generic32
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.arch .abm
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popcnt %ecx,%ebx
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lzcnt %ecx,%ebx
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@ -0,0 +1,11 @@
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#objdump: -dw
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#name: i386 arch 8
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.*: file format .*
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Disassembly of section .text:
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0+ <.text>:
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[ ]*[a-f0-9]+: f3 0f b8 d9 popcnt %ecx,%ebx
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[ ]*[a-f0-9]+: 0f 7a 12 ca frczss %xmm2,%xmm1
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#pass
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@ -0,0 +1,5 @@
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# Test .arch .sse5
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.arch generic32
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.arch .sse5
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popcnt %ecx,%ebx
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frczss %xmm2, %xmm1
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@ -102,6 +102,10 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "arch-2"
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run_dump_test "arch-3"
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run_dump_test "arch-4"
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run_dump_test "arch-5"
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run_dump_test "arch-6"
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run_dump_test "arch-7"
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run_dump_test "arch-8"
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# These tests require support for 8 and 16 bit relocs,
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# so we only run them for ELF and COFF targets.
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@ -1,3 +1,19 @@
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2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
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* i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
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CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
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CPU_SSE5_FLAGS.
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(cpu_flags): Add CpuSSE4_2_Or_ABM.
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* i386-opc.h (CpuSSE4_2_Or_ABM): New.
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(CpuLM): Updated.
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(i386_cpu_flags): Add cpusse4_2_or_abm.
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* i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
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CpuABM|CpuSSE4_2 on popcnt.
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* i386-init.h: Regenerated.
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* i386-tbl.h: Likewise.
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2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
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* i386-opc.h: Update comments.
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@ -81,7 +81,7 @@ static initializer cpu_flag_init [] =
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{ "CPU_K8_FLAGS",
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"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuK8|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuLM" },
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{ "CPU_AMDFAM10_FLAGS",
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"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuK8|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuLM" },
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"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuK8|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuSSE4_2_Or_ABM|CpuLM" },
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{ "CPU_MMX_FLAGS",
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"CpuMMX" },
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{ "CPU_SSE_FLAGS",
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@ -95,7 +95,7 @@ static initializer cpu_flag_init [] =
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{ "CPU_SSE4_1_FLAGS",
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"CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_1_Or_5" },
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{ "CPU_SSE4_2_FLAGS",
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"CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4_1_Or_5" },
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"CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4_1_Or_5|CpuSSE4_2_Or_ABM" },
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{ "CPU_3DNOW_FLAGS",
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"CpuMMX|Cpu3dnow" },
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{ "CPU_3DNOWA_FLAGS",
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@ -107,9 +107,9 @@ static initializer cpu_flag_init [] =
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{ "CPU_SSE4A_FLAGS",
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"CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a" },
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{ "CPU_ABM_FLAGS",
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"CpuABM" },
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"CpuABM|CpuSSE4_2_Or_ABM" },
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{ "CPU_SSE5_FLAGS",
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"CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuSSE5|CpuSSE4_1_Or_5"},
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"CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuSSE5|CpuSSE4_1_Or_5|CpuSSE4_2_Or_ABM"},
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};
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static initializer operand_type_init [] =
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@ -235,6 +235,7 @@ static bitfield cpu_flags[] =
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BITFIELD (CpuSSE4a),
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BITFIELD (CpuSSE5),
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BITFIELD (CpuSSE4_1_Or_5),
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BITFIELD (CpuSSE4_2_Or_ABM),
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BITFIELD (Cpu3dnow),
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BITFIELD (Cpu3dnowA),
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BITFIELD (CpuPadLock),
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@ -20,143 +20,143 @@
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#define CPU_UNKNOWN_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
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1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
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#define CPU_GENERIC32_FLAGS \
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{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_GENERIC64_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_NONE_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_I186_FLAGS \
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{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_I286_FLAGS \
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{ { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_I386_FLAGS \
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{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_I486_FLAGS \
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{ { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_I586_FLAGS \
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{ { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_I686_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_P2_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_P3_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_P4_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_NOCONA_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
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#define CPU_CORE_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_CORE2_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, \
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1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
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1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
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#define CPU_K6_FLAGS \
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{ { 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_K6_2_FLAGS \
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{ { 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_ATHLON_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_K8_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
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#define CPU_AMDFAM10_FLAGS \
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{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
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0, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0 } }
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0, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0 } }
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#define CPU_MMX_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_SSE_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_SSE2_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_SSE3_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_SSSE3_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, \
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1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define CPU_SSE4_1_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, \
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1, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0 } }
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1, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0 } }
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#define CPU_SSE4_2_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, \
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1, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0 } }
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1, 0, 0, 1, 1, 0, 1, 1, 0, 0, 0, 0 } }
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#define CPU_3DNOW_FLAGS \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_3DNOWA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_PADLOCK_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SVME_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4A_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ABM_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE5_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 1, 1, 0, 0, 1, 1, 0, 0, 0, 0 } }
|
||||
0, 1, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0 } }
|
||||
|
||||
|
||||
#define OPERAND_TYPE_NONE \
|
||||
|
|
|
|||
|
|
@ -84,8 +84,10 @@
|
|||
#define CpuSSE5 (CpuSSE4_2 + 1)
|
||||
/* SSE4.1 or SSE5 support required */
|
||||
#define CpuSSE4_1_Or_5 (CpuSSE5 + 1)
|
||||
/* SSE4.2 or ABM support required */
|
||||
#define CpuSSE4_2_Or_ABM (CpuSSE4_1_Or_5 + 1)
|
||||
/* 64bit support available, used by -march= in assembler. */
|
||||
#define CpuLM (CpuSSE4_1_Or_5 + 1)
|
||||
#define CpuLM (CpuSSE4_2_Or_ABM + 1)
|
||||
/* 64bit support required */
|
||||
#define Cpu64 (CpuLM + 1)
|
||||
/* Not supported in the 64bit mode */
|
||||
|
|
@ -135,6 +137,7 @@ typedef union i386_cpu_flags
|
|||
unsigned int cpusse4_2:1;
|
||||
unsigned int cpusse5:1;
|
||||
unsigned int cpusse4_1_or_5:1;
|
||||
unsigned int cpusse4_2_or_abm:1;
|
||||
unsigned int cpulm:1;
|
||||
unsigned int cpu64:1;
|
||||
unsigned int cpuno64:1;
|
||||
|
|
|
|||
|
|
@ -1459,7 +1459,7 @@ insertq, 2, 0xf20f79, None, 2, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSu
|
|||
insertq, 4, 0xf20f78, None, 2, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Imm8, RegXMM, RegXMM }
|
||||
|
||||
// ABM instructions
|
||||
popcnt, 2, 0xf30fb8, None, 2, CpuABM|CpuSSE4_2, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
|
||||
popcnt, 2, 0xf30fb8, None, 2, CpuSSE4_2_Or_ABM, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
|
||||
lzcnt, 2, 0xf30fbd, None, 2, CpuABM, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
|
||||
|
||||
// SSE5 instructions
|
||||
|
|
|
|||
2868
opcodes/i386-tbl.h
2868
opcodes/i386-tbl.h
File diff suppressed because it is too large
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Reference in New Issue