In src/gas/ChangeLog:
2000-08-30 Mark Hatle <mhatle@mvista.com> * config/tc-ppc.c (md_parse_option): Recognize -m405. In src/opcodes/ChangeLog: 2000-08-30 Mark Hatle <mhatle@mvista.com> * ppc-opc.c Add XTLB macro for a few PPC 4xx extended mnemonics. (powerpc_opcodes): Add table entries for PPC 405 instructions. Changed rfci, icbt, mfdcr, dccci, mtdcr, iccci from PPC to PPC403 instructions. Added extended mnemonic mftbl as defined in the 405GP manual for all PPCs.
This commit is contained in:
Geoffrey Keating
parent
cf39a089d6
commit
e0c2164971
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@ -1,3 +1,7 @@
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2000-08-30 Mark Hatle <mhatle@mvista.com>
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* config/tc-ppc.c (md_parse_option): Recognize -m405.
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2000-08-31 Kazu Hirata <kazu@hxi.com>
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* listing.c: Fix formatting.
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@ -842,6 +842,7 @@ md_parse_option (c, arg)
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else if (strcmp (arg, "ppc") == 0
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|| strcmp (arg, "ppc32") == 0
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|| strcmp (arg, "403") == 0
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|| strcmp (arg, "405") == 0
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|| strcmp (arg, "603") == 0
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|| strcmp (arg, "604") == 0)
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ppc_cpu = PPC_OPCODE_PPC;
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@ -962,7 +963,7 @@ PowerPC options:\n\
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-mpwrx, -mpwr2 generate code for IBM POWER/2 (RIOS2)\n\
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-mpwr generate code for IBM POWER (RIOS1)\n\
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-m601 generate code for Motorola PowerPC 601\n\
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-mppc, -mppc32, -m403, -m603, -m604\n\
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-mppc, -mppc32, -m403, -m405, -m603, -m604\n\
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generate code for Motorola PowerPC 603/604\n\
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-mppc64, -m620 generate code for Motorola PowerPC 620\n\
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-mppc64bridge generate code for PowerPC 64, including bridge insns\n\
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@ -1,3 +1,11 @@
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2000-08-28 Mark Hatle <mhatle@mvista.com>
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* ppc-opc.c: Add XTLB macro for a few PPC 4xx extended mnemonics.
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(powerpc_opcodes): Add table entries for PPC 405 instructions.
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Changed rfci, icbt, mfdcr, dccci, mtdcr, iccci from PPC to PPC403
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instructions. Added extended mnemonic mftbl as defined in the
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405GP manual for all PPCs.
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2000-08-30 Kazu Hirata <kazu@hxi.com>
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* tic80-dis.c: Fix formatting.
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@ -1194,6 +1194,10 @@ extract_tbr (insn, invalid)
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#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
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#define XTO_MASK (X_MASK | TO_MASK)
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/* An X form tlb instruction with the SH field specified. */
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#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
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#define XTLB_MASK (X_MASK | SH_MASK)
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/* An XFL form instruction. */
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#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
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#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
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@ -1321,6 +1325,7 @@ extract_tbr (insn, invalid)
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#define PPC64 PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_ANY
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#define PPCONLY PPC_OPCODE_PPC
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#define PPC403 PPC
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#define PPC405 PPC403
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#define PPC750 PPC
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#define PPC860 PPC
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#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY
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@ -1400,7 +1405,91 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
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{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
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{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
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{ "macchw", XO(4,172,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchws", XO(4,236,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhw", XO(4,44,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhws", XO(4,108,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "mulchw", XRC(4,168,0), X_MASK, PPC405, { RT, RA, RB } },
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{ "mulchw.", XRC(4,168,1), X_MASK, PPC405, { RT, RA, RB } },
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{ "mulchwu", XRC(4,136,0), X_MASK, PPC405, { RT, RA, RB } },
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{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405, { RT, RA, RB } },
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{ "mulhhw", XRC(4,40,0), X_MASK, PPC405, { RT, RA, RB } },
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{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405, { RT, RA, RB } },
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{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405, { RT, RA, RB } },
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{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405, { RT, RA, RB } },
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{ "mullhw", XRC(4,424,0), X_MASK, PPC405, { RT, RA, RB } },
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{ "mullhw.", XRC(4,424,1), X_MASK, PPC405, { RT, RA, RB } },
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{ "mullhwu", XRC(4,392,0), X_MASK, PPC405, { RT, RA, RB } },
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{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405, { RT, RA, RB } },
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{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405, { RT, RA, RB } },
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{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405, { RT, RA, RB } },
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{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
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{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VD } },
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{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
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@ -2039,7 +2128,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
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{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
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{ "rfci", XL(19,51), 0xffffffff, PPC, { 0 } },
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{ "rfci", XL(19,51), 0xffffffff, PPC403, { 0 } },
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{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
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@ -2542,7 +2631,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "lhzx", X(31,279), X_MASK, COM, { RT, RA, RB } },
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{ "icbt", X(31,262), XRT_MASK, PPC, { RA, RB } },
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{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
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{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
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{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
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@ -2591,7 +2680,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
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{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
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{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
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{ "mfdcr", X(31,323), X_MASK, PPC, { RT, SPR } },
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{ "mfdcr", X(31,323), X_MASK, PPC403, { RT, SPR } },
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{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
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{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
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@ -2629,6 +2718,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
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{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
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{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
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{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } },
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{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } },
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{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } },
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{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } },
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{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
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{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
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{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
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@ -2669,9 +2762,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
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{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
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{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
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{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
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{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
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{ "mficdbdr",XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
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{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
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{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
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{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
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{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
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{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
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{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
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{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
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@ -2679,12 +2773,21 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
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{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
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{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
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{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
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{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
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{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
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{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
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{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
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{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
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{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
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{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
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{ "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
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{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
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{ "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
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{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
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{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
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{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
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{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
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{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
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{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
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{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
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||||
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|
@ -2698,6 +2801,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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|||
{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
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{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
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{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
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{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
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{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
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{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
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{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
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|
@ -2719,7 +2823,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
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{ "lhax", X(31,343), X_MASK, COM, { RT, RA, RB } },
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{ "dccci", X(31,454), XRT_MASK, PPC, { RA, RB } },
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{ "dccci", X(31,454), XRT_MASK, PPC403, { RA, RB } },
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||||
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{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
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{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
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|
@ -2733,6 +2837,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
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||||
{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
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||||
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||||
{ "mftbl", XSPR(31,371,268), XSPR_MASK, PPC, { RT } },
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||||
{ "mftbu", XSPR(31,371,269), XSPR_MASK, PPC, { RT } },
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||||
{ "mftb", X(31,371), X_MASK, PPC, { RT, TBR } },
|
||||
|
||||
|
|
@ -2820,7 +2925,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "mtthrm1", XSPR(31,451,1020), XSPR_MASK, PPC750, { RT } },
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||||
{ "mtthrm2", XSPR(31,451,1021), XSPR_MASK, PPC750, { RT } },
|
||||
{ "mtthrm3", XSPR(31,451,1022), XSPR_MASK, PPC750, { RT } },
|
||||
{ "mtdcr", X(31,451), X_MASK, PPC, { SPR, RS } },
|
||||
{ "mtdcr", X(31,451), X_MASK, PPC403, { SPR, RS } },
|
||||
|
||||
{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
|
||||
{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
|
||||
|
|
@ -2867,6 +2972,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RT } },
|
||||
{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RT } },
|
||||
{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RT } },
|
||||
{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
|
||||
{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
|
||||
{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
|
||||
|
|
@ -2877,8 +2986,19 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
|
||||
{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mticdbdr",XSPR(31,467,979), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RT } },
|
||||
|
|
@ -2889,6 +3009,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RT } },
|
||||
{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RT } },
|
||||
|
|
@ -3005,6 +3126,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
|
||||
{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
|
||||
|
||||
{ "dcba", X(31,758), XRT_MASK, PPC405, { RA, RB } },
|
||||
|
||||
{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
|
||||
|
||||
{ "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
|
||||
|
|
@ -3045,6 +3168,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
|
||||
{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
|
||||
|
||||
{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
|
||||
{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
|
||||
{ "tlbre", X(31,946), X_MASK, PPC403, { RT, RA, SH } },
|
||||
|
||||
{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
|
||||
|
|
@ -3053,9 +3178,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
|
||||
{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
|
||||
|
||||
{ "iccci", X(31,966), XRT_MASK, PPC, { RA, RB } },
|
||||
{ "iccci", X(31,966), XRT_MASK, PPC403, { RA, RB } },
|
||||
|
||||
{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
|
||||
|
||||
{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
|
||||
{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
|
||||
{ "tlbwe", X(31,978), X_MASK, PPC403, { RS, RA, SH } },
|
||||
|
||||
{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
|
||||
|
|
|
|||
Loading…
Reference in New Issue