[ gas/ChangeLog ]
* config/tc-mips.c (mips_set_options): Add ase_smartmips flag. (mips_opts): Likewise. (file_ase_smartmips): New variable. (ISA_HAS_ROR): SmartMIPS implements rotate instructions. (macro_build): Handle SmartMIPS instructions. (mips_ip): Likewise. (md_longopts): Add argument handling for smartmips. (md_parse_options, mips_after_parse_args): Likewise. (s_mipsset): Add .set smartmips support. (md_show_usage): Document -msmartmips/-mno-smartmips. * doc/as.texinfo: Document -msmartmips/-mno-smartmips and .set smartmips. * doc/c-mips.texi: Likewise. [ gas/testsuite/ChangeLog ] * gas/mips/smartmips.s, gas/mips/smartmips.d: New smartmips test. * gas/mips/mips.exp: Run smartmips test.
This commit is contained in:
Thiemo Seufer
parent
336e5de1c9
commit
e16bfa71a1
@ -1,3 +1,21 @@
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2006-05-08 Thiemo Seufer <ths@mips.com>
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Nigel Stephens <nigel@mips.com>
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David Ung <davidu@mips.com>
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* config/tc-mips.c (mips_set_options): Add ase_smartmips flag.
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(mips_opts): Likewise.
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(file_ase_smartmips): New variable.
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(ISA_HAS_ROR): SmartMIPS implements rotate instructions.
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(macro_build): Handle SmartMIPS instructions.
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(mips_ip): Likewise.
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(md_longopts): Add argument handling for smartmips.
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(md_parse_options, mips_after_parse_args): Likewise.
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(s_mipsset): Add .set smartmips support.
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(md_show_usage): Document -msmartmips/-mno-smartmips.
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* doc/as.texinfo: Document -msmartmips/-mno-smartmips and
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.set smartmips.
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* doc/c-mips.texi: Likewise.
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2006-05-08 Alan Modra <amodra@bigpond.net.au>
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* write.c (relax_segment): Add pass count arg. Don't error on
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@ -193,6 +193,7 @@ struct mips_set_options
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command line options, and based on the default architecture. */
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int ase_mips3d;
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int ase_mdmx;
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int ase_smartmips;
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int ase_dsp;
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int ase_mt;
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/* Whether we are assembling for the mips16 processor. 0 if we are
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@ -245,7 +246,7 @@ static int file_mips_fp32 = -1;
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static struct mips_set_options mips_opts =
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{
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ISA_UNKNOWN, -1, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE
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ISA_UNKNOWN, -1, -1, 0, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE
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};
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/* These variables are filled in with the masks of registers used.
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@ -269,6 +270,13 @@ static int file_ase_mips3d;
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command line (e.g., by -march). */
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static int file_ase_mdmx;
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/* True if -msmartmips was passed or implied by arguments passed on the
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command line (e.g., by -march). */
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static int file_ase_smartmips;
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#define ISA_SUPPORT_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
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|| mips_opts.isa == ISA_MIPS32R2)
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/* True if -mdsp was passed or implied by arguments passed on the
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command line (e.g., by -march). */
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static int file_ase_dsp;
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@ -318,6 +326,7 @@ static int mips_32bitmode = 0;
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#define ISA_HAS_ROR(ISA) ( \
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(ISA) == ISA_MIPS32R2 \
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|| (ISA) == ISA_MIPS64R2 \
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|| mips_opts.ase_smartmips \
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)
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#define HAVE_32BIT_GPRS \
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@ -3012,7 +3021,8 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
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|| mo->pinfo == INSN_MACRO
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|| !OPCODE_IS_MEMBER (mo,
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(mips_opts.isa
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| (file_ase_mips16 ? INSN_MIPS16 : 0)),
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| (file_ase_mips16 ? INSN_MIPS16 : 0)
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| (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)),
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mips_opts.arch)
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|| (mips_opts.arch == CPU_R4650 && (mo->pinfo & FP_D) != 0))
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{
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@ -8032,7 +8042,8 @@ mips_ip (char *str, struct mips_cl_insn *ip)
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| (mips_opts.ase_mdmx ? INSN_MDMX : 0)
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| (mips_opts.ase_dsp ? INSN_DSP : 0)
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| (mips_opts.ase_mt ? INSN_MT : 0)
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| (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
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| (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)
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| (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)),
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mips_opts.arch))
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ok = TRUE;
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else
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@ -10620,9 +10631,13 @@ struct option md_longopts[] =
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{"mmt", no_argument, NULL, OPTION_MT},
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#define OPTION_NO_MT (OPTION_ASE_BASE + 9)
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{"mno-mt", no_argument, NULL, OPTION_NO_MT},
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#define OPTION_SMARTMIPS (OPTION_ASE_BASE + 10)
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{"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
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#define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11)
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{"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
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/* Old-style architecture options. Don't add more of these. */
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#define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 10)
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#define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 12)
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#define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
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{"m4650", no_argument, NULL, OPTION_M4650},
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#define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
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@ -10910,6 +10925,14 @@ md_parse_option (int c, char *arg)
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mips_opts.ase_mips3d = 0;
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break;
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case OPTION_SMARTMIPS:
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mips_opts.ase_smartmips = 1;
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break;
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case OPTION_NO_SMARTMIPS:
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mips_opts.ase_smartmips = 0;
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break;
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case OPTION_FIX_VR4120:
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mips_fix_vr4120 = 1;
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break;
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@ -11248,6 +11271,7 @@ mips_after_parse_args (void)
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file_ase_mips16 = mips_opts.mips16;
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file_ase_mips3d = mips_opts.ase_mips3d;
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file_ase_mdmx = mips_opts.ase_mdmx;
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file_ase_smartmips = mips_opts.ase_smartmips;
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file_ase_dsp = mips_opts.ase_dsp;
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file_ase_mt = mips_opts.ase_mt;
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mips_opts.gp32 = file_mips_gp32;
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@ -12101,6 +12125,15 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
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else if (strcmp (name, "nomips16") == 0
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|| strcmp (name, "noMIPS-16") == 0)
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mips_opts.mips16 = 0;
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else if (strcmp (name, "smartmips") == 0)
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{
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if (!ISA_SUPPORT_SMARTMIPS)
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as_warn ("%s ISA does not support SmartMIPS ASE",
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mips_cpu_info_from_isa (mips_opts.isa)->name);
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mips_opts.ase_smartmips = 1;
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}
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else if (strcmp (name, "nosmartmips") == 0)
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mips_opts.ase_smartmips = 0;
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else if (strcmp (name, "mips3d") == 0)
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mips_opts.ase_mips3d = 1;
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else if (strcmp (name, "nomips3d") == 0)
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@ -14570,6 +14603,9 @@ MIPS options:\n\
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-mips16 generate mips16 instructions\n\
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-no-mips16 do not generate mips16 instructions\n"));
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fprintf (stream, _("\
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-msmartmips generate smartmips instructions\n\
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-mno-smartmips do not generate smartmips instructions\n"));
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fprintf (stream, _("\
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-mdsp generate DSP instructions\n\
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-mno-dsp do not generate DSP instructions\n"));
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fprintf (stream, _("\
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@ -367,6 +367,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
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[@b{-trap}] [@b{-no-break}] [@b{-break}] [@b{-no-trap}]
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[@b{-mfix7000}] [@b{-mno-fix7000}]
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[@b{-mips16}] [@b{-no-mips16}]
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[@b{-msmartmips}] [@b{-mno-smartmips}]
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[@b{-mips3d}] [@b{-no-mips3d}]
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[@b{-mdmx}] [@b{-no-mdmx}]
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[@b{-mdsp}] [@b{-mno-dsp}]
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@ -1006,6 +1007,12 @@ Generate code for the MIPS 16 processor. This is equivalent to putting
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@code{.set mips16} at the start of the assembly file. @samp{-no-mips16}
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turns off this option.
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@item -msmartmips
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@itemx -mno-smartmips
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Enables the SmartMIPS extension to the MIPS32 instruction set. This is
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equivalent to putting @code{.set smartmips} at the start of the assembly file.
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@samp{-mno-smartmips} turns off this option.
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@item -mips3d
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@itemx -no-mips3d
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Generate code for the MIPS-3D Application Specific Extension.
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@ -106,6 +106,14 @@ Generate code for the MIPS 16 processor. This is equivalent to putting
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@samp{.set mips16} at the start of the assembly file. @samp{-no-mips16}
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turns off this option.
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@item -msmartmips
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@itemx -mno-smartmips
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Enables the SmartMIPS extensions to the MIPS32 instruction set, which
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provides a number of new instructions which target smartcard and
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cryptographic applications. This is equivalent to putting
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@samp{.set smartmips} at the start of the assembly file.
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@samp{-mno-smartmips} turns off this option.
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@item -mips3d
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@itemx -no-mips3d
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Generate code for the MIPS-3D Application Specific Extension.
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@ -399,6 +407,10 @@ The directive @samp{.set mips16} puts the assembler into MIPS 16 mode,
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in which it will assemble instructions for the MIPS 16 processor. Use
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@samp{.set nomips16} to return to normal 32 bit mode.
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The @samp{.set smartmips} directive enables use of the SmartMIPS
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extensions to the MIPS32 @sc{isa}; the @samp{.set nosmartmips} directive
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reverses that.
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Traditional @sc{mips} assemblers do not support this directive.
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@node MIPS autoextend
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@ -1,3 +1,10 @@
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2006-05-08 Thiemo Seufer <ths@mips.com>
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Nigel Stephens <nigel@mips.com>
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David Ung <davidu@mips.com>
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* gas/mips/smartmips.s, gas/mips/smartmips.d: New smartmips test.
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* gas/mips/mips.exp: Run smartmips test.
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2006-05-05 Julian Brown <julian@codesourcery.com>
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* gas/arm/vfp-neon-overlap.s: New test. Overlapping VFP/Neon
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@ -766,6 +766,7 @@ if { [istarget mips*-*-vxworks*] } {
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run_list_test "noat-6" ""
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run_list_test "noat-7" ""
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run_dump_test_arches "smartmips" [mips_arch_list_matching mips32 !gpr64]
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run_dump_test_arches "mips32-dsp" [mips_arch_list_matching mips32r2]
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run_dump_test_arches "mips32-mt" [mips_arch_list_matching mips32r2 !gpr64]
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29
gas/testsuite/gas/mips/smartmips.d
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29
gas/testsuite/gas/mips/smartmips.d
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@ -0,0 +1,29 @@
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#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
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#name: SmartMIPS
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#as: -msmartmips
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.*: +file format .*mips.*
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Disassembly of section \.text:
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0+0000 <[^>]*> 00c52046 rorv \$4,\$5,\$6
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0+0004 <[^>]*> 00c52046 rorv \$4,\$5,\$6
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0+0008 <[^>]*> 00c52046 rorv \$4,\$5,\$6
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0+000c <[^>]*> 00c52046 rorv \$4,\$5,\$6
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0+0010 <[^>]*> 002527c2 ror \$4,\$5,0x1f
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0+0014 <[^>]*> 00252202 ror \$4,\$5,0x8
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0+0018 <[^>]*> 00252042 ror \$4,\$5,0x1
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0+001c <[^>]*> 00252002 ror \$4,\$5,0x0
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0+0020 <[^>]*> 002527c2 ror \$4,\$5,0x1f
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0+0024 <[^>]*> 00252042 ror \$4,\$5,0x1
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0+0028 <[^>]*> 00252602 ror \$4,\$5,0x18
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0+002c <[^>]*> 002527c2 ror \$4,\$5,0x1f
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0+0030 <[^>]*> 00252002 ror \$4,\$5,0x0
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0+0034 <[^>]*> 70a41088 lwxs \$2,\$4\(\$5\)
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0+0038 <[^>]*> 72110441 maddp \$16,\$17
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0+003c <[^>]*> 016c0459 multp \$11,\$12
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0+0040 <[^>]*> 00004052 mflhxu \$8
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0+0044 <[^>]*> 00800053 mtlhx \$4
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0+0048 <[^>]*> 70d80481 pperm \$6,\$24
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0+004c <[^>]*> 00000000 nop
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31
gas/testsuite/gas/mips/smartmips.s
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31
gas/testsuite/gas/mips/smartmips.s
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@ -0,0 +1,31 @@
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# Source file used to test SmartMIPS instruction set
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.text
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stuff:
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ror $4,$5,$6
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rorv $4,$5,$6
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rotr $4,$5,$6
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rotrv $4,$5,$6
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ror $4,$5,31
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ror $4,$5,8
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ror $4,$5,1
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ror $4,$5,0
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rotr $4,$5,31
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rol $4,$5,31
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rol $4,$5,8
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rol $4,$5,1
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rol $4,$5,0
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lwxs $2,$4($5)
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maddp $16,$17
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multp $11,$12
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mflhxu $8
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mtlhx $4
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pperm $6,$24
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.p2align 4
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