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x86: fold (supposed to be) identical code 

The Q and L suffix exclusion checks in match_template() ought to be
(kept) in sync as far as their FPU and SIMD aspects go. This was
already violated by only the Q one checking for active broadcast.
Convert the code such that there'll be only one instance of the logic,
the more that subsequently the logic is liable to need further
refinement / extension. (The alternative would be to drop all SIMD-ness
from the L part, but it is in principle possible to enable all sorts of
SIMD support with just a pre-386 CPU, via suitable .arch directives.)
This commit is contained in:
Jan Beulich 2020-03-06 08:55:03 +01:00
parent 672a349b01
commit e365e234ab
2 changed files with 20 additions and 27 deletions
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6
gas/ChangeLog
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@ -1,3 +1,9 @@
2020-03-06 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (match_template): Fold duplicate code in
logic rejecting certain suffixes in certain modes. Drop
pointless "else".
2020-03-06 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (process_suffix): Exlucde !vexw insns

41
gas/config/tc-i386.c
View File

@ -5874,43 +5874,30 @@ match_template (char mnem_suffix)
for (j = 0; j < MAX_OPERANDS; j++)
operand_types[j] = t->operand_types[j];
/* In general, don't allow 64-bit operands in 32-bit mode. */
if (i.suffix == QWORD_MNEM_SUFFIX
&& flag_code != CODE_64BIT
/* In general, don't allow
- 64-bit operands outside of 64-bit mode,
- 32-bit operands on pre-386. */
if (((i.suffix == QWORD_MNEM_SUFFIX
&& flag_code != CODE_64BIT
&& (t->base_opcode != 0x0fc7
|| t->extension_opcode != 1 /* cmpxchg8b */))
|| (i.suffix == LONG_MNEM_SUFFIX
&& !cpu_arch_flags.bitfield.cpui386))
&& (intel_syntax
? (t->opcode_modifier.mnemonicsize != IGNORESIZE
&& !t->opcode_modifier.broadcast
&& !t->opcode_modifier.broadcast
&& !intel_float_operand (t->name))
: intel_float_operand (t->name) != 2)
&& ((operand_types[0].bitfield.class != RegMMX
&& operand_types[0].bitfield.class != RegSIMD)
|| (operand_types[t->operands > 1].bitfield.class != RegMMX
&& operand_types[t->operands > 1].bitfield.class != RegSIMD))
&& (t->base_opcode != 0x0fc7
|| t->extension_opcode != 1 /* cmpxchg8b */))
continue;
/* In general, don't allow 32-bit operands on pre-386. */
else if (i.suffix == LONG_MNEM_SUFFIX
&& !cpu_arch_flags.bitfield.cpui386
&& (intel_syntax
? (t->opcode_modifier.mnemonicsize != IGNORESIZE
&& !intel_float_operand (t->name))
: intel_float_operand (t->name) != 2)
&& ((operand_types[0].bitfield.class != RegMMX
&& operand_types[0].bitfield.class != RegSIMD)
|| (operand_types[t->operands > 1].bitfield.class != RegMMX
&& operand_types[t->operands > 1].bitfield.class
!= RegSIMD)))
&& operand_types[t->operands > 1].bitfield.class != RegSIMD)))
continue;
/* Do not verify operands when there are none. */
else
{
if (!t->operands)
/* We've found a match; break out of loop. */
break;
}
if (!t->operands)
/* We've found a match; break out of loop. */
break;
if (!t->opcode_modifier.jump
|| t->opcode_modifier.jump == JUMP_ABSOLUTE)