x86: fold (supposed to be) identical code
The Q and L suffix exclusion checks in match_template() ought to be (kept) in sync as far as their FPU and SIMD aspects go. This was already violated by only the Q one checking for active broadcast. Convert the code such that there'll be only one instance of the logic, the more that subsequently the logic is liable to need further refinement / extension. (The alternative would be to drop all SIMD-ness from the L part, but it is in principle possible to enable all sorts of SIMD support with just a pre-386 CPU, via suitable .arch directives.)
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@ -1,3 +1,9 @@
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2020-03-06 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (match_template): Fold duplicate code in
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logic rejecting certain suffixes in certain modes. Drop
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pointless "else".
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2020-03-06 Jan Beulich <jbeulich@suse.com>
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2020-03-06 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (process_suffix): Exlucde !vexw insns
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* config/tc-i386.c (process_suffix): Exlucde !vexw insns
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@ -5874,43 +5874,30 @@ match_template (char mnem_suffix)
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for (j = 0; j < MAX_OPERANDS; j++)
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for (j = 0; j < MAX_OPERANDS; j++)
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operand_types[j] = t->operand_types[j];
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operand_types[j] = t->operand_types[j];
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/* In general, don't allow 64-bit operands in 32-bit mode. */
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/* In general, don't allow
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if (i.suffix == QWORD_MNEM_SUFFIX
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- 64-bit operands outside of 64-bit mode,
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&& flag_code != CODE_64BIT
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- 32-bit operands on pre-386. */
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if (((i.suffix == QWORD_MNEM_SUFFIX
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&& flag_code != CODE_64BIT
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&& (t->base_opcode != 0x0fc7
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|| t->extension_opcode != 1 /* cmpxchg8b */))
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|| (i.suffix == LONG_MNEM_SUFFIX
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&& !cpu_arch_flags.bitfield.cpui386))
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&& (intel_syntax
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&& (intel_syntax
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? (t->opcode_modifier.mnemonicsize != IGNORESIZE
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? (t->opcode_modifier.mnemonicsize != IGNORESIZE
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&& !t->opcode_modifier.broadcast
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&& !t->opcode_modifier.broadcast
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&& !intel_float_operand (t->name))
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&& !intel_float_operand (t->name))
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: intel_float_operand (t->name) != 2)
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: intel_float_operand (t->name) != 2)
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&& ((operand_types[0].bitfield.class != RegMMX
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&& ((operand_types[0].bitfield.class != RegMMX
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&& operand_types[0].bitfield.class != RegSIMD)
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&& operand_types[0].bitfield.class != RegSIMD)
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|| (operand_types[t->operands > 1].bitfield.class != RegMMX
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|| (operand_types[t->operands > 1].bitfield.class != RegMMX
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&& operand_types[t->operands > 1].bitfield.class != RegSIMD))
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&& operand_types[t->operands > 1].bitfield.class != RegSIMD)))
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&& (t->base_opcode != 0x0fc7
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|| t->extension_opcode != 1 /* cmpxchg8b */))
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continue;
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/* In general, don't allow 32-bit operands on pre-386. */
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else if (i.suffix == LONG_MNEM_SUFFIX
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&& !cpu_arch_flags.bitfield.cpui386
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&& (intel_syntax
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? (t->opcode_modifier.mnemonicsize != IGNORESIZE
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&& !intel_float_operand (t->name))
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: intel_float_operand (t->name) != 2)
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&& ((operand_types[0].bitfield.class != RegMMX
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&& operand_types[0].bitfield.class != RegSIMD)
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|| (operand_types[t->operands > 1].bitfield.class != RegMMX
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&& operand_types[t->operands > 1].bitfield.class
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!= RegSIMD)))
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continue;
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continue;
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/* Do not verify operands when there are none. */
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/* Do not verify operands when there are none. */
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else
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if (!t->operands)
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{
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/* We've found a match; break out of loop. */
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if (!t->operands)
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break;
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/* We've found a match; break out of loop. */
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break;
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}
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if (!t->opcode_modifier.jump
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if (!t->opcode_modifier.jump
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|| t->opcode_modifier.jump == JUMP_ABSOLUTE)
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|| t->opcode_modifier.jump == JUMP_ABSOLUTE)
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