[binutils, Arm] Add support for conditional instructions in Armv8.1-M Mainline
This patch adds the following instructions which are part of the Armv8.1-M Mainline: CINC CINV CNEG CSINC CSINV CSNEG CSET CSETM CSEL gas/ChangeLog: 2019-05-21 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (TOGGLE_BIT): New. (T16_32_TAB): New entries for cinc, cinv, cneg, csinc, csinv, csneg, cset, csetm and csel. (operand_parse_code): New OP_RR_ZR. (parse_operand): Handle case for OP_RR_ZR. (do_t_cond): New. (insns): New instructions for cinc, cinv, cneg, csinc, csinv, csneg, cset, csetm, csel. * testsuite/gas/arm/armv8_1-m-cond-bad.d: New test. * testsuite/gas/arm/armv8_1-m-cond-bad.l: New test. * testsuite/gas/arm/armv8_1-m-cond-bad.s: New test. * testsuite/gas/arm/armv8_1-m-cond.d: New test. * testsuite/gas/arm/armv8_1-m-cond.s: New test. opcodes/ChangeLog: 2019-05-21 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (enum mve_instructions): New enum for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv and cneg. (mve_opcodes): New instructions as above. (is_mve_encoding_conflict): Add cases for csinc, csinv, csneg and csel. (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
This commit is contained in:
Sudakshina Das
parent
23d00a419f
commit
e39c1607a2
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@ -1,3 +1,19 @@
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2019-05-21 Sudakshina Das <sudi.das@arm.com>
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* config/tc-arm.c (TOGGLE_BIT): New.
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(T16_32_TAB): New entries for cinc, cinv, cneg, csinc,
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csinv, csneg, cset, csetm and csel.
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(operand_parse_code): New OP_RR_ZR.
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(parse_operand): Handle case for OP_RR_ZR.
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(do_t_cond): New.
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(insns): New instructions for cinc, cinv, cneg, csinc,
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csinv, csneg, cset, csetm, csel.
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* testsuite/gas/arm/armv8_1-m-cond-bad.d: New test.
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* testsuite/gas/arm/armv8_1-m-cond-bad.l: New test.
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* testsuite/gas/arm/armv8_1-m-cond-bad.s: New test.
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* testsuite/gas/arm/armv8_1-m-cond.d: New test.
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* testsuite/gas/arm/armv8_1-m-cond.s: New test.
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2019-05-21 Sudakshina Das <sudi.das@arm.com>
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* config/tc-arm.c (operand_parse_code): New entries for
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@ -1009,6 +1009,9 @@ static void it_fsm_post_encode (void);
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} \
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while (0)
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/* Toggle value[pos]. */
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#define TOGGLE_BIT(value, pos) (value ^ (1 << pos))
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/* Pure syntax. */
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/* This array holds the chars that always start a comment. If the
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@ -6930,6 +6933,7 @@ enum operand_parse_code
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OP_RRe, /* ARM register, only even numbered. */
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OP_RRo, /* ARM register, only odd numbered, not r13 or r15. */
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OP_RRnpcsp_I32, /* ARM register (no BadReg) or literal 1 .. 32 */
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OP_RR_ZR, /* ARM register or ZR but no PC */
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OP_REGLST, /* ARM register list */
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OP_CLRMLST, /* CLRM register list */
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@ -7793,6 +7797,8 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
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case OP_oRMQRZ:
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po_reg_or_goto (REG_TYPE_MQ, try_rr_zr);
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break;
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case OP_RR_ZR:
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try_rr_zr:
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po_reg_or_goto (REG_TYPE_RN, ZR);
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break;
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@ -7880,6 +7886,7 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
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case OP_RMQRZ:
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case OP_oRMQRZ:
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case OP_RR_ZR:
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if (!inst.operands[i].iszr && inst.operands[i].reg == REG_PC)
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inst.error = BAD_PC;
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break;
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@ -11107,7 +11114,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
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inst.error = _("instruction does not accept unindexed addressing");
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}
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/* Table of Thumb instructions which exist in both 16- and 32-bit
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/* Table of Thumb instructions which exist in 16- and/or 32-bit
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encodings (the latter only in post-V6T2 cores). The index is the
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value used in the insns table below. When there is more than one
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possible 16-bit encoding for the instruction, this table always
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@ -11136,11 +11143,20 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
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X(_bflx, 0000, f070e001), \
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X(_bic, 4380, ea200000), \
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X(_bics, 4380, ea300000), \
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X(_cinc, 0000, ea509000), \
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X(_cinv, 0000, ea50a000), \
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X(_cmn, 42c0, eb100f00), \
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X(_cmp, 2800, ebb00f00), \
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X(_cneg, 0000, ea50b000), \
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X(_cpsie, b660, f3af8400), \
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X(_cpsid, b670, f3af8600), \
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X(_cpy, 4600, ea4f0000), \
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X(_csel, 0000, ea508000), \
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X(_cset, 0000, ea5f900f), \
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X(_csetm, 0000, ea5fa00f), \
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X(_csinc, 0000, ea509000), \
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X(_csinv, 0000, ea50a000), \
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X(_csneg, 0000, ea50b000), \
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X(_dec_sp,80dd, f1ad0d00), \
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X(_dls, 0000, f040e001), \
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X(_dlstp, 0000, f000e001), \
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@ -11955,6 +11971,60 @@ do_t_clz (void)
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inst.instruction |= Rm;
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}
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/* For the Armv8.1-M conditional instructions. */
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static void
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do_t_cond (void)
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{
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unsigned Rd, Rn, Rm;
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signed int cond;
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constraint (inst.cond != COND_ALWAYS, BAD_COND);
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Rd = inst.operands[0].reg;
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switch (inst.instruction)
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{
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case T_MNEM_csinc:
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case T_MNEM_csinv:
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case T_MNEM_csneg:
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case T_MNEM_csel:
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Rn = inst.operands[1].reg;
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Rm = inst.operands[2].reg;
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cond = inst.operands[3].imm;
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constraint (Rn == REG_SP, BAD_SP);
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constraint (Rm == REG_SP, BAD_SP);
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break;
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case T_MNEM_cinc:
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case T_MNEM_cinv:
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case T_MNEM_cneg:
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Rn = inst.operands[1].reg;
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cond = inst.operands[2].imm;
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/* Invert the last bit to invert the cond. */
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cond = TOGGLE_BIT (cond, 0);
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constraint (Rn == REG_SP, BAD_SP);
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Rm = Rn;
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break;
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case T_MNEM_csetm:
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case T_MNEM_cset:
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cond = inst.operands[1].imm;
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/* Invert the last bit to invert the cond. */
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cond = TOGGLE_BIT (cond, 0);
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Rn = REG_PC;
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Rm = REG_PC;
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break;
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default: abort ();
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}
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set_pred_insn_type (OUTSIDE_PRED_INSN);
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inst.instruction = THUMB_OP32 (inst.instruction);
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inst.instruction |= Rd << 8;
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inst.instruction |= Rn << 16;
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inst.instruction |= Rm;
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inst.instruction |= cond << 4;
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}
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static void
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do_t_csdb (void)
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{
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@ -25157,6 +25227,16 @@ static const struct asm_opcode insns[] =
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/* Armv8.1-M Mainline instructions. */
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#undef THUMB_VARIANT
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#define THUMB_VARIANT & arm_ext_v8_1m_main
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toU("cinc", _cinc, 3, (RRnpcsp, RR_ZR, COND), t_cond),
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toU("cinv", _cinv, 3, (RRnpcsp, RR_ZR, COND), t_cond),
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toU("cneg", _cneg, 3, (RRnpcsp, RR_ZR, COND), t_cond),
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toU("csel", _csel, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond),
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toU("csetm", _csetm, 2, (RRnpcsp, COND), t_cond),
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toU("cset", _cset, 2, (RRnpcsp, COND), t_cond),
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toU("csinc", _csinc, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond),
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toU("csinv", _csinv, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond),
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toU("csneg", _csneg, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond),
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toC("bf", _bf, 2, (EXPs, EXPs), t_branch_future),
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toU("bfcsel", _bfcsel, 4, (EXPs, EXPs, EXPs, COND), t_branch_future),
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toC("bfx", _bfx, 2, (EXPs, RRnpcsp), t_branch_future),
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@ -0,0 +1,4 @@
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#name: Invalid Armv8.1-M Mainline conditional instructions
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#source: armv8_1-m-cond-bad.s
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#as: -march=armv8.1-m.main
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#error_output: armv8_1-m-cond-bad.l
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@ -0,0 +1,8 @@
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.*: Assembler messages:
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.*: Error: condition required -- `cset r4,r2,ne'
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.*: Error: r13 not allowed here -- `csetm sp,ne'
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.*: Error: r15 not allowed here -- `cinc r3,pc,lt'
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.*: Error: r15 not allowed here -- `cinv pc,r2,lt'
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.*: Error: r13 not allowed here -- `cneg r3,sp,lt'
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.*: Error: instruction not allowed in IT block -- `csinc r3,r2,r4,lt'
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.*: Error: instruction cannot be conditional -- `csnegne r3,r2,r4,lt'
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@ -0,0 +1,15 @@
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.syntax unified
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.text
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foo:
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cset r4, r2, ne
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csetm sp, ne
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cinc r3, pc, lt
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cinv pc, r2, lt
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cneg r3, sp, lt
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it eq
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csinc r3, r2, r4, lt
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csinv r3, r4, r4, lt
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it ne
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csnegne r3, r2, r4, lt
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csinv r3, r4, r4, lt
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@ -0,0 +1,21 @@
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#name: Valid Armv8.1-M Mainline conditional instructions
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#source: armv8_1-m-cond.s
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#as: -march=armv8.1-m.main
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#objdump: -dr --prefix-addresses --show-raw-insn -marmv8.1-m.main
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.*: +file format .*arm.*
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Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> ea5f 940f cset r4, ne
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0[0-9a-f]+ <[^>]+> ea5f a40f csetm r4, ne
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0[0-9a-f]+ <[^>]+> ea52 93a2 cinc r3, r2, lt
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0[0-9a-f]+ <[^>]+> ea52 a3a2 cinv r3, r2, lt
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0[0-9a-f]+ <[^>]+> ea52 b3a2 cneg r3, r2, lt
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0[0-9a-f]+ <[^>]+> ea52 93b4 csinc r3, r2, r4, lt
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0[0-9a-f]+ <[^>]+> ea54 93b4 cinc r3, r4, ge
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0[0-9a-f]+ <[^>]+> ea5f 93bf cset r3, ge
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0[0-9a-f]+ <[^>]+> ea52 a3b4 csinv r3, r2, r4, lt
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0[0-9a-f]+ <[^>]+> ea54 a3b4 cinv r3, r4, ge
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0[0-9a-f]+ <[^>]+> ea5f a3bf csetm r3, ge
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0[0-9a-f]+ <[^>]+> ea52 b3b4 csneg r3, r2, r4, lt
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0[0-9a-f]+ <[^>]+> ea54 b3b4 cneg r3, r4, ge
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@ -0,0 +1,17 @@
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.syntax unified
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.text
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foo:
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cset r4, ne
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csetm r4, ne
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cinc r3, r2, lt
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cinv r3, r2, lt
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cneg r3, r2, lt
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csinc r3, r2, r4, lt
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csinc r3, r4, r4, lt
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csinc r3, zr, zr, lt
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csinv r3, r2, r4, lt
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csinv r3, r4, r4, lt
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csinv r3, zr, zr, lt
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csneg r3, r2, r4, lt
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csneg r3, r4, r4, lt
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@ -1,3 +1,13 @@
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2019-05-21 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (enum mve_instructions): New enum
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for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
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and cneg.
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(mve_opcodes): New instructions as above.
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(is_mve_encoding_conflict): Add cases for csinc, csinv,
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csneg and csel.
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(print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
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2019-05-21 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (emun mve_instructions): Updated for new instructions.
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@ -281,6 +281,15 @@ enum mve_instructions
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MVE_SRSHR,
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MVE_SQSHLL,
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MVE_SQSHL,
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MVE_CINC,
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MVE_CINV,
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MVE_CNEG,
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MVE_CSINC,
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MVE_CSINV,
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MVE_CSET,
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MVE_CSETM,
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MVE_CSNEG,
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MVE_CSEL,
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MVE_NONE
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};
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@ -2060,6 +2069,8 @@ static const struct opcode32 neon_opcodes[] =
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%<bitfield>r print as an ARM register
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%<bitfield>d print the bitfield in decimal
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%<bitfield>A print accumulate or not
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%<bitfield>c print bitfield as a condition code
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%<bitfield>C print bitfield as an inverted condition code
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%<bitfield>Q print as a MVE Q register
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%<bitfield>F print as a MVE S register
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%<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
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@ -3400,6 +3411,51 @@ static const struct mopcode32 mve_opcodes[] =
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0xea500f1f, 0xfff08f3f,
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"urshr%c\t%16-19S, %j"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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MVE_CSINC,
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0xea509000, 0xfff0f000,
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"csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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MVE_CSINV,
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0xea50a000, 0xfff0f000,
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"csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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MVE_CSET,
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0xea5f900f, 0xfffff00f,
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"cset\t%8-11S, %4-7C"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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MVE_CSETM,
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0xea5fa00f, 0xfffff00f,
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"csetm\t%8-11S, %4-7C"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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MVE_CSEL,
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0xea508000, 0xfff0f000,
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"csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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MVE_CSNEG,
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0xea50b000, 0xfff0f000,
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"csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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MVE_CINC,
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0xea509000, 0xfff0f000,
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"cinc\t%8-11S, %16-19Z, %4-7C"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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MVE_CINV,
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0xea50a000, 0xfff0f000,
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"cinv\t%8-11S, %16-19Z, %4-7C"},
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{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
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MVE_CNEG,
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0xea50b000, 0xfff0f000,
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"cneg\t%8-11S, %16-19Z, %4-7C"},
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{ARM_FEATURE_CORE_LOW (0),
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MVE_NONE,
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0x00000000, 0x00000000, 0}
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@ -5653,6 +5709,30 @@ is_mve_encoding_conflict (unsigned long given,
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else
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return FALSE;
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case MVE_CSINC:
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case MVE_CSINV:
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{
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unsigned long rm, rn;
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rm = arm_decode_field (given, 0, 3);
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rn = arm_decode_field (given, 16, 19);
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/* CSET/CSETM. */
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if (rm == 0xf && rn == 0xf)
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return TRUE;
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/* CINC/CINV. */
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else if (rn == rm && rn != 0xf)
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return TRUE;
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}
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/* Fall through. */
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case MVE_CSEL:
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case MVE_CSNEG:
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if (arm_decode_field (given, 0, 3) == 0xd)
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return TRUE;
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/* CNEG. */
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else if (matched_insn == MVE_CSNEG)
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if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19))
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return TRUE;
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return FALSE;
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default:
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case MVE_VADD_FP_T1:
|
||||
case MVE_VADD_FP_T2:
|
||||
|
|
@ -9264,6 +9344,15 @@ print_insn_mve (struct disassemble_info *info, long given)
|
|||
func (stream, "%s", arm_regnames[value]);
|
||||
break;
|
||||
|
||||
case 'c':
|
||||
func (stream, "%s", arm_conditional[value]);
|
||||
break;
|
||||
|
||||
case 'C':
|
||||
value ^= 1;
|
||||
func (stream, "%s", arm_conditional[value]);
|
||||
break;
|
||||
|
||||
case 'S':
|
||||
if (value == 13 || value == 15)
|
||||
is_unpredictable = TRUE;
|
||||
|
|
|
|||
Loading…
Reference in New Issue