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Delete TiC80, no longer supported by GDB.

This commit is contained in:
Andrew Cagney 2002-06-01 23:23:28 +00:00
parent b646261c73
commit e4045cdb95
16 changed files with 4 additions and 8593 deletions
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4
sim/ChangeLog
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@ -1,3 +1,7 @@
2002-06-01 Andrew Cagney <ac131313@redhat.com>
* tic80/: Delete directory.
2002-05-16 Stephane Carrez <stcarrez@nerim.fr>
* MAINTAINERS: Update my email address.

662
sim/tic80/ChangeLog
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@ -1,662 +0,0 @@
Tue Jul 4 13:58:43 2000 Andrew Cagney <cagney@b1.cygnus.com>
* tic80.igen: Rename insns. Re-format.
* tic80.dc: rename dc.
* tic80.ic: rename ic. Replace ``compute'' with ``cache''.
Wed May 24 14:40:34 2000 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
2000-04-12 Frank Ch. Eigler <fche@redhat.com>
* cpu.h (GPR_CLEAR): New macro.
(GPR_SET): Removed macro.
Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
1999-05-08 Felix Lee <flee@cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
Fri May 1 14:41:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
* insns: Pass correct arguments to sim_engine_abort.
Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
* configure: Regenerated to track ../common/aclocal.m4 changes.
* config.in: Ditto.
Sun Apr 26 15:19:45 1998 Tom Tromey <tromey@cygnus.com>
* acconfig.h: New file.
* configure.in: Reverted change of Apr 24; use sinclude again.
Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
* configure: Regenerated to track ../common/aclocal.m4 changes.
* config.in: Ditto.
Fri Apr 24 11:18:28 1998 Tom Tromey <tromey@cygnus.com>
* configure.in: Don't call sinclude.
Fri Apr 24 19:43:30 1998 Andrew Cagney <cagney@b1.cygnus.com>
* ic (rBase, rLink): Make the type a pointer.
Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
Wed Mar 11 14:12:56 1998 Andrew Cagney <cagney@b1.cygnus.com>
* alu.h (IMEM32_IMMED, IMEM32, STORE, MEM): Replace sim_core_*_map
with read_map, write_map, exec_map resp.
Thu Feb 26 19:08:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
* sim-calls.c (sim_info): Delete.
Tue Feb 17 14:35:05 1998 Michael Meissner <meissner@cygnus.com>
* misc.c (tic80_trace_cond_br): Take size/code arguments, and
decode bcond conditions and bbo/bbz comparison bits.
* cpu.h (tic80_trace_cond_br): Update prototype.
(TRACE_COND_PR): Take size/code additional arguments.
* insns: (bbo/bbz/bcnd): Update call to TRACE_COND_PR.
Tue Feb 17 12:50:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
* sim-calls.c (sim_store_register, sim_fetch_register): Pass in
length parameter. Return -1.
Fri Feb 13 17:11:22 1998 Michael Meissner <meissner@cygnus.com>
* insns ({get,set}_fp_reg): Tic80 floating point is little endian,
not big endian.
* misc.c (tic80_trace_fpu*): Pass address of sim_fpu structure,
not the structure itself. Use %g consistantly to print floating
point.
* cpu.h: (tic80_trace_fpu*): Update prototypes.
Tue Feb 3 16:25:47 1998 Andrew Cagney <cagney@b1.cygnus.com>
* alu.h (IMEM32, IMEM32_IMMED): Rename IMEM and IMEM_IMMED so that
in sync with recent igen change.
Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
Fri Jan 30 11:47:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
* cpu.h (CPU_CIA): Delete macro, replace with...
(CIA_SET, CIA_GET): Define.
Wed Jan 28 18:44:33 1998 Michael Meissner <meissner@cygnus.com>
* misc.c (tic80_trace_cmp_internal): New function to return
compare bits as a string.
(tic80_trace_{,fpu2}cmp): New functions for tracing cmp and fcmp.
* cpu.h (tic80_trace_{,fpu2}cmp): Add declaration.
(TRACE_{,FPU2}CMP): New macros for tracing compares.
* insns (do_{,f}cmp): Use compare specific tracing functions to
print out the flag bits.
Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
* configure: Regenerated to track ../common/aclocal.m4 changes.
Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
* config.in: Ditto.
Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
Mon Nov 24 14:57:58 1997 Doug Evans <devans@seba.cygnus.com>
* cpu.h (TRACE_COND_BR): Use TRACE_BRANCH_P, not TRACE_ALU_P.
Sat Nov 22 21:42:09 1997 Andrew Cagney <cagney@b1.cygnus.com>
* interp.c (engine_step): Replace SIGTRAP with SIM_SIGTRAP.
(engine_run_until_stop): Replace SIGINT with SIM_SIGINT.
* sim-main.h: Include sim-signal.h.
(SIGTRAP): Delete definition.
* interp.c, sim-calls.c: Do not include signal.h.
* insns (illegal): SIGILL -> SIM_SIGILL.
(fp_unavailable): SIGFPE -> SIM_SIGFPE.
(do_trap): SIGTRAP -> SIM_SIGTRAP.
Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
* sim-main.h (CIA_ADDR): Define.
* Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
Fri Oct 17 17:26:36 1997 Andrew Cagney <cagney@b1.cygnus.com>
* alu.h (ALU32_END): Use ALU32_RESULT.
Mon Sep 29 12:49:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
* insns (get_fp_reg, set_fp_reg): Update to use changed sim_fpu
interface.
(do_fadd, do_fcmp, do_fdiv, do_fmpy, do_frnd, do_fsub): Ditto.
* misc.c (tic80_trace_fpu3, tic80_trace_fpu2, tic80_trace_fpu1,
tic80_trace_fpu2i) Update to use changed sim_fpu interface.
Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
* configure.in (SIM_AC_OPTIONS_BITSIZE): Define.
* configure: Regenerated to track ../common/aclocal.m4 changes.
Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
* Makefile.in (SIM_WARNINGS, SIM_ALIGNMENT, SIM_ENDIAN,
SIM_HOSTENDIAN, SIM_INLINE, SIM_RESERVED_BITS): Delete, moved to
common.
(SIM_EXTRA_CFLAGS): Update.
Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
Tue Sep 16 23:10:03 1997 Felix Lee <flee@cygnus.com>
* sim-main.h (kill): macro was missing args.
(SIGTRAP): define for MSVC.
Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
Mon Sep 8 20:10:43 1997 Andrew Cagney <cagney@b1.cygnus.com>
* cpu.h (CPU_CIA): Define.
* sim-main.h (struct sim_state): Delete halt_ok, path_to_halt,
restart_ok, path_to_restart members.
(struct sim_state): Delete reason, siggnal members.
Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
* configure: Regenerated to track ../common/aclocal.m4 changes.
Thu Sep 4 17:45:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
* sim-calls.c (sim_open): Add memory before parsing arguments.
(sim_read): Delete, replace with sim-hrw.
(sim_write): Delete, replace with sim-hrw.
Thu Sep 4 10:48:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
* sim-calls.c (sim_open): Use sim_do_command to add memory, only
add memory if none already present.
(sim_open): Move init of registers from here.
(sim_create_inferior): To here. Init modules.
* Makefile.in (SIM_OBJS): Add sim-memopt.o module.
* sim-calls.c (sim_open): Add zero modulo arg to sim_core_attach.
Mon Sep 1 11:06:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
* sim-calls.c (sim_open): Use sim_state_alloc
(simulation): Delete.
Sat Aug 30 09:40:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
* insns (do_trap): Unsigned `i' for unsigned iterator.
(do_trap): Ditto for comparison with getpid.
Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
* config.in: Ditto.
Wed Aug 27 13:41:24 1997 Andrew Cagney <cagney@b1.cygnus.com>
* insns (do_st): Use U8_4 instead of V4_L8.
* sim-calls.c (sim_open): Add call to sim_analyze_program, update
call to sim_config.
* sim-calls.c (sim_kill): Delete.
(sim_create_inferior): Add ABFD argument. Initialize PC from ABFD
and not SD.
(sim_load): Delete, use sim-hload.c.
* Makefile.in (SIM_OBJS): Add sim-hload.o module.
Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
* config.in: Ditto.
Mon Aug 25 16:33:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
* sim-calls.c (sim_open): Add ABFD argument.
(sim_open): Move sim_config call to just after argument
parsing. Check return status.
Fri Aug 8 21:52:27 1997 Mark Alexander <marka@cygnus.com>
* sim-calls.c (sim_store_register): Allow accumulators
other than A0 to be modified. Correct error message.
Thu May 29 14:02:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
* misc.c (tic80_trace_fpu3, tic80_trace_fpu2, tic80_trace_fpu1,
tic80_trace_fpu2i): Pass in function prefix.
(tic80_trace_ldst): Rewrite so it calls print_one_insn directly.
* Makefile.in (SIM_OBJS): Include sim-watch.o module.
* sim-main.h (WITH_WATCHPOINTS): Enable watchpoints.
* ic (bitnum): Compute bitnum from BITNUM.
* insn (bbo, bbz): Use.
* insn: Convert long immediate instructions to igen long immediate
form.
* insn: Add disasembler information.
Thu May 29 12:09:13 1997 Andrew Cagney <cagney@b2.cygnus.com>
* alu.h (IMEM_IMMED): New macro, fetch 32bit immediate operand N.
* insns (subu i): Immediate is signed not unsigned.
Tue May 27 13:22:13 1997 Andrew Cagney <cagney@b1.cygnus.com>
* sim-calls.c (sim_read): Pass NULL cpu to sim_core_read_buffer.
(sim_write): Ditto for write.
Tue May 20 09:33:31 1997 Andrew Cagney <cagney@b1.cygnus.com>
* sim-calls.c (sim_load): Set STATE_LOADED_P.
* sim-main.h: Include <unistd.h>.
* sim-calls.c (sim_set_callback): Delete.
(sim_open): Add/install callback argument.
(sim_size): Delete.
Mon May 19 18:59:33 1997 Mike Meissner <meissner@cygnus.com>
* configure.in: Check for getpid, kill functions.
* config{.in,ure}: Regenerate.
* insns (do_trap): Add support for kill, getpid system calls.
* sim-main.h (errno.h): Include.
(getpid,kill): Define as NOPs if the host doesn't have them.
Mon May 19 14:58:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
* sim-calls.c (sim_open): Set the simulator base magic number.
(sim_load): Delete prototype of sim_load_file.
(sim_open): Define sd to be &simulation.
Fri May 16 14:35:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
* insns (illegal, fp_unavailable): Halt instead of abort the
simulator.
* insns: Replace calls to engine_error with sim_engine_abort.
Ditto for engine_halt V sim_engine_halt.
Tue May 13 15:24:12 1997 Andrew Cagney <cagney@b2.cygnus.com>
* interp.c (engine_run_until_stop): Delete. Moved to common.
(engine_step): Ditto.
(engine_step): Ditto.
(engine_halt): Ditto.
(engine_restart): Ditto.
(engine_halt): Ditto.
(engine_error): Ditto.
* sim-calls.c (sim_stop): Delete. Moved to common.
(sim_stop_reason): Ditto.
(sim_resume): Ditto.
* Makefile.in (SIM_OBJS): Link in generic sim-engine, sim-run,
sim-resume, sim-reason, sim-stop modules.
Fri May 16 11:57:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
* ic (compute): Drop check for REG == 0, now always forced to
zero.
* cpu.h (GPR_SET): New macro update the gpr.
* insns (do_add): Use GPR_SET to update the GPR register.
* sim-calls.c (sim_fetch_register): Pretend that r0 is zero.
* Makefile.in (tmp-igen): Specify zero-r0 so that every
instruction clears r0.
* interp.c (engine_run_until_stop): Igen now generates code to
clear r0.
(engine_step): Ditto.
Thu May 15 11:45:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
* insns (do_shift): When rot==0 and zero/sign merge treat it as
32.
(set_fp_reg): For interger conversion, use sim-fpu fpu2i
functions.
(do_fmpy): Perform iii and uuu using integer arithmetic.
* Makefile.in (ENGINE_H): Assume everything depends on the fpu.
* insns (get_fp_reg): Use sim_fpu_u32to to perform unsigned
conversion.
(do_fcmp): Update to use new fp compare functions. Make reg nr arg
instead of reg. Stops fp overflow.
(get_fp_reg): Assume val is valid when reg == 0.
(set_fp_reg): Fix double conversion.
* misc.c (tic80_trace_fpu1): New function, trace simple fp op.
* insns (do_frnd): Add tracing.
* cpu.h (TRACE_FPU1): Ditto.
* insns (do_trap): Printf formatting.
Wed May 14 18:05:50 1997 Mike Meissner <meissner@cygnus.com>
* misc.c (tic80_trace_fpu{3,2,2i}): Align columns with other
insns. Use %g to print floating point instead of %f in case the
numbers are real large.
Tue May 13 18:00:10 1997 Mike Meissner <meissner@cygnus.com>
* insns (do_trap): For system calls that are defined, but not
provided return EINVAL. Temporarily add traps 74-79 to just print
the register state.
* interp.c (engine_{run_until_stop,step}): Before executing
instructions, make sure r0 == 0.
Tue May 13 16:39:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
* alu.h (IMEM): Take full cia not just IP as argument.
* interp.c (engine_run_until_stop): Delete handling of annuled
instructions.
(engine_step): Ditto.
* insn (do_branch): New function.
(do_bbo, do_bbz, do_bcnd, do_bsr, do_jsr): Use do_branch to handle
annuled branches.
Mon May 12 17:15:52 1997 Mike Meissner <meissner@cygnus.com>
* insns (do_{ld,st}): Fix tracing for ld/st.
Mon May 12 11:12:24 1997 Andrew Cagney <cagney@b1.cygnus.com>
* sim-calls.c (sim_stop_reason): Restore keep_running after a
CNTRL-C, don't re-clear it.
* interp.c (engine_error): stop rather than signal with SIGABRT
when an error.
* insns (do_ld): For 64bit loads, always store LSW in rDest, MSW in
rDest + 1. Also done by Michael Meissner <meissner@cygnus.com>
(do_st): Converse for store.
* misc.c (tic80_trace_fpu2i): Correct printf format for int type.
Sun May 11 11:02:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
* sim-calls.c (sim_stop_reason): Return a SIGINT if keep_running
was cleared.
* interp.c (engine_step): New function. Single step the simulator
taking care of cntrl-c during a step.
* sim-calls.c (sim_resume): Differentiate between stepping and
running so that a cntrl-c during a step is reported.
Sun May 11 10:54:31 1997 Mark Alexander <marka@cygnus.com>
* sim-calls.c (sim_fetch_register): Use correct reg base.
(sim_store_register): Ditto.
Sun May 11 10:25:14 1997 Michael Meissner <meissner@cygnus.com>
* cpu.h (tic80_trace_shift): Add declaration.
(TRACE_SHIFT): New macro to trace shift instructions.
* misc.c (tic80_trace_alu2): Align spacing.
(tic80_trace_shift): New function to trace shifts.
* insns (lmo): Add missing 0b prefix to bits.
(do_shift): Use ~ (unsigned32)0, instead of -1. Use TRACE_SHIFT
instead of TRACE_ALU2.
(sl r): Use EndMask as is, instead of using Source+1 register.
(subu): Operands are unsigned, not signed.
(do_{ld,st}): Fix endian problems with ld.d/st.d.
Sat May 10 12:35:47 1997 Michael Meissner <meissner@cygnus.com>
* insns (and{.tt,.tf,.ft,.ff}): Immediate values are unsigned, not
signed.
Fri May 9 15:47:36 1997 Mike Meissner <meissner@cygnus.com>
* insns (cmp_vals,do_cmp): Produce the correct bits as specified
by the architecture.
(xor): Fix xor immediate patterns to use the correct bits.
Fri May 9 09:55:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
* alu.h (long_immediate): Adjust the CIA delay-pointer as well as
the NIA when a 64bit insn.
Thu May 8 11:57:47 1997 Michael Meissner <meissner@cygnus.com>
* insns (jsr,bsr): For non-allulled calls, set r31 so that the
return address does not reexecute the instruction in the delay
slot.
(bbo,bbz): Complement bit number to reverse the one's complement
that the assembler is required to do.
* misc.c (tic80_trace_*): Change format slightly to accomidate
real large decimal values.
Thu May 8 14:07:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
* sim-calls.c (sim_do_command): Implement.
(sim_store_register): Fix typo T2H v H2T.
Wed May 7 11:48:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
* cpu.h (TRACE_FPU2, TRACE_FPU3, TRACE_FPU2I): Add.
* insn: Clean up fpu tracing.
* sim-calls.c (sim_create_inferior): Start out with interrupts
enabled.
* cpu.h (TRACE_SINK3), misc.c (tic80_trace_sink3): Three argument
sink
* insns (rdcr, swcr, wrcr, brcr, rmo, lmo): Implement.
* insns (do_*): Remove MY_INDEX/indx argument from support functions,
igen now handles this.
* cpu.h (CR): New macro - access TIc80 control registers.
* misc.c: New file.
(tic80_cr2index): New function, map control register opcode index
into the internal CR enum.
* interp.c
(tic80_trace_{alu{2,3},nop,sink{1,2},{,u}cond_br,ldst}): Move from
here
* misc.c: to here.
* Makefile.in (SIM_OBJS): Add misc.o.
Tue May 6 15:22:58 1997 Mike Meissner <meissner@cygnus.com>
* cpu.h ({,v}{S,D}P_FPR): Delete unused macros that won't work on
big endian hosts.
(tic80_trace_{alu{2,3},nop,sink{1,2},{,u}cond_br,ldst}): Declare
new functions.
(TRACE_{ALU{2,3},NOP,SINK{1,2},{,U}COND_BR,LD,ST}): New macros to
trace various instruction types.
* insns: Modify all instructions to support semantic tracing.
* interp.c (toplevel): Include itable.h.
(tic80_trace_{alu{2,3},nop,sink{1,2},{,u}cond_br,ldst}): New
functions to provide semantic level tracing information.
Mon May 5 11:50:43 1997 Andrew Cagney <cagney@b1.cygnus.com>
* alu.h: Update usage of core object to reflect recent changes in
../common/sim-*core.
* sim-calls.c (sim_open): Ditto.
Mon May 5 14:10:17 1997 Andrew Cagney <cagney@b1.cygnus.com>
* insn (cmnd): No-op cache flushes.
* insns (do_trap): Allow writes to STDERR.
* Makefile.in (SIM_OBJS): Link in sim-fpu.o.
(SIM_EXTRA_LIBS): Link in the math library.
* alu.h: Add support for floating point unit using sim-alu.
* insns (fadd, fsub, fmpy, fdiv, fcmp, frnd*): Implement.
Fri May 2 14:57:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
* sim-calls.c: Include sim-utils.h and sim-options.h.
* sim-main.h (sim_state): Drop sim_events and sim_core members,
moved to simulator base type.
* alu.h (IMEM, MEM, STORE): Update track changes in common
directory.
* insns: Drop cia argument from functions, igen now handles this.
* interp.c (engine_init): Include string.h/strings.h to define
memset et.al.
* sim-main.h (sim_cia): Delcare, tracking common dir changes.
* cpu.h (sim_cpu): Update instruction_address with sim_cia.
Wed Apr 30 11:26:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
* sim-main.h (signal.h): Include so that SIG* available to all
callers of sig_halt.
* insns (do_shift): New function, implement shift operations.
(do_trap): Add handler for trap 73 - SIGTRAP.
Tue Apr 29 10:58:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
* alu.h (MEM, STORE): Force addresses to be correctly aligned.
* insns (do_jsr): Fix.
(do_st, do_ld): Handle 64bit transfers.
(do_trap): Match libgloss.
(rdcr): Implement nop - Dest == r0 - variant.
* sim-calls.c (sim_create_inferior): Initialize SP.
* Makefile.in (ENGINE_H): Everything now depends on sim-options.h.
(support.o): Depends on ENGINE_H.
* cpu.h: Four accumulators.
* Makefile.in (tmp-igen): Include line number information in
generated files.
* insns (dld, dst): Fill in.
Mon Apr 28 13:02:26 1997 Andrew Cagney <cagney@b1.cygnus.com>
* insns (vld): Fix instruction format wrong.
Thu Apr 24 16:43:09 1997 Andrew Cagney <cagney@b1.cygnus.com>
* dc: Add additional rules so that minor opcode files are
detected.
* insns: Enable more instructions.
* sim-calls.c (sim_fetch_register,sim_store_register, sim_write):
Implement.
Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
* Makefile.in (SIM_OBJS): Add sim-module.o, sim-profile.o.
* sim-calls.c (sim_open): Call sim_module_uninstall if argument
parsing fails. Call sim_post_argv_init.
(sim_close): Call sim_module_uninstall.
Wed Apr 23 20:05:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
* insns (and, bbo, bcnd, bsr, dcache, jsr, or, xor, nor): Enable.
* ic: Add fields for enabled instructions.

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sim/tic80/Makefile.in
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# Makefile for blah ...
# Copyright blah ...
## COMMON_PRE_CONFIG_FRAG
# These variables are given default values in COMMON_PRE_CONFIG_FRAG.
# We override the ones we need to here.
# Not all of these need to be mentioned, only the necessary ones.
# List of object files, less common parts.
SIM_OBJS = \
$(SIM_NEW_COMMON_OBJS) \
support.o idecode.o semantics.o itable.o misc.o \
sim-engine.o \
sim-calls.o \
sim-hload.o \
sim-hrw.o \
sim-reason.o \
sim-resume.o \
sim-run.o \
sim-stop.o \
# List of extra dependencies.
# Generally this consists of simulator specific files included by sim-main.h.
SIM_EXTRA_DEPS = itable.h idecode.h cpu.h alu.h
# List of extra libraries to link with
SIM_EXTRA_LIBS = -lm
# List of generators
SIM_GEN=tmp-igen
# List of flags to always pass to $(CC).
SIM_EXTRA_CFLAGS = \
-DWITH_TARGET_WORD_MSB=31
# List of main object files for `run'.
SIM_RUN_OBJS = nrun.o
# Dependency of `clean' to clean any extra files.
SIM_EXTRA_CLEAN = clean-igen
## COMMON_POST_CONFIG_FRAG
# Rules need to build $(SIM_OBJS), plus whatever else the target wants.
# ... target specific rules ...
BUILT_SRC_FROM_IGEN = \
icache.h \
icache.c \
idecode.h \
idecode.c \
semantics.h \
semantics.c \
model.h \
model.c \
support.h \
support.c \
itable.h itable.c
$(BUILT_SRC_FROM_IGEN): tmp-igen
#
.PHONY: clean-igen
clean-igen:
rm -f $(BUILT_SRC_FROM_IGEN)
rm -f tmp-igen tmp-insns
../igen/igen:
cd ../igen && $(MAKE)
tmp-igen: $(srcdir)/tic80.dc $(srcdir)/tic80.igen $(srcdir)/tic80.ic ../igen/igen
cd ../igen && $(MAKE)
../igen/igen \
-F f \
-G direct-access \
-G delayed-branch \
-G zero-r0 \
-F short,emul \
-B 32 -H 31 \
-o $(srcdir)/tic80.dc \
-k $(srcdir)/tic80.ic \
-i $(srcdir)/tic80.igen \
-n icache.h -hc tmp-icache.h \
-n icache.c -c tmp-icache.c \
-n semantics.h -hs tmp-semantics.h \
-n semantics.c -s tmp-semantics.c \
-n idecode.h -hd tmp-idecode.h \
-n idecode.c -d tmp-idecode.c \
-n model.h -hm tmp-model.h \
-n model.c -m tmp-model.c \
-n support.h -hf tmp-support.h \
-n support.c -f tmp-support.c \
-n itable.h -ht tmp-itable.h \
-n itable.c -t tmp-itable.c
$(srcdir)/../../move-if-change tmp-icache.h icache.h
$(srcdir)/../../move-if-change tmp-icache.c icache.c
$(srcdir)/../../move-if-change tmp-idecode.h idecode.h
$(srcdir)/../../move-if-change tmp-idecode.c idecode.c
$(srcdir)/../../move-if-change tmp-semantics.h semantics.h
$(srcdir)/../../move-if-change tmp-semantics.c semantics.c
$(srcdir)/../../move-if-change tmp-model.h model.h
$(srcdir)/../../move-if-change tmp-model.c model.c
$(srcdir)/../../move-if-change tmp-support.h support.h
$(srcdir)/../../move-if-change tmp-support.c support.c
$(srcdir)/../../move-if-change tmp-itable.h itable.h
$(srcdir)/../../move-if-change tmp-itable.c itable.c
touch tmp-igen
ENGINE_H = \
sim-main.h \
$(srcdir)/../common/sim-basics.h \
config.h \
$(srcdir)/../common/sim-config.h \
$(srcdir)/../common/sim-inline.h \
$(srcdir)/../common/sim-types.h \
$(srcdir)/../common/sim-bits.h \
$(srcdir)/../common/sim-endian.h \
$(srcdir)/../common/sim-options.h \
itable.h \
idecode.h \
cpu.h \
alu.h \
$(srcdir)/../common/sim-alu.h \
$(srcdir)/../common/sim-core.h \
$(srcdir)/../common/sim-events.h \
$(srcdir)/../common/sim-fpu.h \
$(srcdir)/../common/sim-engine.h \
idecode.o: $(ENGINE_H)
semantics.o: $(ENGINE_H)
support.o: $(ENGINE_H)
interp.o: interp.c $(ENGINE_H)
sim-calls.o: sim-calls.c $(ENGINE_H)
cpu.o: cpu.c $(ENGINE_H)
misc.o: $(ENGINE_H)

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sim/tic80/acconfig.h
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/* Define to 1 if NLS is requested. */
#undef ENABLE_NLS
/* Define as 1 if you have catgets and don't want to use GNU gettext. */
#undef HAVE_CATGETS
/* Define as 1 if you have gettext and don't want to use GNU gettext. */
#undef HAVE_GETTEXT
/* Define as 1 if you have the stpcpy function. */
#undef HAVE_STPCPY
/* Define if your locale.h file contains LC_MESSAGES. */
#undef HAVE_LC_MESSAGES

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sim/tic80/alu.h
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/* Texas Instruments TMS320C80 (MVP) Simulator.
Copyright (C) 1997 Free Software Foundation, Inc.
Contributed by Cygnus Support.
This file is part of GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#ifndef _TIC80_ALU_H_
#define _TIC80_ALU_H_
#define ALU_CARRY 0 /* FIXME */
#define ALU32_END(TARG) \
{ \
(TARG) = ALU32_RESULT; /* FIXME */ \
}
#define ALU_END(TARG) ALU32_END(TARG)
#include "sim-alu.h"
/* Bring data in from the cold */
#define IMEM32(CIA) \
(sim_core_read_aligned_4(STATE_CPU (sd, 0), CIA, exec_map, (CIA).ip))
#define IMEM32_IMMED(CIA, N) \
(sim_core_read_aligned_4 (STATE_CPU (sd, 0), CIA, exec_map, (CIA).ip + 4 * (N)))
#define MEM(SIGN, EA, NR_BYTES) \
((SIGN##_##NR_BYTES) sim_core_read_unaligned_##NR_BYTES (STATE_CPU (sd, 0), cia, \
read_map, \
(EA)))
#define STORE(EA, NR_BYTES, VAL) \
do { \
sim_core_write_unaligned_##NR_BYTES (STATE_CPU (sd, 0), cia, \
write_map, \
(EA), (VAL)); \
} while (0)
#define long_immediate(VARIABLE) \
unsigned_word VARIABLE = MEM (unsigned, nia.ip, 4); \
cia.dp += sizeof (instruction_word); \
nia.ip += sizeof (instruction_word); \
nia.dp += sizeof (instruction_word);
/* Floating point support */
#define IS_FP_AVAILABLE ((CPU)->cr[IE_CR] & IE_CR_IE)
#include "sim-fpu.h"
#endif

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sim/tic80/config.in
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/* config.in. Generated automatically from configure.in by autoheader. */
/* Define if using alloca.c. */
#undef C_ALLOCA
/* Define to empty if the keyword does not work. */
#undef const
/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems.
This function is required for alloca.c support on those systems. */
#undef CRAY_STACKSEG_END
/* Define if you have alloca, as a function or macro. */
#undef HAVE_ALLOCA
/* Define if you have <alloca.h> and it should be used (not on Ultrix). */
#undef HAVE_ALLOCA_H
/* Define if you have a working `mmap' system call. */
#undef HAVE_MMAP
/* Define as __inline if that's what the C compiler calls it. */
#undef inline
/* Define to `long' if <sys/types.h> doesn't define. */
#undef off_t
/* Define if you need to in order for stat and other things to work. */
#undef _POSIX_SOURCE
/* Define as the return type of signal handlers (int or void). */
#undef RETSIGTYPE
/* Define to `unsigned' if <sys/types.h> doesn't define. */
#undef size_t
/* If using the C implementation of alloca, define if you know the
direction of stack growth for your system; otherwise it will be
automatically deduced at run-time.
STACK_DIRECTION > 0 => grows toward higher addresses
STACK_DIRECTION < 0 => grows toward lower addresses
STACK_DIRECTION = 0 => direction of growth unknown
*/
#undef STACK_DIRECTION
/* Define if you have the ANSI C header files. */
#undef STDC_HEADERS
/* Define if your processor stores words with the most significant
byte first (like Motorola and SPARC, unlike Intel and VAX). */
#undef WORDS_BIGENDIAN
/* Define to 1 if NLS is requested. */
#undef ENABLE_NLS
/* Define as 1 if you have gettext and don't want to use GNU gettext. */
#undef HAVE_GETTEXT
/* Define as 1 if you have the stpcpy function. */
#undef HAVE_STPCPY
/* Define if your locale.h file contains LC_MESSAGES. */
#undef HAVE_LC_MESSAGES
/* Define if you have the __argz_count function. */
#undef HAVE___ARGZ_COUNT
/* Define if you have the __argz_next function. */
#undef HAVE___ARGZ_NEXT
/* Define if you have the __argz_stringify function. */
#undef HAVE___ARGZ_STRINGIFY
/* Define if you have the __setfpucw function. */
#undef HAVE___SETFPUCW
/* Define if you have the dcgettext function. */
#undef HAVE_DCGETTEXT
/* Define if you have the getcwd function. */
#undef HAVE_GETCWD
/* Define if you have the getpagesize function. */
#undef HAVE_GETPAGESIZE
/* Define if you have the getpid function. */
#undef HAVE_GETPID
/* Define if you have the getrusage function. */
#undef HAVE_GETRUSAGE
/* Define if you have the kill function. */
#undef HAVE_KILL
/* Define if you have the munmap function. */
#undef HAVE_MUNMAP
/* Define if you have the putenv function. */
#undef HAVE_PUTENV
/* Define if you have the setenv function. */
#undef HAVE_SETENV
/* Define if you have the setlocale function. */
#undef HAVE_SETLOCALE
/* Define if you have the sigaction function. */
#undef HAVE_SIGACTION
/* Define if you have the stpcpy function. */
#undef HAVE_STPCPY
/* Define if you have the strcasecmp function. */
#undef HAVE_STRCASECMP
/* Define if you have the strchr function. */
#undef HAVE_STRCHR
/* Define if you have the time function. */
#undef HAVE_TIME
/* Define if you have the <argz.h> header file. */
#undef HAVE_ARGZ_H
/* Define if you have the <fcntl.h> header file. */
#undef HAVE_FCNTL_H
/* Define if you have the <fpu_control.h> header file. */
#undef HAVE_FPU_CONTROL_H
/* Define if you have the <limits.h> header file. */
#undef HAVE_LIMITS_H
/* Define if you have the <locale.h> header file. */
#undef HAVE_LOCALE_H
/* Define if you have the <malloc.h> header file. */
#undef HAVE_MALLOC_H
/* Define if you have the <nl_types.h> header file. */
#undef HAVE_NL_TYPES_H
/* Define if you have the <stdlib.h> header file. */
#undef HAVE_STDLIB_H
/* Define if you have the <string.h> header file. */
#undef HAVE_STRING_H
/* Define if you have the <strings.h> header file. */
#undef HAVE_STRINGS_H
/* Define if you have the <sys/param.h> header file. */
#undef HAVE_SYS_PARAM_H
/* Define if you have the <sys/resource.h> header file. */
#undef HAVE_SYS_RESOURCE_H
/* Define if you have the <sys/time.h> header file. */
#undef HAVE_SYS_TIME_H
/* Define if you have the <time.h> header file. */
#undef HAVE_TIME_H
/* Define if you have the <unistd.h> header file. */
#undef HAVE_UNISTD_H
/* Define if you have the <values.h> header file. */
#undef HAVE_VALUES_H

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sim/tic80/configure vendored
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sim/tic80/configure.in
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dnl Process this file with autoconf to produce a configure script.
sinclude(../common/aclocal.m4)
AC_PREREQ(2.5)dnl
AC_INIT(Makefile.in)
SIM_AC_COMMON
dnl Options available in this module
SIM_AC_OPTION_INLINE(0)
SIM_AC_OPTION_ENDIAN(LITTLE_ENDIAN)
SIM_AC_OPTION_ALIGNMENT(FORCED_ALIGNMENT)
SIM_AC_OPTION_HOSTENDIAN
SIM_AC_OPTION_WARNINGS
SIM_AC_OPTION_RESERVED_BITS(1)
SIM_AC_OPTION_BITSIZE(32,31)
dnl For UNIX emulation
AC_CHECK_HEADERS(stdlib.h unistd.h string.h strings.h)
AC_CHECK_FUNCS(getpid kill)
SIM_AC_OUTPUT

345
sim/tic80/cpu.h
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/* TIc80 Simulator.
Copyright (C) 1997, 1998 Free Software Foundation, Inc.
Contributed by Cygnus Support.
This file is part of GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
/* TI C80 control registers */
typedef enum {
EPC_CR,
EIP_CR,
CONFIG_CR,
INTPEN_CR,
IE_CR,
FPST_CR,
PPERROR_CR,
PKTREQ_CR,
TCOUNT_CR,
TSCALE_CR,
FLTOP_CR,
FLTADR_CR,
FLTTAG_CR,
FLTDLT_CR,
FLTDTH_CR,
FLT005_CR,
FLT006_CR,
FLT007_CR,
FLT008_CR,
FLT009_CR,
FLT010_CR,
FLT011_CR,
FLT012_CR,
FLT013_CR,
FLT014_CR,
FLT015_CR,
SYSSTK_CR,
SYSTMP_CR,
MPC_CR,
MIP_CR,
ECOMCNTL_CR,
ANASTAT_CR,
BRK1_CR,
BRK2_CR,
ITAG0_CR,
ITAG1_CR,
ITAG2_CR,
ITAG3_CR,
ITAG4_CR,
ITAG5_CR,
ITAG6_CR,
ITAG7_CR,
ITAG8_CR,
ITAG9_CR,
ITAG10_CR,
ITAG11_CR,
ITAG12_CR,
ITAG13_CR,
ITAG14_CR,
ITAG15_CR,
ILRU_CR,
DTAG0_CR,
DTAG1_CR,
DTAG2_CR,
DTAG3_CR,
DTAG4_CR,
DTAG5_CR,
DTAG6_CR,
DTAG7_CR,
DTAG8_CR,
DTAG9_CR,
DTAG10_CR,
DTAG11_CR,
DTAG12_CR,
DTAG13_CR,
DTAG14_CR,
DTAG15_CR,
DLRU_CR,
IN0P_CR,
IN1P_CR,
OUTP_CR,
SCRATCH_CR,
nr_tic80_control_regs,
} tic80_control_regs;
/* extern int tic80_cr2index (tic80_control_regs reg); */
/* Map an instruction CR index onto the corresponding internal cr enum
or SCRATCH_CR if the index is invalid */
extern tic80_control_regs tic80_index2cr (int index);
/* TIc80 interrupt register bits */
enum {
IE_CR_PE = BIT32(31),
IE_CR_X4 = BIT32(30),
IE_CR_X3 = BIT32(29),
IE_CR_BP = BIT32(28),
IE_CR_PB = BIT32(27),
IE_CR_PC = BIT32(26),
IE_CR_MI = BIT32(25),
/**/
IE_CR_P3 = BIT32(19),
IE_CR_P2 = BIT32(18),
IE_CR_P1 = BIT32(17),
IE_CR_P0 = BIT32(16),
IE_CR_IO = BIT32(15),
IE_CR_MF = BIT32(14),
/**/
IE_CR_X2 = BIT32(12),
IE_CR_X1 = BIT32(11),
IE_CR_TI = BIT32(10),
IE_CR_F1 = BIT32(9),
IE_CR_F0 = BIT32(8),
IE_CR_FX = BIT32(7),
IE_CR_FU = BIT32(6),
IE_CR_FO = BIT32(5),
/**/
IE_CR_FZ = BIT32(3),
IE_CR_FI = BIT32(2),
/**/
IE_CR_IE = BIT32(0),
};
struct _sim_cpu {
unsigned32 reg[32];
unsigned64 acc[4];
unsigned32 cr[nr_tic80_control_regs];
int is_user_mode; /* hidden mode latch */
sim_cia cia;
sim_cpu_base base;
};
#define CIA_GET(CPU) ((CPU)->cia)
#define CIA_SET(CPU,VAL) ((CPU)->cia = (VAL))
#define GPR(N) ((CPU)->reg[N])
#define GPR_CLEAR(N) (GPR((N)) = 0)
#define ACC(N) ((CPU)->acc[N])
#define CR(N) ((CPU)->cr[tic80_index2cr ((N))])
#if defined(WITH_TRACE)
extern char *tic80_trace_alu3 PARAMS ((int, unsigned32, unsigned32, unsigned32));
extern char *tic80_trace_cmp PARAMS ((int, unsigned32, unsigned32, unsigned32));
extern char *tic80_trace_alu2 PARAMS ((int, unsigned32, unsigned32));
extern char *tic80_trace_shift PARAMS ((int, unsigned32, unsigned32, int, int, int, int, int));
extern void tic80_trace_fpu3 PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, sim_fpu *, sim_fpu *, sim_fpu *));
extern void tic80_trace_fpu2 PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, sim_fpu *, sim_fpu *));
extern void tic80_trace_fpu1 PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, sim_fpu *));
extern void tic80_trace_fpu2i PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, unsigned32, sim_fpu *, sim_fpu *));
extern void tic80_trace_fpu2cmp PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, unsigned32, sim_fpu *, sim_fpu *));
extern char *tic80_trace_nop PARAMS ((int));
extern char *tic80_trace_sink1 PARAMS ((int, unsigned32));
extern char *tic80_trace_sink2 PARAMS ((int, unsigned32, unsigned32));
extern char *tic80_trace_sink3 PARAMS ((int, unsigned32, unsigned32, unsigned32));
extern char *tic80_trace_cond_br PARAMS ((int, int, unsigned32, unsigned32, int, int));
extern char *tic80_trace_ucond_br PARAMS ((int, unsigned32));
extern void tic80_trace_ldst PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, int, int, int, unsigned32, unsigned32, unsigned32));
#define TRACE_ALU3(indx, result, input1, input2) \
do { \
if (TRACE_ALU_P (CPU)) { \
trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
itable[indx].line_nr, "alu", \
tic80_trace_alu3 (indx, result, input1, input2)); \
} \
} while (0)
#define TRACE_CMP(indx, result, input1, input2) \
do { \
if (TRACE_ALU_P (CPU)) { \
trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
itable[indx].line_nr, "alu", \
tic80_trace_cmp (indx, result, input1, input2)); \
} \
} while (0)
#define TRACE_ALU2(indx, result, input) \
do { \
if (TRACE_ALU_P (CPU)) { \
trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
itable[indx].line_nr, "alu", \
tic80_trace_alu2 (indx, result, input)); \
} \
} while (0)
#define TRACE_SHIFT(indx, result, input, i, n, merge, endmask, rotate) \
do { \
if (TRACE_ALU_P (CPU)) { \
trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
itable[indx].line_nr, "shift", \
tic80_trace_shift (indx, result, input, i, n, \
merge, endmask, rotate)); \
} \
} while (0)
#define TRACE_FPU3(result, input1, input2) \
do { \
if (TRACE_FPU_P (CPU)) { \
tic80_trace_fpu3 (SD, CPU, cia, MY_INDEX, \
&result, &input1, &input2); \
} \
} while (0)
#define TRACE_FPU2(result, input) \
do { \
if (TRACE_FPU_P (CPU)) { \
tic80_trace_fpu2 (SD, CPU, cia, MY_INDEX, \
&result, &input); \
} \
} while (0)
#define TRACE_FPU1(result) \
do { \
if (TRACE_FPU_P (CPU)) { \
tic80_trace_fpu1 (SD, CPU, cia, MY_INDEX, \
&result); \
} \
} while (0)
#define TRACE_FPU2I(result, input1, input2) \
do { \
if (TRACE_FPU_P (CPU)) { \
tic80_trace_fpu2i (SD, CPU, cia, MY_INDEX, \
result, &input1, &input2); \
} \
} while (0)
#define TRACE_FPU2CMP(result, input1, input2) \
do { \
if (TRACE_FPU_P (CPU)) { \
tic80_trace_fpu2cmp (SD, CPU, cia, MY_INDEX, \
result, &input1, &input2); \
} \
} while (0)
#define TRACE_NOP(indx) \
do { \
if (TRACE_ALU_P (CPU)) { \
trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
itable[indx].line_nr, "nop", \
tic80_trace_nop (indx)); \
} \
} while (0)
#define TRACE_SINK1(indx, input) \
do { \
if (TRACE_ALU_P (CPU)) { \
trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
itable[indx].line_nr, "nop", \
tic80_trace_sink1 (indx, input)); \
} \
} while (0)
#define TRACE_SINK2(indx, input1, input2) \
do { \
if (TRACE_ALU_P (CPU)) { \
trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
itable[indx].line_nr, "nop", \
tic80_trace_sink2 (indx, input1, input2)); \
} \
} while (0)
#define TRACE_SINK3(indx, input1, input2, input3) \
do { \
if (TRACE_ALU_P (CPU)) { \
trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
itable[indx].line_nr, "nop", \
tic80_trace_sink3 (indx, input1, input2, input3)); \
} \
} while (0)
#define TRACE_COND_BR(indx, jump_p, cond, target, size, code) \
do { \
if (TRACE_BRANCH_P (CPU)) { \
trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
itable[indx].line_nr, "branch", \
tic80_trace_cond_br (indx, jump_p, cond, target, \
size, code)); \
} \
} while (0)
#define TRACE_UCOND_BR(indx, target) \
do { \
if (TRACE_BRANCH_P (CPU)) { \
trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
itable[indx].line_nr, "branch", \
tic80_trace_ucond_br (indx, target)); \
} \
} while (0)
#define TRACE_LD(result, m, s, addr1, addr2) \
do { \
if (TRACE_MEMORY_P (CPU)) { \
tic80_trace_ldst (SD, CPU, cia, MY_INDEX, \
0, m, s, result, addr1, addr2); \
} \
} while (0)
#define TRACE_ST(value, m, s, addr1, addr2) \
do { \
if (TRACE_MEMORY_P (CPU)) { \
tic80_trace_ldst (SD, CPU, cia, MY_INDEX, \
1, m, s, value, addr1, addr2); \
} \
} while (0)
#else
#define TRACE_ALU3(indx, result, input1, input2)
#define TRACE_ALU2(indx, result, input)
#define TRACE_FPU3(result, input1, input2)
#define TRACE_FPU2(result, input)
#define TRACE_FPU1(result)
#define TRACE_FPU2I(result, input1, input2)
#define TRACE_NOP(indx)
#define TRACE_SINK1(indx, input)
#define TRACE_SINK2(indx, input1, input2)
#define TRACE_SINK3(indx, input1, input2, input3)
#define TRACE_COND_BR(indx, jump_p, cond, target, size, code)
#define TRACE_UCOND_BR(indx, target)
#define TRACE_LD(m, s, result, addr1, addr2)
#define TRACE_ST(m, s, value, addr1, addr2)
#endif

127
sim/tic80/interp.c
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@ -1,127 +0,0 @@
/* This file is part of the GDB simulators.
Copyright (C) 1997, Free Software Foundation
Condtributed by Cyngnus Solutions.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include "sim-main.h"
#include "idecode.h"
#include "itable.h"
#ifdef HAVE_STRING_H
#include <string.h>
#else
#ifdef HAVE_STRINGS_H
#include <strings.h>
#endif
#endif
#if 0
void
engine_error (SIM_DESC sd,
sim_cpu *cpu,
instruction_address cia,
const char *fmt,
...)
{
va_list ap;
va_start (ap, fmt);
sim_io_evprintf (sd, fmt, ap);
va_end (ap);
sim_halt (sd, cpu, NULL, cia, sim_stopped, SIGABRT);
}
void
engine_halt (SIM_DESC sd,
sim_cpu *cpu,
instruction_address cia,
enum sim_stop reason,
int siggnal)
{
if (!sd->halt_ok)
sim_io_error (sd, "engine_halt - bad longjmp");
sd->reason = reason;
sd->siggnal = siggnal;
sd->halt_ok = 0;
sd->restart_ok = 0;
if (cpu != NULL)
cpu->cia = cia;
longjmp (sd->path_to_halt, 1);
}
void
engine_restart (SIM_DESC sd,
sim_cpu *cpu,
instruction_address cia)
{
if (!sd->restart_ok)
sim_io_error (sd, "engine_restart - bad longjmp");
sd->restart_ok = 0;
cpu->cia = cia;
longjmp(sd->path_to_restart, 1);
}
void
engine_run_until_stop (SIM_DESC sd,
volatile int *keep_running)
{
if (!setjmp (sd->path_to_halt))
{
instruction_address cia;
sim_cpu *cpu = STATE_CPU (sd, 0);
sd->halt_ok = 1;
setjmp (sd->path_to_restart);
sd->restart_ok = 1;
cia = cpu->cia;
do
{
instruction_word insn = IMEM (cia);
cia = idecode_issue (sd, insn, cia);
}
while (*keep_running);
engine_halt (sd, cpu, cia, sim_stopped, SIM_SIGINT);
}
}
void
engine_step (SIM_DESC sd)
{
if (!setjmp (sd->path_to_halt))
{
instruction_address cia;
instruction_word insn;
sim_cpu *cpu = STATE_CPU (sd, 0);
sd->halt_ok = 1;
setjmp (sd->path_to_restart);
sd->restart_ok = 1;
cia = cpu->cia;
insn = IMEM (cia);
cia = idecode_issue (sd, insn, cia);
engine_halt (sd, cpu, cia, sim_stopped, SIM_SIGTRAP);
}
}
#endif

624
sim/tic80/misc.c
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@ -1,624 +0,0 @@
/* TIc80 Simulator.
Copyright (C) 1997, 1998 Free Software Foundation, Inc.
Contributed by Cygnus Support.
This file is part of GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "sim-main.h"
#ifdef HAVE_STRING_H
#include <string.h>
#else
#ifdef HAVE_STRINGS_H
#include <strings.h>
#endif
#endif
tic80_control_regs
tic80_index2cr (int index)
{
switch (index)
{
case 0x0000: return EPC_CR;
case 0x0001: return EIP_CR;
case 0x0002: return CONFIG_CR;
case 0x0004: return INTPEN_CR;
case 0x0006: return IE_CR;
case 0x0008: return FPST_CR;
case 0x000A: return PPERROR_CR;
case 0x000D: return PKTREQ_CR;
case 0x000E: return TCOUNT_CR;
case 0x000F: return TSCALE_CR;
case 0x0010: return FLTOP_CR;
case 0x0011: return FLTADR_CR;
case 0x0012: return FLTTAG_CR;
case 0x0013: return FLTDLT_CR;
case 0x0014: return FLTDTH_CR;
case 0x0015: return FLT005_CR;
case 0x0016: return FLT006_CR;
case 0x0017: return FLT007_CR;
case 0x0018: return FLT008_CR;
case 0x0019: return FLT009_CR;
case 0x001a: return FLT010_CR;
case 0x001b: return FLT011_CR;
case 0x001c: return FLT012_CR;
case 0x001d: return FLT013_CR;
case 0x001e: return FLT014_CR;
case 0x001f: return FLT015_CR;
case 0x0020: return SYSSTK_CR;
case 0x0021: return SYSTMP_CR;
case 0x0030: return MPC_CR;
case 0x0031: return MIP_CR;
case 0x0033: return ECOMCNTL_CR;
case 0x0034: return ANASTAT_CR;
case 0x0039: return BRK1_CR;
case 0x003A: return BRK2_CR;
case 0x0200: return ITAG0_CR;
case 0x0201: return ITAG1_CR;
case 0x0202: return ITAG2_CR;
case 0x0203: return ITAG3_CR;
case 0x0204: return ITAG4_CR;
case 0x0205: return ITAG5_CR;
case 0x0206: return ITAG6_CR;
case 0x0207: return ITAG7_CR;
case 0x0208: return ITAG8_CR;
case 0x0209: return ITAG9_CR;
case 0x020a: return ITAG10_CR;
case 0x020b: return ITAG11_CR;
case 0x020c: return ITAG12_CR;
case 0x020d: return ITAG13_CR;
case 0x020e: return ITAG14_CR;
case 0x020f: return ITAG15_CR;
case 0x0300: return ILRU_CR;
case 0x0400: return DTAG0_CR;
case 0x0401: return DTAG1_CR;
case 0x0402: return DTAG2_CR;
case 0x0403: return DTAG3_CR;
case 0x0404: return DTAG4_CR;
case 0x0405: return DTAG5_CR;
case 0x0406: return DTAG6_CR;
case 0x0407: return DTAG7_CR;
case 0x0408: return DTAG8_CR;
case 0x0409: return DTAG9_CR;
case 0x040a: return DTAG10_CR;
case 0x040b: return DTAG11_CR;
case 0x040c: return DTAG12_CR;
case 0x040d: return DTAG13_CR;
case 0x040e: return DTAG14_CR;
case 0x040f: return DTAG15_CR;
case 0x0500: return DLRU_CR;
case 0x4000: return IN0P_CR;
case 0x4001: return IN1P_CR;
case 0x4002: return OUTP_CR;
default: return SCRATCH_CR;
}
}
#if defined(WITH_TRACE)
/* Tracing support routines */
static char tic80_trace_buffer[1024];
static int tic80_size_name;
#define SIZE_HEX 8
#define SIZE_DECIMAL 11
/* Initialize tracing by calculating the maximum name size */
static void
tic80_init_trace (void)
{
int i;
int len, max_len = 0;
for (i = 0; i < (int)nr_itable_entries; i++) {
len = strlen (itable[i].name);
if (len > max_len)
max_len = len;
}
tic80_size_name = max_len + sizeof(":m") - 1 + sizeof (":s") - 1;
}
/* Given an integer which is the result of a comparison, return a string
giving which bits are set. */
static char *
tic80_trace_cmp_internal (unsigned32 flag)
{
struct cmp_bits { unsigned32 bit; char *string; };
static char buffer[32*8];
static struct cmp_bits bits[] =
{
{ BIT32(29), "hs" },
{ BIT32(28), "lo" },
{ BIT32(27), "ls" },
{ BIT32(26), "hi" },
{ BIT32(25), "ge" },
{ BIT32(24), "lt" },
{ BIT32(23), "le" },
{ BIT32(22), "gt" },
{ BIT32(21), "ne" },
{ BIT32(20), "eq" },
{ BIT32(19), "hs.h" },
{ BIT32(18), "lo.h" },
{ BIT32(17), "ls.h" },
{ BIT32(16), "hi.h" },
{ BIT32(15), "ge.h" },
{ BIT32(14), "lt.h" },
{ BIT32(13), "le.h" },
{ BIT32(12), "gt.h" },
{ BIT32(11), "ne.h" },
{ BIT32(10), "eq.h" },
{ BIT32( 9), "hs.b" },
{ BIT32( 8), "lo.b" },
{ BIT32( 7), "ls.b" },
{ BIT32( 6), "hi.b" },
{ BIT32( 5), "ge.b" },
{ BIT32( 4), "lt.b" },
{ BIT32( 3), "le.b" },
{ BIT32( 2), "gt.b" },
{ BIT32( 1), "ne.b" },
{ BIT32( 0), "eq.b" },
{ 0, (char *)0 },
};
int i;
char *p = buffer;
for (i = 0; bits[i].bit != 0; i++)
{
if ((flag & bits[i].bit) != 0)
{
if (p != buffer)
*p++ = ' ';
strcpy (p, bits[i].string);
p += strlen (p);
}
}
*p = '\0';
return buffer;
}
/* Trace the result of an ALU operation with 2 integer inputs and an integer output */
char *
tic80_trace_alu3 (int indx,
unsigned32 result,
unsigned32 input1,
unsigned32 input2)
{
if (!tic80_size_name)
tic80_init_trace ();
sprintf (tic80_trace_buffer, "%-*s 0x%.*lx/%*ld 0x%.*lx/%*ld => 0x%.*lx/%*ld",
tic80_size_name, itable[indx].name,
SIZE_HEX, input1, SIZE_DECIMAL, (long)(signed32)input1,
SIZE_HEX, input2, SIZE_DECIMAL, (long)(signed32)input2,
SIZE_HEX, result, SIZE_DECIMAL, (long)(signed32)result);
return tic80_trace_buffer;
}
/* Trace the result of an ALU operation with 2 integer inputs and an integer output
that sets the bits from a compare instruction. */
char *
tic80_trace_cmp (int indx,
unsigned32 result,
unsigned32 input1,
unsigned32 input2)
{
if (!tic80_size_name)
tic80_init_trace ();
sprintf (tic80_trace_buffer, "%-*s 0x%.*lx/%*ld 0x%.*lx/%*ld => 0x%.*lx %s",
tic80_size_name, itable[indx].name,
SIZE_HEX, input1, SIZE_DECIMAL, (long)(signed32)input1,
SIZE_HEX, input2, SIZE_DECIMAL, (long)(signed32)input2,
SIZE_HEX, result, tic80_trace_cmp_internal (result));
return tic80_trace_buffer;
}
/* Trace the result of an ALU operation with 1 integer input and an integer output */
char *
tic80_trace_alu2 (int indx,
unsigned32 result,
unsigned32 input)
{
if (!tic80_size_name)
tic80_init_trace ();
sprintf (tic80_trace_buffer, "%-*s 0x%.*lx/%*ld %*s => 0x%.*lx/%*ld",
tic80_size_name, itable[indx].name,
SIZE_HEX, input, SIZE_DECIMAL, (long)(signed32)input,
SIZE_HEX + SIZE_DECIMAL + 3, "",
SIZE_HEX, result, SIZE_DECIMAL, (long)(signed32)result);
return tic80_trace_buffer;
}
/* Trace the result of a shift instruction */
char *
tic80_trace_shift (int indx,
unsigned32 result,
unsigned32 input,
int i,
int n,
int merge,
int endmask,
int rotate)
{
const char *merge_name;
char name[40];
char *p;
if (!tic80_size_name)
tic80_init_trace ();
switch (merge)
{
default: merge_name = ".??"; break;
case 0: merge_name = ".dz"; break;
case 1: merge_name = ".dm"; break;
case 2: merge_name = ".ds"; break;
case 3: merge_name = ".ez"; break;
case 4: merge_name = ".em"; break;
case 5: merge_name = ".es"; break;
case 6: merge_name = ".iz"; break;
case 7: merge_name = ".im"; break;
}
/* Don't use itable[indx].name, which is just sl {r,i}. Instead reconstruct
the name, using the i and n fields. */
p = strchr (itable[indx].name, ' ');
sprintf (name, "s%s%s%s%s",
(n) ? "r" : "l",
(i) ? "i" : "",
merge_name,
(p) ? p : "");
sprintf (tic80_trace_buffer, "%-*s 0x%.*lx/%*ld %*s%2d,%2d => 0x%.*lx/%*ld",
tic80_size_name, name,
SIZE_HEX, input, SIZE_DECIMAL, (long)(signed32)input,
SIZE_HEX + SIZE_DECIMAL - 2, "",
rotate, endmask,
SIZE_HEX, result, SIZE_DECIMAL, (long)(signed32)result);
return tic80_trace_buffer;
}
/* Trace the result of an FPU operation with 2 floating point inputs and a floating point output */
void
tic80_trace_fpu3 (SIM_DESC sd,
sim_cpu *cpu,
sim_cia cia,
int indx,
sim_fpu *result,
sim_fpu *input1,
sim_fpu *input2)
{
if (!tic80_size_name)
tic80_init_trace ();
trace_one_insn (sd, cpu, cia.ip, 1,
itable[indx].file, itable[indx].line_nr, "fpu",
"%-*s %*g %*g => %*g",
tic80_size_name, itable[indx].name,
SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (input1),
SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (input2),
SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (result));
}
/* Trace the result of an FPU operation with 1 floating point input and a floating point output */
void
tic80_trace_fpu2 (SIM_DESC sd,
sim_cpu *cpu,
sim_cia cia,
int indx,
sim_fpu *result,
sim_fpu *input)
{
if (!tic80_size_name)
tic80_init_trace ();
trace_one_insn (sd, cpu, cia.ip, 1,
itable[indx].file, itable[indx].line_nr, "fpu",
"%-*s %*g %-*s => %*g",
tic80_size_name, itable[indx].name,
SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (input),
SIZE_HEX + SIZE_DECIMAL + 3, "",
SIZE_HEX + SIZE_DECIMAL, sim_fpu_2d (result));
}
/* Trace the result of an FPU operation with 1 floating point input and a floating point output */
void
tic80_trace_fpu1 (SIM_DESC sd,
sim_cpu *cpu,
sim_cia cia,
int indx,
sim_fpu *result)
{
if (!tic80_size_name)
tic80_init_trace ();
trace_one_insn (sd, cpu, cia.ip, 1,
itable[indx].file, itable[indx].line_nr, "fpu",
"%-*s %-*s %-*s => %*g",
tic80_size_name, itable[indx].name,
SIZE_HEX + SIZE_DECIMAL + 3, "",
SIZE_HEX + SIZE_DECIMAL + 3, "",
SIZE_HEX + SIZE_DECIMAL, sim_fpu_2d (result));
}
/* Trace the result of an FPU operation with 2 floating point inputs and an integer output */
void
tic80_trace_fpu2i (SIM_DESC sd,
sim_cpu *cpu,
sim_cia cia,
int indx,
unsigned32 result,
sim_fpu *input1,
sim_fpu *input2)
{
if (!tic80_size_name)
tic80_init_trace ();
trace_one_insn (sd, cpu, cia.ip, 1,
itable[indx].file, itable[indx].line_nr, "fpu",
"%-*s %*g %*g => 0x%.*lx %-*ld",
tic80_size_name, itable[indx].name,
SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (input1),
SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (input2),
SIZE_HEX, result, SIZE_DECIMAL, (long)(signed32)result);
}
/* Trace the result of an FPU operation with 2 floating point inputs and an integer output
that is the result of a comparison. */
void
tic80_trace_fpu2cmp (SIM_DESC sd,
sim_cpu *cpu,
sim_cia cia,
int indx,
unsigned32 result,
sim_fpu *input1,
sim_fpu *input2)
{
if (!tic80_size_name)
tic80_init_trace ();
trace_one_insn (sd, cpu, cia.ip, 1,
itable[indx].file, itable[indx].line_nr, "fpu",
"%-*s %*g %*g => 0x%.*lx %s",
tic80_size_name, itable[indx].name,
SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (input1),
SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (input2),
SIZE_HEX, result, tic80_trace_cmp_internal (result));
}
/* Trace the result of a NOP operation */
char *
tic80_trace_nop (int indx)
{
if (!tic80_size_name)
tic80_init_trace ();
sprintf (tic80_trace_buffer, "%s", itable[indx].name);
return tic80_trace_buffer;
}
/* Trace the result of a data sink with one input */
char *
tic80_trace_sink1 (int indx, unsigned32 input)
{
if (!tic80_size_name)
tic80_init_trace ();
sprintf (tic80_trace_buffer, "%-*s 0x%.*lx/%*ld",
tic80_size_name, itable[indx].name,
SIZE_HEX, input, SIZE_DECIMAL, (long)(signed32)input);
return tic80_trace_buffer;
}
/* Trace the result of a data sink with two inputs */
char *
tic80_trace_sink2 (int indx, unsigned32 input1, unsigned32 input2)
{
if (!tic80_size_name)
tic80_init_trace ();
sprintf (tic80_trace_buffer, "%-*s 0x%.*lx/%*ld 0x%.*lx/%*ld",
tic80_size_name, itable[indx].name,
SIZE_HEX, input1, SIZE_DECIMAL, (long)(signed32)input1,
SIZE_HEX, input2, SIZE_DECIMAL, (long)(signed32)input2);
return tic80_trace_buffer;
}
/* Trace the result of a data sink with three inputs */
char *
tic80_trace_sink3 (int indx, unsigned32 input1, unsigned32 input2, unsigned32 input3)
{
if (!tic80_size_name)
tic80_init_trace ();
sprintf (tic80_trace_buffer, "%-*s 0x%.*lx/%*ld 0x%.*lx/%*ld 0x%.*lx/%*ld",
tic80_size_name, itable[indx].name,
SIZE_HEX, input1, SIZE_DECIMAL, (long)(signed32)input1,
SIZE_HEX, input2, SIZE_DECIMAL, (long)(signed32)input2,
SIZE_HEX, input3, SIZE_DECIMAL, (long)(signed32)input3);
return tic80_trace_buffer;
}
/* Trace the result of a conditional branch operation */
char *
tic80_trace_cond_br (int indx,
int jump_p,
unsigned32 cond,
unsigned32 target,
int size,
int code)
{
char *suffix1, *suffix2;
if (!tic80_size_name)
tic80_init_trace ();
if (size >= 0 && code >= 0)
{ /* BCND */
switch (code)
{
default: suffix1 = "???"; break;
case 0: suffix1 = "nev"; break;
case 1: suffix1 = "gt0"; break;
case 2: suffix1 = "eq0"; break;
case 3: suffix1 = "ge0"; break;
case 4: suffix1 = "lt0"; break;
case 5: suffix1 = "ne0"; break;
case 6: suffix1 = "le0"; break;
case 7: suffix1 = "alw"; break;
}
switch (size)
{
default: suffix2 = ".?"; break;
case 0: suffix2 = ".b"; break;
case 1: suffix2 = ".h"; break;
case 2: suffix2 = ".w"; break;
}
} else { /* BBO/BBZ */
suffix2 = "";
switch (cond)
{
default: suffix1 = "??.?"; break;
case 29: suffix1 = "hs.w"; break;
case 28: suffix1 = "lo.w"; break;
case 27: suffix1 = "ls.w"; break;
case 26: suffix1 = "hi.w"; break;
case 25: suffix1 = "ge.w"; break;
case 24: suffix1 = "lt.w"; break;
case 23: suffix1 = "le.w"; break;
case 22: suffix1 = "gt.w"; break;
case 21: suffix1 = "ne.w"; break;
case 20: suffix1 = "eq.w"; break;
case 19: suffix1 = "hs.h"; break;
case 18: suffix1 = "lo.h"; break;
case 17: suffix1 = "ls.h"; break;
case 16: suffix1 = "hi.h"; break;
case 15: suffix1 = "ge.h"; break;
case 14: suffix1 = "lt.h"; break;
case 13: suffix1 = "le.h"; break;
case 12: suffix1 = "gt.h"; break;
case 11: suffix1 = "ne.h"; break;
case 10: suffix1 = "eq.h"; break;
case 9: suffix1 = "hs.b"; break;
case 8: suffix1 = "lo.b"; break;
case 7: suffix1 = "ls.b"; break;
case 6: suffix1 = "hi.b"; break;
case 5: suffix1 = "ge.b"; break;
case 4: suffix1 = "lt.b"; break;
case 3: suffix1 = "le.b"; break;
case 2: suffix1 = "gt.b"; break;
case 1: suffix1 = "ne.b"; break;
case 0: suffix1 = "eq.b"; break;
}
}
if (jump_p)
sprintf (tic80_trace_buffer,
"%-*s 0x%.*lx %*s 0x%.*lx/%*ld => 0x%.*lx %s%s",
tic80_size_name, itable[indx].name,
SIZE_HEX, target, SIZE_DECIMAL, "",
SIZE_HEX, cond, SIZE_DECIMAL, (long)(signed32)cond,
SIZE_HEX, target,
suffix1, suffix2);
else
sprintf (tic80_trace_buffer,
"%-*s 0x%.*lx %*s 0x%.*lx/%*ld => %-*s %s%s",
tic80_size_name, itable[indx].name,
SIZE_HEX, target, SIZE_DECIMAL, "",
SIZE_HEX, cond, SIZE_DECIMAL, (long)(signed32)cond,
SIZE_HEX + 2, "[no jump]",
suffix1, suffix2);
return tic80_trace_buffer;
}
/* Trace the result of a unconditional branch operation */
char *
tic80_trace_ucond_br (int indx,
unsigned32 target)
{
if (!tic80_size_name)
tic80_init_trace ();
sprintf (tic80_trace_buffer,
"%-*s 0x%.*lx %*s => 0x%.*lx",
tic80_size_name, itable[indx].name,
SIZE_HEX, target, (SIZE_DECIMAL*2) + SIZE_HEX + 4, "",
SIZE_HEX, target);
return tic80_trace_buffer;
}
/* Trace the result of a load or store operation with 2 integer addresses
and an integer output or input */
void
tic80_trace_ldst (SIM_DESC sd,
sim_cpu *cpu,
sim_cia cia,
int indx,
int st_p,
int m_p,
int s_p,
unsigned32 value,
unsigned32 input1,
unsigned32 input2)
{
char name[40];
if (!tic80_size_name)
tic80_init_trace ();
strcpy (name, itable[indx].name);
if (m_p)
strcat (name, ":m");
if (s_p)
strcat (name, ":s");
trace_one_insn (sd, cpu, cia.ip, 1,
itable[indx].file, itable[indx].line_nr, "memory",
"%-*s 0x%.*lx/%*ld 0x%.*lx/%*ld %s 0x%.*lx/%*ld",
tic80_size_name, name,
SIZE_HEX, input1, SIZE_DECIMAL, (long)(signed32)input1,
SIZE_HEX, input2, SIZE_DECIMAL, (long)(signed32)input2,
(!st_p) ? "=>" : "<=",
SIZE_HEX, value, SIZE_DECIMAL, (long)(signed32)value);
}
#endif /* WITH_TRACE */

203
sim/tic80/sim-calls.c
View File

@ -1,203 +0,0 @@
/* This file is part of the program psim.
Copyright (C) 1994-1996, Andrew Cagney <cagney@highland.com.au>
Copyright (C) 1997, Free Software Foundation
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <stdarg.h>
#include <ctype.h>
#include "bfd.h"
#include "sim-main.h"
#include "sim-utils.h"
#include "sim-options.h"
#ifdef HAVE_STDLIB_H
#include <stdlib.h>
#endif
#ifdef HAVE_STRING_H
#include <string.h>
#else
#ifdef HAVE_STRINGS_H
#include <strings.h>
#endif
#endif
#define SIM_ADDR unsigned
SIM_DESC
sim_open (SIM_OPEN_KIND kind,
host_callback *callback,
struct _bfd *abfd,
char **argv)
{
char *buf;
SIM_DESC sd = sim_state_alloc (kind, callback);
if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
return 0;
#define TIC80_MEM_START 0x2000000
#define TIC80_MEM_SIZE 0x100000
/* main memory */
asprintf (&buf, "memory region 0x%lx,0x%lx",
TIC80_MEM_START, TIC80_MEM_SIZE);
sim_do_command (sd, buf);
free (buf);
/* interrupt memory */
sim_do_command (sd, "memory region 0x1010000,0x1000");
/* some memory at zero */
sim_do_command (sd, "memory region 0,0x100000");
/* getopt will print the error message so we just have to exit if this fails.
FIXME: Hmmm... in the case of gdb we need getopt to call
print_filtered. */
if (sim_parse_args (sd, argv) != SIM_RC_OK)
{
/* Uninstall the modules to avoid memory leaks,
file descriptor leaks, etc. */
sim_module_uninstall (sd);
return 0;
}
/* check for/establish the a reference program image */
if (sim_analyze_program (sd,
(STATE_PROG_ARGV (sd) != NULL
? *STATE_PROG_ARGV (sd)
: NULL),
abfd) != SIM_RC_OK)
{
sim_module_uninstall (sd);
return 0;
}
/* establish any remaining configuration options */
if (sim_config (sd) != SIM_RC_OK)
{
sim_module_uninstall (sd);
return 0;
}
if (sim_post_argv_init (sd) != SIM_RC_OK)
{
/* Uninstall the modules to avoid memory leaks,
file descriptor leaks, etc. */
sim_module_uninstall (sd);
return 0;
}
/* FIXME: for now */
return sd;
}
void
sim_close (SIM_DESC sd, int quitting)
{
/* Uninstall the modules to avoid memory leaks,
file descriptor leaks, etc. */
sim_module_uninstall (sd);
}
/* FIXME - these magic numbers need to be moved elsewhere */
#define SP_REGNUM 1 /* Contains address of top of stack */
#define FP_REGNUM 31 /* Contains address of executing stack frame */
#define PC_REGNUM 32 /* Contains program counter (FIXME?) */
#define NPC_REGNUM 33 /* Contains the next program counter (FIXME?) */
#define A0_REGNUM 34 /* Accumulator register 0 */
#define A3_REGNUM 37 /* Accumulator register 1 */
#define R0_REGNUM 0 /* General Purpose Register 0 - for sim */
#define Rn_REGNUM 31 /* Last General Purpose Register - for sim */
#define An_REGNUM A3_REGNUM /* Last Accumulator register - for sim */
int
sim_fetch_register (SIM_DESC sd, int regnr, unsigned char *buf, int length)
{
if (regnr == R0_REGNUM)
memset (buf, 0, sizeof (unsigned32));
else if (regnr > R0_REGNUM && regnr <= Rn_REGNUM)
*(unsigned32*)buf = H2T_4 (STATE_CPU (sd, 0)->reg[regnr - R0_REGNUM]);
else if (regnr == PC_REGNUM)
*(unsigned32*)buf = H2T_4 (STATE_CPU (sd, 0)->cia.ip);
else if (regnr == NPC_REGNUM)
*(unsigned32*)buf = H2T_4 (STATE_CPU (sd, 0)->cia.dp);
else if (regnr >= A0_REGNUM && regnr <= An_REGNUM)
*(unsigned64*)buf = H2T_8 (STATE_CPU (sd, 0)->acc[regnr - A0_REGNUM]);
else
sim_io_error (sd, "sim_fetch_register - unknown register nr %d", regnr);
return -1;
}
int
sim_store_register (SIM_DESC sd, int regnr, unsigned char *buf, int length)
{
if (regnr >= R0_REGNUM && regnr <= Rn_REGNUM)
STATE_CPU (sd, 0)->reg[regnr - R0_REGNUM] = T2H_4 (*(unsigned32*)buf);
else if (regnr == PC_REGNUM)
STATE_CPU (sd, 0)->cia.ip = T2H_4 (*(unsigned32*)buf);
else if (regnr == NPC_REGNUM)
STATE_CPU (sd, 0)->cia.dp = T2H_4 (*(unsigned32*)buf);
else if (regnr >= A0_REGNUM && regnr <= An_REGNUM)
STATE_CPU (sd, 0)->acc[regnr - A0_REGNUM] = T2H_8 (*(unsigned64*)buf);
else
sim_io_error (sd, "sim_store_register - unknown register nr %d", regnr);
return -1;
}
SIM_RC
sim_create_inferior (SIM_DESC sd,
struct _bfd *abfd,
char **argv,
char **envp)
{
/* clear all registers */
memset (&STATE_CPU (sd, 0)->reg, 0, sizeof (STATE_CPU (sd, 0)->reg));
memset (&STATE_CPU (sd, 0)->acc, 0, sizeof (STATE_CPU (sd, 0)->acc));
memset (&STATE_CPU (sd, 0)->cr, 0, sizeof (STATE_CPU (sd, 0)->cr));
STATE_CPU (sd, 0)->is_user_mode = 0;
memset (&STATE_CPU (sd, 0)->cia, 0, sizeof (STATE_CPU (sd, 0)->cia));
/* initialize any modules */
sim_module_init (sd);
/* set the stack-pointer/program counter */
if (abfd != NULL)
STATE_CPU (sd, 0)->cia.ip = bfd_get_start_address (abfd);
else
STATE_CPU (sd, 0)->cia.ip = 0;
STATE_CPU (sd, 0)->cia.dp = (STATE_CPU (sd, 0)->cia.ip
+ sizeof (instruction_word));
STATE_CPU (sd, 0)->cr[IE_CR] |= IE_CR_IE;
STATE_CPU (sd, 0)->reg[1] = TIC80_MEM_START + TIC80_MEM_SIZE - 16;
return SIM_RC_OK;
}
void
sim_do_command (SIM_DESC sd, char *cmd)
{
if (sim_args_command (sd, cmd) != SIM_RC_OK)
sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
}

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sim/tic80/sim-main.h
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@ -1,81 +0,0 @@
/* This file is part of the program psim.
Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
Copyright (C) 1997, Free Software Foundation
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _SIM_MAIN_H_
#define _SIM_MAIN_H_
#include "sim-basics.h"
#include "sim-signal.h"
#include <signal.h> /* For kill() in insns:do_trap */
#include <errno.h>
#ifdef HAVE_UNISTD_H
#include <unistd.h>
#endif
/* These are generated files. */
#include "itable.h"
#include "idecode.h"
#include "idecode.h"
typedef instruction_address sim_cia;
static const sim_cia null_cia = {0}; /* Dummy */
#define NULL_CIA null_cia
/* FIXME: Perhaps igen should generate access macros for
`instruction_address' that we could use. */
#define CIA_ADDR(cia) ((cia).ip)
#define WITH_WATCHPOINTS 1
#include "sim-base.h"
#include "alu.h"
#include "cpu.h"
struct sim_state {
/* the processors proper */
sim_cpu cpu;
#define STATE_CPU(sd, n) (&(sd)->cpu)
/* The base class. */
sim_state_base base;
};
/* (re) initialize the simulator */
extern void engine_init
(SIM_DESC sd);
#ifndef HAVE_GETPID
#define getpid() 42
#endif
#ifndef HAVE_KILL
#define kill(sig, pid) (errno = EINVAL, -1)
#endif
#endif

6
sim/tic80/tic80.dc
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@ -1,6 +0,0 @@
# most instructions
switch: 21: 12: 21: 12
switch: 11: 7: 6: 12
#switch: 21: 13: 21: 13
#switch: 12: 7: 6: 13
switch: 27: 27: 27: 27

52
sim/tic80/tic80.ic
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@ -1,52 +0,0 @@
cache:Dest:Dest:
cache:Dest:rDest:signed_word *:(&(CPU)->reg[Dest])
#
cache:Source1:Source1:
cache:Source1:vSource1:signed_word:(GPR (Source1) + 0)
#cache:Source1:vSource1:signed_word:(Source1 == 0 ? 0 : (CPU)->reg[Source1])
#
cache:Source2:Source2:
cache:Source2:vSource2:signed_word:(GPR (Source2) + 0)
#cache:Source2:vSource2:signed_word:(Source2 == 0 ? 0 : (CPU)->reg[Source2])
#
cache:Source:Source:
cache:Source:vSource:signed_word:(GPR (Source) + 0)
#cache:Source:vSource:signed_word:(Source == 0 ? 0 : (CPU)->reg[Source])
#
cache:IndOff:IndOff:
cache:IndOff:rIndOff:signed_word:(GPR (IndOff) + 0)
#cache:IndOff:rIndOff:signed_word:(IndOff == 0 ? 0 : (CPU)->reg[IndOff])
#
cache:Base:Base:
cache:Base:vBase:signed_word:(GPR (Base) + 0)
cache:Base:rBase:signed_word*:(&GPR (Base))
#cache:Base:vBase:signed_word:(Base == 0 ? 0 : (CPU)->reg[Base])
#
cache:Link:Link:
cache:Link:rLink:signed_word*:(&(CPU)->reg[Link])
#
# Trap Number
cache:UTN:UTN:
cache:INDTR:INDTR:
cache:INDTR:UTN:unsigned_word:(INDTR == 0 ? 0 : (CPU)->reg[INDTR])
#
cache:A:A:
#
cache:SignedImmediate:SignedImmediate:
cache:SignedImmediate:vSource1:signed_word:SEXT (SignedImmediate, 14)
#
cache:UnsignedImmediate:UnsignedImmediate:
cache:UnsignedImmediate:vSource1:signed_word:UnsignedImmediate
#
cache:BITNUM:BITNUM:
cache:Code:Code:
cache:BITNUM:bitnum:int:(~BITNUM) & 0x1f
#
cache:SignedOffset:SignedOffset:
cache:SignedOffset:vSignedOffset:signed_word:SEXT (SignedOffset, 14)
#
cache:UCRN:UCRN:
cache:INDCR:INDCR:
cache:INDCR:UCRN:unsigned32:(GPR (INDCR) + 0)
#cache:INDCR:UCRN:unsigned32:(INDCR == 0 ? 0 : (CPU)->reg[INDCR])

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sim/tic80/tic80.igen
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