* gas/config/tc-arm.c (do_vfp_reg2_from_sp2): Rename from
do_vfp_sp_reg2. (do_vfp_sp2_from_reg2): New function. (insns): Use them. (do_vfp_dp_from_reg2): Check return values properly. * opcodes/arm-opc.h (arm_opcodes): Move generic mcrr after known specific opcodes. * gas/testsuite/gas/arm/vfp2.s, gas/arm/vfp2.d: New test. * gas/testsuite/gas/arm/arm.exp: Add them.
This commit is contained in:
Paul Brook
parent
041ab88cf0
commit
e45d06306f
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@ -1,3 +1,10 @@
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2004-01-09 Paul Brook <paul@codesourcery.com>
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* config/tc-arm.c (do_vfp_reg2_from_sp2): Rename from do_vfp_sp_reg2.
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(do_vfp_sp2_from_reg2): New function.
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(insns): Use them.
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(do_vfp_dp_from_reg2): Check return values properly.
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2004-01-08 Ian Lance Taylor <ian@wasabisystems.com>
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* config/tc-mips.c (warn_nops): Remove static variable.
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@ -929,7 +929,8 @@ static void do_vfp_sp_dyadic PARAMS ((char *));
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static void do_vfp_dp_dyadic PARAMS ((char *));
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static void do_vfp_reg_from_sp PARAMS ((char *));
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static void do_vfp_sp_from_reg PARAMS ((char *));
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static void do_vfp_sp_reg2 PARAMS ((char *));
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static void do_vfp_reg2_from_sp2 PARAMS ((char *));
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static void do_vfp_sp2_from_reg2 PARAMS ((char *));
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static void do_vfp_reg_from_dp PARAMS ((char *));
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static void do_vfp_reg2_from_dp PARAMS ((char *));
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static void do_vfp_dp_from_reg PARAMS ((char *));
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@ -1976,8 +1977,8 @@ static const struct asm_opcode insns[] =
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{"fcmpezd", 0xeeb50bc0, 7, FPU_VFP_EXT_V1, do_vfp_dp_compare_z},
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/* VFP V2. */
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{"fmsrr", 0xec400a10, 5, FPU_VFP_EXT_V2, do_vfp_sp_reg2},
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{"fmrrs", 0xec500a10, 5, FPU_VFP_EXT_V2, do_vfp_sp_reg2},
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{"fmsrr", 0xec400a10, 5, FPU_VFP_EXT_V2, do_vfp_sp2_from_reg2},
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{"fmrrs", 0xec500a10, 5, FPU_VFP_EXT_V2, do_vfp_reg2_from_sp2},
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{"fmdrr", 0xec400b10, 5, FPU_VFP_EXT_V2, do_vfp_dp_from_reg2},
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{"fmrrd", 0xec500b10, 5, FPU_VFP_EXT_V2, do_vfp_reg2_from_dp},
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@ -8954,15 +8955,13 @@ do_vfp_reg_from_sp (str)
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}
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static void
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do_vfp_sp_reg2 (str)
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do_vfp_reg2_from_sp2 (str)
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char *str;
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{
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skip_whitespace (str);
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if (reg_required_here (&str, 12) == FAIL)
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return;
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if (skip_past_comma (&str) == FAIL
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if (reg_required_here (&str, 12) == FAIL
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|| skip_past_comma (&str) == FAIL
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|| reg_required_here (&str, 16) == FAIL
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|| skip_past_comma (&str) == FAIL)
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{
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@ -9001,6 +9000,32 @@ do_vfp_sp_from_reg (str)
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end_of_line (str);
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}
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static void
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do_vfp_sp2_from_reg2 (str)
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char *str;
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{
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skip_whitespace (str);
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/* We require exactly two consecutive SP registers. */
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if (vfp_sp_reg_list (&str, VFP_REG_Sm) != 2)
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{
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if (! inst.error)
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inst.error = _("only two consecutive VFP SP registers allowed here");
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}
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if (skip_past_comma (&str) == FAIL
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|| reg_required_here (&str, 12) == FAIL
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|| skip_past_comma (&str) == FAIL
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|| reg_required_here (&str, 16) == FAIL)
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{
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if (! inst.error)
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inst.error = BAD_ARGS;
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return;
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}
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end_of_line (str);
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}
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static void
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do_vfp_reg_from_dp (str)
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char *str;
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@ -9075,7 +9100,7 @@ do_vfp_dp_from_reg2 (str)
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if (skip_past_comma (&str) == FAIL
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|| reg_required_here (&str, 12) == FAIL
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|| skip_past_comma (&str) == FAIL
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|| reg_required_here (&str, 16))
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|| reg_required_here (&str, 16) == FAIL)
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{
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if (! inst.error)
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inst.error = BAD_ARGS;
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@ -1,3 +1,8 @@
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2004-01-09 Paul Brook <paul@codesourcery.com>
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* gas/arm/vfp2.s, gas/arm/vfp2.d: New test.
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* gas/arm/arm.exp: Add them.
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2004-01-08 Ian Lance Taylor <ian@wasabisystems.com>
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* gas/mips/ldstla-n64.d: Pass -64 to assembler, not -n64.
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@ -61,6 +61,8 @@ if {[istarget *arm*-*-*] || [istarget "xscale-*-*"]} then {
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run_dump_test "vfp1"
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run_dump_test "vfp2"
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run_errors_test "vfp-bad" "-mfpu=vfp" "VFP errors"
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run_dump_test "xscale"
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@ -0,0 +1,17 @@
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#objdump: -dr --prefix-addresses --show-raw-insn
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#name: VFP Additional instructions
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#as: -mfpu=vfp
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# Test the ARM VFP Double Precision instructions
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.*: +file format .*arm.*
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Disassembly of section .text:
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0+000 <[^>]*> ec4a5b10 fmdrr d0, r5, sl
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0+004 <[^>]*> ec5a5b10 fmrrd r5, sl, d0
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0+008 <[^>]*> ec4a5a37 fmsrr r5, sl, {s15, s16}
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0+00c <[^>]*> ec5a5a37 fmrrs r5, sl, {s15, s16}
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0+010 <[^>]*> ec45ab1f fmdrr d15, sl, r5
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0+014 <[^>]*> ec55ab1f fmrrd sl, r5, d15
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0+018 <[^>]*> ec45aa38 fmsrr sl, r5, {s17, s18}
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0+01c <[^>]*> ec55aa38 fmrrs sl, r5, {s17, s18}
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@ -0,0 +1,18 @@
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@ VFP2 Additional instructions
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.text
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.global F
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F:
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@ First we test the basic syntax and bit patterns of the opcodes.
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@ Use a combination of r5, r10, s15, s17, d0 and d15 to exercise
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@ the full register bitpatterns
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fmdrr d0, r5, r10
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fmrrd r5, r10, d0
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fmsrr {s15, s16}, r5, r10
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fmrrs r5, r10, {s15, s16}
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fmdrr d15, r10, r5
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fmrrd r10, r5, d15
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fmsrr {s17, s18}, r10, r5
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fmrrs r10, r5, {s17, s18}
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@ -1,3 +1,8 @@
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2004-01-09 Paul Brook <paul@codesourcery.com>
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* arm-opc.h (arm_opcodes): Move generic mcrr after known
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specific opcodes.
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2004-01-07 Daniel Jacobowitz <drow@mvista.com>
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* Makefile.am (libopcodes_la_DEPENDENCIES)
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@ -328,9 +328,6 @@ static const struct arm_opcode arm_opcodes[] =
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{0x01200050, 0x0ff00ff0, "qsub%c\t%12-15r, %0-3r, %16-19r"},
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{0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"},
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{0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
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{0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
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/* ARM Instructions. */
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{0x00000090, 0x0e100090, "str%c%6's%5?hb\t%12-15r, %s"},
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{0x00100090, 0x0e100090, "ldr%c%6's%5?hb\t%12-15r, %s"},
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@ -569,6 +566,8 @@ static const struct arm_opcode arm_opcodes[] =
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{0x0e300600, 0x0ff00f00, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
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/* Generic coprocessor instructions */
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{0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
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{0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
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{0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
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{0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
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{0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
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