From e52d501632e2c9c117e14ba1b2a52c75f2d6f353 Mon Sep 17 00:00:00 2001 From: Nathan Froyd Date: Fri, 12 Nov 2010 21:53:10 +0000 Subject: [PATCH] gdb/ * rs6000-tdep.c (gdb_print_insn_powerpc): Disassemble e500 instructions if debugging an E500 binary. --- gdb/ChangeLog | 5 +++++ gdb/rs6000-tdep.c | 14 +++++++++++++- 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/gdb/ChangeLog b/gdb/ChangeLog index 58ce121d58..8e60d3a1a1 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,8 @@ +2010-11-12 Nathan Froyd + + * rs6000-tdep.c (gdb_print_insn_powerpc): Disassemble e500 + instructions if debugging an E500 binary. + 2010-11-12 Tom Tromey * varobj.c (value_get_print_value): Rearrange. Pass stream to diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c index 09c7f8ff9c..611c775e3c 100644 --- a/gdb/rs6000-tdep.c +++ b/gdb/rs6000-tdep.c @@ -3029,7 +3029,19 @@ static int gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info) { if (!info->disassembler_options) - info->disassembler_options = "any"; + { + /* When debugging E500 binaries and disassembling code containing + E500-specific (SPE) instructions, one sometimes sees AltiVec + instructions instead. The opcode spaces for SPE instructions + and AltiVec instructions overlap, and specifiying the "any" cpu + looks for AltiVec instructions first. If we know we're + debugging an E500 binary, however, we can specify the "e500x2" + cpu and get much more sane disassembly output. */ + if (info->mach == bfd_mach_ppc_e500) + info->disassembler_options = "e500x2"; + else + info->disassembler_options = "any"; + } if (info->endian == BFD_ENDIAN_BIG) return print_insn_big_powerpc (memaddr, info);