Tue Jul 11 14:28:55 1995 Jeff Spiegel <jeffs@lsil.com>
* config/tc-mips.c (mips_4010): New static variable. (interlocks): New static variable. (md_begin): Check for a cpu of "r4010". Set mips_4010 correctly. If mips_4650 or mips_4010, set interlocks. (append_insn): Check interlocks, not mips_4650. (mips_emit_delays): Likewise. (mips_ip): Only permit INSN_4010 instructions if mips_4010. (md_longopts): Add "m4010" and "no-m4010". (md_parse_option): Accept -mcpu=r4010. Handle -m4010 and -no-m4010. (md_show_usage): Document -m4010 and -no-m4010.
This commit is contained in:
Ian Lance Taylor
parent
89abbf9d2c
commit
e532b44c23
@ -19,7 +19,7 @@
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to
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the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
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the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "as.h"
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#include "config.h"
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@ -126,6 +126,13 @@ static int mips_cpu = -1;
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/* Whether the 4650 instructions (mad/madu) are permitted. */
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static int mips_4650 = -1;
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/* Whether the 4010 instructions are permitted. */
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static int mips_4010 = -1;
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/* Whether the processor uses hardware interlocks, and thus does not
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require nops to be inserted. */
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static int interlocks = -1;
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/* MIPS PIC level. */
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enum mips_pic_level
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@ -584,6 +591,14 @@ md_begin ()
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if (mips_4650 == -1)
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mips_4650 = 1;
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}
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else if (strcmp (cpu, "r4010") == 0)
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{
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mips_isa = 2;
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if (mips_cpu == -1)
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mips_cpu = 4010;
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if (mips_4010 == -1)
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mips_4010 = 1;
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}
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else if (strcmp (cpu, "r8000") == 0
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|| strcmp (cpu, "mips4") == 0)
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{
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@ -611,6 +626,14 @@ md_begin ()
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if (mips_4650 < 0)
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mips_4650 = 0;
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if (mips_4010 < 0)
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mips_4010 = 0;
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if (mips_4650 || mips_4010)
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interlocks = 1;
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else
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interlocks = 0;
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if (mips_isa < 2 && mips_trap)
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as_bad ("trap exception not supported at ISA 1");
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@ -936,7 +959,7 @@ append_insn (place, ip, address_expr, reloc_type)
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/* The previous instruction reads the LO register; if the
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current instruction writes to the LO register, we must
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insert two NOPS. The R4650 has interlocks. */
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if (! mips_4650
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if (! interlocks
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&& (mips_optimize == 0
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|| (pinfo & INSN_WRITE_LO)))
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nops += 2;
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@ -946,7 +969,7 @@ append_insn (place, ip, address_expr, reloc_type)
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/* The previous instruction reads the HI register; if the
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current instruction writes to the HI register, we must
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insert a NOP. The R4650 has interlocks. */
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if (! mips_4650
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if (! interlocks
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&& (mips_optimize == 0
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|| (pinfo & INSN_WRITE_HI)))
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nops += 2;
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@ -967,10 +990,10 @@ append_insn (place, ip, address_expr, reloc_type)
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&& (pinfo & INSN_READ_COND_CODE))
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|| ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
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&& (pinfo & INSN_WRITE_LO)
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&& ! mips_4650)
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&& ! interlocks)
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|| ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
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&& (pinfo & INSN_WRITE_HI)
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&& ! mips_4650)))
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&& ! interlocks)))
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++nops;
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/* If we are being given a nop instruction, don't bother with
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@ -1143,7 +1166,7 @@ append_insn (place, ip, address_expr, reloc_type)
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& (INSN_LOAD_COPROC_DELAY
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| INSN_COPROC_MOVE_DELAY
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| INSN_WRITE_COND_CODE)))
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|| (! mips_4650
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|| (! interlocks
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&& (prev_pinfo
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& (INSN_READ_LO
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| INSN_READ_HI)))
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@ -1333,7 +1356,7 @@ mips_emit_delays ()
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& (INSN_LOAD_COPROC_DELAY
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| INSN_COPROC_MOVE_DELAY
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| INSN_WRITE_COND_CODE)))
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|| (! mips_4650
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|| (! interlocks
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&& (prev_insn.insn_mo->pinfo
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& (INSN_READ_LO
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| INSN_READ_HI)))
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@ -1345,14 +1368,14 @@ mips_emit_delays ()
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nop = 1;
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if ((mips_isa < 4
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&& (prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
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|| (! mips_4650
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|| (! interlocks
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&& ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
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|| (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
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emit_nop ();
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}
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else if ((mips_isa < 4
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&& (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
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|| (! mips_4650
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|| (! interlocks
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&& ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
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|| (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
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nop = 1;
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@ -4358,7 +4381,9 @@ mips_ip (str, ip)
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if (insn_isa > mips_isa
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|| ((insn->pinfo & INSN_ISA) == INSN_4650
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&& ! mips_4650))
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&& ! mips_4650)
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|| ((insn->pinfo & INSN_ISA) == INSN_4010
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&& ! mips_4010))
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{
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if (insn + 1 < &mips_opcodes[NUMOPCODES]
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&& strcmp (insn->name, insn[1].name) == 0)
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@ -5241,6 +5266,10 @@ struct option md_longopts[] = {
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{"m4650", no_argument, NULL, OPTION_M4650},
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#define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
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{"no-m4650", no_argument, NULL, OPTION_NO_M4650},
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#define OPTION_M4010 (OPTION_MD_BASE + 15)
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{"m4010", no_argument, NULL, OPTION_M4010},
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#define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
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{"no-m4010", no_argument, NULL, OPTION_NO_M4010},
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#define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
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#define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
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@ -5373,6 +5402,12 @@ md_parse_option (c, arg)
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if (mips_4650 < 0)
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mips_4650 = 1;
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}
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else if (strcmp (p, "4010") == 0)
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{
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mips_cpu = 4010;
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if (mips_4010 < 0)
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mips_4010 = 1;
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}
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break;
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case '6':
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@ -5412,6 +5447,14 @@ md_parse_option (c, arg)
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mips_4650 = 0;
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break;
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case OPTION_M4010:
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mips_4010 = 1;
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break;
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case OPTION_NO_M4010:
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mips_4010 = 0;
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break;
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case OPTION_MEMBEDDED_PIC:
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mips_pic = EMBEDDED_PIC;
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if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
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@ -5489,8 +5532,10 @@ MIPS options:\n\
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-mips2, -mcpu=r6000 generate code for r6000\n\
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-mips3, -mcpu=r4000 generate code for r4000\n\
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-mips4, -mcpu=r8000 generate code for r8000\n\
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-m4650 permit -m4650 instructions\n\
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-no-m4650 do not permit -m4650 instructions\n\
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-m4650 permit R4650 instructions\n\
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-no-m4650 do not permit R4650 instructions\n\
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-m4010 permit R4010 instructions\n\
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-no-m4010 do not permit R4010 instructions\n\
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-O0 remove unneeded NOPs, do not swap branches\n\
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-O remove unneeded NOPs and swap branches\n\
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--trap, --no-break trap exception on div by 0 and mult overflow\n\
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