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Add the endian reversing versions of load/store instructions; 

2012-11-14  Edgar E. Iglesias <edgar.iglesias@gmail.com>

	* microblaze-opc.h: Increase MAX_OPCODES (op_code_struct):  add lbur,
	lhur, lwr, sbr, shr, swr
	* microblaze-opcm.h (microblaze_instr): add lbur, lhur, lwr, sbr, shr,
	swr

2012-11-14  David Holsgrove  <david.holsgrove@xilinx.com>

	* gas/microblaze/allinsn.exp: New file - test newly added opcodes
	* gas/microblaze/allinsn.s: Likewise
	* gas/microblaze/allinsn.d: Likewise
This commit is contained in:
Michael Eager 2012-11-14 16:19:30 +00:00
parent aff68abbd7
commit e692c2171e
7 changed files with 78 additions and 2 deletions
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6
gas/testsuite/ChangeLog
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@ -1,3 +1,9 @@
2012-11-14 David Holsgrove <david.holsgrove@xilinx.com>
* gas/microblaze/allinsn.exp: New file - test newly added opcodes
* gas/microblaze/allinsn.s: Likewise
* gas/microblaze/allinsn.d: Likewise
2012-11-14 Ulrich Weigand <uweigand@de.ibm.com>
* gas/ppc/astest.d: Update for fixup changes.

24
gas/testsuite/gas/microblaze/allinsn.d Normal file
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@ -0,0 +1,24 @@
#as:
#objdump: -d
.*: +file format .*
Disassembly of section .text:
00000000 <lbur>:
0: c0000200 lbur r0, r0, r0
00000004 <lhur>:
4: c4000200 lhur r0, r0, r0
00000008 <lwr>:
8: c8000200 lwr r0, r0, r0
0000000c <sbr>:
c: d0000200 sbr r0, r0, r0
00000010 <shr>:
10: d4000200 shr r0, r0, r0
00000014 <swr>:
14: d8000200 swr r0, r0, r0

5
gas/testsuite/gas/microblaze/allinsn.exp Normal file
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@ -0,0 +1,5 @@
# MicroBlaze test for special register.
if [istarget microblaze*-*-*] {
run_dump_test "allinsn"
}

27
gas/testsuite/gas/microblaze/allinsn.s Normal file
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@ -0,0 +1,27 @@
.text
footext:
.text
.global lbur
lbur:
lbur r0,r0,r0
.text
.global lhur
lhur:
lhur r0,r0,r0
.text
.global lwr
lwr:
lwr r0,r0,r0
.text
.global sbr
sbr:
sbr r0,r0,r0
.text
.global shr
shr:
shr r0,r0,r0
.text
.global swr
swr:
swr r0,r0,r0

7
opcodes/ChangeLog
View File

@ -1,3 +1,10 @@
2012-11-14 Edgar E. Iglesias <edgar.iglesias@gmail.com>
* microblaze-opc.h: Increase MAX_OPCODES (op_code_struct): add lbur,
lhur, lwr, sbr, shr, swr
* microblaze-opcm.h (microblaze_instr): add lbur, lhur, lwr, sbr, shr,
swr
2012-11-09 Nick Clifton <nickc@redhat.com>
* configure.in: Add bfd_v850_rh850_arch.

8
opcodes/microblaze-opc.h
View File

@ -96,7 +96,7 @@
#define DELAY_SLOT 1
#define NO_DELAY_SLOT 0
#define MAX_OPCODES 280
#define MAX_OPCODES 284
struct op_code_struct
{
@ -220,12 +220,18 @@ struct op_code_struct
{"bgei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBCA00000, OPCODE_MASK_H1, bgei, branch_inst },
{"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst },
{"lbu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst },
{"lbur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000200, OPCODE_MASK_H4, lbur, memory_load_inst },
{"lhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst },
{"lhur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000200, OPCODE_MASK_H4, lhur, memory_load_inst },
{"lw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst },
{"lwr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000200, OPCODE_MASK_H4, lwr, memory_load_inst },
{"lwx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst },
{"sb", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst },
{"sbr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000200, OPCODE_MASK_H4, sbr, memory_store_inst },
{"sh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst },
{"shr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000200, OPCODE_MASK_H4, shr, memory_store_inst },
{"sw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst },
{"swr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000200, OPCODE_MASK_H4, swr, memory_store_inst },
{"swx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst },
{"lbui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst },
{"lhui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst },

3
opcodes/microblaze-opcm.h
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@ -36,7 +36,8 @@ enum microblaze_instr
bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
bgtid, bgei, bgeid, lbu, lhu, lw, lwx, sb, sh, sw, swx, lbui, lhui, lwi,
bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh,
shr, sw, swr, swx, lbui, lhui, lwi,
sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv,
fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
fint, fsqrt,