Add the endian reversing versions of load/store instructions;
2012-11-14 Edgar E. Iglesias <edgar.iglesias@gmail.com> * microblaze-opc.h: Increase MAX_OPCODES (op_code_struct): add lbur, lhur, lwr, sbr, shr, swr * microblaze-opcm.h (microblaze_instr): add lbur, lhur, lwr, sbr, shr, swr 2012-11-14 David Holsgrove <david.holsgrove@xilinx.com> * gas/microblaze/allinsn.exp: New file - test newly added opcodes * gas/microblaze/allinsn.s: Likewise * gas/microblaze/allinsn.d: Likewise
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@ -1,3 +1,9 @@
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2012-11-14 David Holsgrove <david.holsgrove@xilinx.com>
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* gas/microblaze/allinsn.exp: New file - test newly added opcodes
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* gas/microblaze/allinsn.s: Likewise
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* gas/microblaze/allinsn.d: Likewise
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2012-11-14 Ulrich Weigand <uweigand@de.ibm.com>
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* gas/ppc/astest.d: Update for fixup changes.
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#as:
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#objdump: -d
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.*: +file format .*
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Disassembly of section .text:
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00000000 <lbur>:
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0: c0000200 lbur r0, r0, r0
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00000004 <lhur>:
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4: c4000200 lhur r0, r0, r0
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00000008 <lwr>:
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8: c8000200 lwr r0, r0, r0
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0000000c <sbr>:
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c: d0000200 sbr r0, r0, r0
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00000010 <shr>:
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10: d4000200 shr r0, r0, r0
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00000014 <swr>:
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14: d8000200 swr r0, r0, r0
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# MicroBlaze test for special register.
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if [istarget microblaze*-*-*] {
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run_dump_test "allinsn"
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}
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@ -0,0 +1,27 @@
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.text
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footext:
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.text
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.global lbur
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lbur:
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lbur r0,r0,r0
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.text
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.global lhur
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lhur:
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lhur r0,r0,r0
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.text
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.global lwr
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lwr:
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lwr r0,r0,r0
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.text
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.global sbr
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sbr:
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sbr r0,r0,r0
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.text
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.global shr
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shr:
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shr r0,r0,r0
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.text
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.global swr
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swr:
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swr r0,r0,r0
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@ -1,3 +1,10 @@
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2012-11-14 Edgar E. Iglesias <edgar.iglesias@gmail.com>
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* microblaze-opc.h: Increase MAX_OPCODES (op_code_struct): add lbur,
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lhur, lwr, sbr, shr, swr
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* microblaze-opcm.h (microblaze_instr): add lbur, lhur, lwr, sbr, shr,
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swr
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2012-11-09 Nick Clifton <nickc@redhat.com>
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* configure.in: Add bfd_v850_rh850_arch.
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@ -96,7 +96,7 @@
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#define DELAY_SLOT 1
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#define NO_DELAY_SLOT 0
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#define MAX_OPCODES 280
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#define MAX_OPCODES 284
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struct op_code_struct
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{
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@ -220,12 +220,18 @@ struct op_code_struct
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{"bgei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBCA00000, OPCODE_MASK_H1, bgei, branch_inst },
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{"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst },
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{"lbu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst },
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{"lbur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000200, OPCODE_MASK_H4, lbur, memory_load_inst },
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{"lhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst },
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{"lhur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000200, OPCODE_MASK_H4, lhur, memory_load_inst },
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{"lw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst },
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{"lwr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000200, OPCODE_MASK_H4, lwr, memory_load_inst },
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{"lwx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst },
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{"sb", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst },
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{"sbr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000200, OPCODE_MASK_H4, sbr, memory_store_inst },
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{"sh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst },
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{"shr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000200, OPCODE_MASK_H4, shr, memory_store_inst },
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{"sw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst },
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{"swr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000200, OPCODE_MASK_H4, swr, memory_store_inst },
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{"swx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst },
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{"lbui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst },
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{"lhui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst },
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@ -36,7 +36,8 @@ enum microblaze_instr
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bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
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imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
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brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
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bgtid, bgei, bgeid, lbu, lhu, lw, lwx, sb, sh, sw, swx, lbui, lhui, lwi,
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bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh,
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shr, sw, swr, swx, lbui, lhui, lwi,
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sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv,
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fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
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fint, fsqrt,
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