RISC-V: Add missing hint instructions from RV128I.
gas/ * testsuite/gas/riscv/c-zero-imm.d: Add more tests. * testsuite/gas/riscv/c-zero-imm.s: Likewise. * testsuite/gas/riscv/c-zero-reg.d: Fix typo in test. Add disabled future test for RV128 support. * testsuite/gas/riscv/c-zero-reg.s: Likewise. include/ * opcode/riscv-opc.h (MATCH_C_SRLI64, MASK_C_SRLI64): New. (MATCH_C_SRAI64, MASK_C_SRAI64): New. (MATCH_C_SLLI64, MASK_C_SLLI64): New. opcodes/ * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New. (match_c_slli64, match_srxi_as_c_srxi): New. (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli. <srli, srl, srai, sra>: Use match_srxi_as_c_srxi. <c.slli, c.srli, c.srai>: Use match_s_slli. <c.slli64, c.srli64, c.srai64>: New.
This commit is contained in:
Jim Wilson
parent
7402fbcae1
commit
e6f372ba66
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@ -1,3 +1,11 @@
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2018-05-08 Jim Wilson <jimw@sifive.com>
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* testsuite/gas/riscv/c-zero-imm.d: Add more tests.
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* testsuite/gas/riscv/c-zero-imm.s: Likewise.
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* testsuite/gas/riscv/c-zero-reg.d: Fix typo in test. Add disabled
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future test for RV128 support.
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* testsuite/gas/riscv/c-zero-reg.s: Likewise.
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2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
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H.J. Lu <hongjiu.lu@intel.com>
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@ -14,4 +14,10 @@ Disassembly of section .text:
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[ ]+8:[ ]+0001[ ]+nop
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[ ]+a:[ ]+00070713[ ]+mv[ ]+a4,a4
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[ ]+e:[ ]+0781[ ]+addi[ ]+a5,a5,0
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[ ]+10:[ ]+00051513[ ]+slli[ ]+a0,a0,0x0
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[ ]+14:[ ]+0005d593[ ]+srli[ ]+a1,a1,0x0
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[ ]+18:[ ]+40065613[ ]+srai[ ]+a2,a2,0x0
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[ ]+1c:[ ]+0682[ ]+c.slli64[ ]+a3
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[ ]+1e:[ ]+8301[ ]+c.srli64[ ]+a4
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[ ]+20:[ ]+8781[ ]+c.srai64[ ]+a5
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#...
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@ -9,3 +9,11 @@
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addi a4,a4,0
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# These are hints.
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c.addi a5,0
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# Don't let these compress to hints.
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slli a0, a0, 0
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srli a1, a1, 0
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srai a2, a2, 0
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# These are hints.
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c.slli64 a3
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c.srli64 a4
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c.srai64 a5
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@ -14,7 +14,7 @@ Disassembly of section .text:
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[ ]+8:[ ]+9006[ ]+c.add[ ]+zero,ra
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[ ]+a:[ ]+00500013[ ]+li[ ]+zero,5
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[ ]+e:[ ]+00006037[ ]+lui[ ]+zero,0x6
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[ ]+12:[ ]+00709013[ ]+slli[ ]+zero,ra,0x7
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[ ]+12:[ ]+00701013[ ]+slli[ ]+zero,zero,0x7
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[ ]+16:[ ]+00008013[ ]+mv[ ]+zero,ra
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[ ]+1a:[ ]+00100033[ ]+add[ ]+zero,zero,ra
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#...
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@ -8,6 +8,8 @@
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# Don't let these compress to hints.
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li x0, 5
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lui x0, 6
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slli x0, x1, 7
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slli x0, x0, 7
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mv x0, x1
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add x0, x0, x1
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# RV128 support not implemented yet.
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# slli x0, x0, 64
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@ -1,3 +1,9 @@
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2018-05-08 Jim Wilson <jimw@sifive.com>
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* opcode/riscv-opc.h (MATCH_C_SRLI64, MASK_C_SRLI64): New.
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(MATCH_C_SRAI64, MASK_C_SRAI64): New.
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(MATCH_C_SLLI64, MASK_C_SLLI64): New.
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2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
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* opcode/ppc.h (powerpc_num_opcodes): Change type to unsigned.
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@ -459,8 +459,12 @@
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#define MASK_C_LUI 0xe003
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#define MATCH_C_SRLI 0x8001
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#define MASK_C_SRLI 0xec03
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#define MATCH_C_SRLI64 0x8001
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#define MASK_C_SRLI64 0xfc7f
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#define MATCH_C_SRAI 0x8401
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#define MASK_C_SRAI 0xec03
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#define MATCH_C_SRAI64 0x8401
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#define MASK_C_SRAI64 0xfc7f
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#define MATCH_C_ANDI 0x8801
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#define MASK_C_ANDI 0xec03
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#define MATCH_C_SUB 0x8c01
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@ -483,6 +487,8 @@
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#define MASK_C_BNEZ 0xe003
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#define MATCH_C_SLLI 0x2
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#define MASK_C_SLLI 0xe003
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#define MATCH_C_SLLI64 0x2
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#define MASK_C_SLLI64 0xf07f
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#define MATCH_C_FLDSP 0x2002
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#define MASK_C_FLDSP 0xe003
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#define MATCH_C_LWSP 0x4002
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@ -1,3 +1,12 @@
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2018-05-08 Jim Wilson <jimw@sifive.com>
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* riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
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(match_c_slli64, match_srxi_as_c_srxi): New.
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(riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
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<srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
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<c.slli, c.srli, c.srai>: Use match_s_slli.
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<c.slli64, c.srli64, c.srai64>: New.
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2018-05-08 Alan Modra <amodra@gmail.com>
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* ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
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@ -162,6 +162,39 @@ match_c_addi4spn (const struct riscv_opcode *op, insn_t insn)
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return match_opcode (op, insn) && EXTRACT_RVC_ADDI4SPN_IMM (insn) != 0;
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}
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/* This requires a non-zero shift. A zero rd is a hint, so is allowed. */
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static int
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match_c_slli (const struct riscv_opcode *op, insn_t insn)
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{
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return match_opcode (op, insn) && EXTRACT_RVC_IMM (insn) != 0;
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}
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/* This requires a non-zero rd, and a non-zero shift. */
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static int
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match_slli_as_c_slli (const struct riscv_opcode *op, insn_t insn)
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{
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return match_rd_nonzero (op, insn) && EXTRACT_RVC_IMM (insn) != 0;
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}
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/* This requires a zero shift. A zero rd is a hint, so is allowed. */
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static int
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match_c_slli64 (const struct riscv_opcode *op, insn_t insn)
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{
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return match_opcode (op, insn) && EXTRACT_RVC_IMM (insn) == 0;
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}
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/* This is used for both srli and srai. This requires a non-zero shift.
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A zero rd is not possible. */
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static int
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match_srxi_as_c_srxi (const struct riscv_opcode *op, insn_t insn)
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{
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return match_opcode (op, insn) && EXTRACT_RVC_IMM (insn) != 0;
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}
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const struct riscv_opcode riscv_opcodes[] =
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{
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/* name, isa, operands, match, mask, match_func, pinfo. */
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@ -250,19 +283,19 @@ const struct riscv_opcode riscv_opcodes[] =
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{"la.tls.gd", "I", "d,A", 0, (int) M_LA_TLS_GD, match_never, INSN_MACRO },
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{"la.tls.ie", "I", "d,A", 0, (int) M_LA_TLS_IE, match_never, INSN_MACRO },
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{"neg", "I", "d,t", MATCH_SUB, MASK_SUB | MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0 */
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{"slli", "C", "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, INSN_ALIAS },
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{"slli", "C", "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_slli_as_c_slli, INSN_ALIAS },
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{"slli", "I", "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, 0 },
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{"sll", "C", "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, INSN_ALIAS },
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{"sll", "C", "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_slli_as_c_slli, INSN_ALIAS },
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{"sll", "I", "d,s,t", MATCH_SLL, MASK_SLL, match_opcode, 0 },
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{"sll", "I", "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, INSN_ALIAS },
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{"srli", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_opcode, INSN_ALIAS },
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{"srli", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_srxi_as_c_srxi, INSN_ALIAS },
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{"srli", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, 0 },
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{"srl", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_opcode, INSN_ALIAS },
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{"srl", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_srxi_as_c_srxi, INSN_ALIAS },
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{"srl", "I", "d,s,t", MATCH_SRL, MASK_SRL, match_opcode, 0 },
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{"srl", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, INSN_ALIAS },
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{"srai", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_opcode, INSN_ALIAS },
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{"srai", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_srxi_as_c_srxi, INSN_ALIAS },
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{"srai", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, 0 },
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{"sra", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_opcode, INSN_ALIAS },
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{"sra", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_srxi_as_c_srxi, INSN_ALIAS },
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{"sra", "I", "d,s,t", MATCH_SRA, MASK_SRA, match_opcode, 0 },
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{"sra", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, INSN_ALIAS },
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{"sub", "C", "Cs,Cw,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, INSN_ALIAS },
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@ -686,9 +719,12 @@ const struct riscv_opcode riscv_opcodes[] =
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{"c.and", "C", "Cs,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, 0 },
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{"c.or", "C", "Cs,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, 0 },
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{"c.xor", "C", "Cs,Ct", MATCH_C_XOR, MASK_C_XOR, match_opcode, 0 },
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{"c.slli", "C", "d,C>", MATCH_C_SLLI, MASK_C_SLLI, match_opcode, 0 },
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{"c.srli", "C", "Cs,C>", MATCH_C_SRLI, MASK_C_SRLI, match_opcode, 0 },
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{"c.srai", "C", "Cs,C>", MATCH_C_SRAI, MASK_C_SRAI, match_opcode, 0 },
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{"c.slli", "C", "d,C>", MATCH_C_SLLI, MASK_C_SLLI, match_c_slli, 0 },
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{"c.srli", "C", "Cs,C>", MATCH_C_SRLI, MASK_C_SRLI, match_c_slli, 0 },
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{"c.srai", "C", "Cs,C>", MATCH_C_SRAI, MASK_C_SRAI, match_c_slli, 0 },
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{"c.slli64", "C", "d", MATCH_C_SLLI64, MASK_C_SLLI64, match_c_slli64, 0 },
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{"c.srli64", "C", "Cs", MATCH_C_SRLI64, MASK_C_SRLI64, match_c_slli64, 0 },
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{"c.srai64", "C", "Cs", MATCH_C_SRAI64, MASK_C_SRAI64, match_c_slli64, 0 },
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{"c.andi", "C", "Cs,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, 0 },
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{"c.addiw", "64C", "d,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, 0 },
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{"c.addw", "64C", "Cs,Ct", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, 0 },
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