Finish off adding MIPS32 instructions.
This commit is contained in:
Nick Clifton
parent
b6426432a0
commit
e70f259005
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@ -28,6 +28,10 @@
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* gas/mips/mips16-f.d: Likewise.
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* gas/mips/mips16-f.s: Likewise.
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* gas/mips/mips32.d: Expect disassembly of madd and maddu
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to use their correct names. Add tests for break and sdbbp.
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* gas/mips/mips32.s: Likewise.
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2000-12-01 Chris Demetriou <cgd@sibyte.com>
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* gas/mips/mips16.d: Expect mips16 nops to be used for padding
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@ -9,8 +9,8 @@
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Disassembly of section .text:
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0+0000 <[^>]*> 70410821 clo \$at,\$v0
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0+0004 <[^>]*> 70831820 clz \$v1,\$a0
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0+0008 <[^>]*> 70a60000 mad \$a1,\$a2
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0+000c <[^>]*> 70e80001 madu \$a3,\$t0
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0+0008 <[^>]*> 70a60000 madd \$a1,\$a2
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0+000c <[^>]*> 70e80001 maddu \$a3,\$t0
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0+0010 <[^>]*> 712a0004 msub \$t1,\$t2
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0+0014 <[^>]*> 716c0005 msubu \$t3,\$t4
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0+0018 <[^>]*> 71cf6802 mul \$t5,\$t6,\$t7
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@ -46,4 +46,10 @@ Disassembly of section .text:
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0+0090 <[^>]*> 42000020 wait
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0+0094 <[^>]*> 42000020 wait
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0+0098 <[^>]*> 4359e260 wait 0x56789
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0+009c <[^>]*> 00000000 nop
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0+009c <[^>]*> 0000000d break
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0+00a0 <[^>]*> 0000000d break
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0+00a4 <[^>]*> 0048d14d break 0x12345
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0+00a8 <[^>]*> 7000003f sdbbp
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0+00ac <[^>]*> 7000003f sdbbp
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0+00b0 <[^>]*> 7159e27f sdbbp 0x56789
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...
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@ -10,8 +10,8 @@ text_label:
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clo $1, $2
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clz $3, $4
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madd $5, $6 # disassembles as mad ...
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maddu $7, $8 # disassembles as madu ...
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madd $5, $6
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maddu $7, $8
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msub $9, $10
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msubu $11, $12
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mul $13, $14, $15
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@ -58,6 +58,14 @@ text_label:
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wait 0 # disassembles without code
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wait 0x56789
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# padding to a cache line boundary so it's more likely to
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# pass everywhere
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nop
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# Instructions in previous ISAs or CPUs which are now slightly
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# different.
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break
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break 0 # disassembles without code
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break 0x12345
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sdbbp
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sdbbp 0 # disassembles without code
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sdbbp 0x56789
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# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
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.space 8
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@ -1,3 +1,11 @@
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2000-12-03 Ed Satterthwaite ehs@sibyte.com and
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Chris Demetriou cgd@sibyte.com
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* mips-opc.c (mips_builtin_opcodes): Finish additions
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for MIPS32 support, and clean up existing entries for
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aesthetics, consistency with the MIPS32 ISA, and
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with consistency the rest of the table.
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2000-12-01 Nick Clifton <nickc@redhat.com>
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* mips16-opc.c (mips16_opcodes): Add initialiser for membership
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@ -2,6 +2,7 @@
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Copyright 1993, 1994, 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
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Contributed by Ralph Campbell and OSF
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Commented and modified by Ian Lance Taylor, Cygnus Support
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Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc.
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This file is part of GDB, GAS, and the GNU binutils.
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@ -115,9 +116,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
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them first. The assemblers uses a hash table based on the
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instruction name anyhow. */
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/* name, args, match, mask, pinfo, membership */
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{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, G3|M1|I32},
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{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, I32|G3|M1},
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{"nop", "", 0x00000000, 0xffffffff, 0, I1 },
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{"ssnop", "", 0x00000040, 0xffffffff, 0, M1|I32 },
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{"ssnop", "", 0x00000040, 0xffffffff, 0, I32|M1 },
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{"li", "t,j", 0x24000000, 0xffe00000, WR_t, I1 }, /* addiu */
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{"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */
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{"li", "t,I", 0, (int) M_LI, INSN_MACRO, I1 },
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@ -129,31 +130,31 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"b", "p", 0x04010000, 0xffff0000, UBD, I1 },/* bgez 0 */
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{"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, I1 },/* bgezal 0*/
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{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, I1 },
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{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, I1 },
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{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, I1 },
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{"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, I5 },
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{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
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{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, I1 },
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{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1},
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{"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1},
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{"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5},
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{"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, I1 },
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{"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, I1 },
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{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
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{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, I1 },
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{"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, I5},
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{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
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{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, I1 },
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{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, I1 },
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{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, I1 },
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{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, I1 },
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{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, I1 },
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{"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, I5 },
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{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
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{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, I1 },
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{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
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{"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
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{"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
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{"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, I1 },
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{"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, I1 },
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{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
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{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, I1 },
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{"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, I5 },
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{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
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{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, I1 },
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{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, I1 },
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/* b is at the top of the table. */
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/* bal is at the top of the table. */
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{"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, I1 },
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{"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, I2|T3 },
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{"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, I1|M1 },
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{"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, I4|M1 },
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{"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, I4|I32|M1},
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{"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3|M1},
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{"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, I4|M1 },
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{"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, I4|I32|M1},
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{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, I1 },
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{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, I2|T3 },
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{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, I1 },
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@ -161,9 +162,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, I1 },
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{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, I2|T3 },
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{"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, I1 },
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{"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, I4|M1 },
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{"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, I4|I32|M1},
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{"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 },
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{"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, I4|M1 },
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{"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, I4|I32|M1},
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{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, I1 },
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{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, I2|T3 },
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{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, I1 },
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@ -229,361 +230,361 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"break", "c", 0x0000000d, 0xfc00ffff, TRAP, I1 },
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{"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, I1 },
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{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
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{"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
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{"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
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{"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
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{"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
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{"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
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{"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
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{"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
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{"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
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{"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
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{"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
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{"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
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{"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
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{"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
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{"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
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{"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
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{"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
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{"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
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{"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
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{"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
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{"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
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{"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
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{"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
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{"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
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{"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
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{"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
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{"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
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{"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
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{"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
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{"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
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{"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
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{"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
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{"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
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{"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
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{"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
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{"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
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{"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
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{"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
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{"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
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{"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
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{"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
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{"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
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{"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
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{"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
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{"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
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{"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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{"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
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||||
{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
|
||||
{"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
|
||||
{"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
|
||||
{"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
|
||||
{"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
|
||||
{"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
|
||||
{"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
|
||||
{"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
|
||||
{"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
|
||||
{"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
|
||||
{"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
|
||||
{"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
|
||||
{"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
|
||||
{"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
|
||||
{"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
|
||||
{"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
|
||||
{"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
|
||||
{"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
|
||||
{"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
|
||||
{"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
|
||||
{"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
|
||||
{"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
|
||||
{"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
|
||||
{"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
|
||||
{"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
|
||||
{"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
|
||||
{"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
|
||||
{"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
|
||||
{"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
|
||||
{"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
|
||||
{"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
|
||||
{"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
|
||||
{"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
|
||||
{"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
|
||||
{"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
|
||||
{"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
|
||||
{"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
|
||||
{"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
|
||||
{"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
|
||||
{"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
|
||||
{"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
|
||||
{"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
|
||||
{"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
|
||||
{"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
|
||||
{"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
|
||||
{"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
|
||||
{"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
|
||||
{"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
|
||||
{"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
|
||||
{"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
|
||||
{"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
|
||||
{"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
|
||||
{"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
|
||||
{"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
|
||||
{"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
|
||||
{"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
|
||||
{"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
|
||||
{"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
|
||||
{"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
|
||||
{"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
|
||||
{"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
|
||||
{"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
|
||||
{"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
|
||||
{"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32|M1},
|
||||
{"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
|
||||
{"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32|M1},
|
||||
{"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
|
||||
{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, I3|T3|M1|I32 },
|
||||
{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, I3 },
|
||||
{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, I3 },
|
||||
{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_D, I2 },
|
||||
{"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, I2 },
|
||||
{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, I1 },
|
||||
{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, I3|I32|T3|M1},
|
||||
{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, I3 },
|
||||
{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, I3 },
|
||||
{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_D, I2 },
|
||||
{"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, I2 },
|
||||
{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, I1 },
|
||||
{"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 },
|
||||
{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 },
|
||||
{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
|
||||
{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
|
||||
{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|RD_s, I32 },
|
||||
{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|RD_s, I32 },
|
||||
{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
|
||||
{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
|
||||
{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
|
||||
{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, I32 },
|
||||
{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, I32 },
|
||||
{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
|
||||
{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
|
||||
{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
|
||||
{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
|
||||
{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
|
||||
{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, I3 },
|
||||
{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
|
||||
{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
|
||||
{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, I3 },
|
||||
{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_D|FP_S, I1 },
|
||||
{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_D, I1 },
|
||||
{"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, I3 },
|
||||
{"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S, I3 },
|
||||
{"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S, I3 },
|
||||
{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_D, I1 },
|
||||
{"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, I3 },
|
||||
{"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S, I3 },
|
||||
{"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S, I3 },
|
||||
{"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I1 },
|
||||
{"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, I1 },
|
||||
{"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, I1 },
|
||||
{"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I5 },
|
||||
{"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I5 },
|
||||
{"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_D, I1 },
|
||||
{"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, I1 },
|
||||
{"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5},
|
||||
{"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, I3 },
|
||||
{"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
|
||||
{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, I3 },
|
||||
{"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, I3 },
|
||||
{"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, I3 },
|
||||
{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
|
||||
{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, I3 },
|
||||
{"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_D, I1 },
|
||||
{"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, I1 },
|
||||
{"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
|
||||
{"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, I3 },
|
||||
{"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
|
||||
{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, I3 },
|
||||
{"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, I3 },
|
||||
{"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, I3 },
|
||||
{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
|
||||
{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, I3 },
|
||||
/* dctr and dctw are used on the r5000. */
|
||||
{"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, I3 },
|
||||
{"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, I3 },
|
||||
{"deret", "", 0x4200001f, 0xffffffff, 0, G2|M1|I32 },
|
||||
{"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, I3 },
|
||||
{"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, I3 },
|
||||
{"deret", "", 0x4200001f, 0xffffffff, 0, I32|G2|M1},
|
||||
/* For ddiv, see the comments about div. */
|
||||
{"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
|
||||
{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, I3 },
|
||||
{"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, I3 },
|
||||
{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, I3 },
|
||||
{"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, I3 },
|
||||
/* For ddivu, see the comments about div. */
|
||||
{"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
|
||||
{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, I3 },
|
||||
{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, I3 },
|
||||
{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, I3 },
|
||||
{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, I3 },
|
||||
/* The MIPS assembler treats the div opcode with two operands as
|
||||
though the first operand appeared twice (the first operand is both
|
||||
a source and a destination). To get the div machine instruction,
|
||||
you must use an explicit destination of $0. */
|
||||
{"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
|
||||
{"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
|
||||
{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, I1 },
|
||||
{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, I1 },
|
||||
{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, I1 },
|
||||
{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, I1 },
|
||||
{"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
|
||||
{"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
|
||||
/* For divu, see the comments about div. */
|
||||
{"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
|
||||
{"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
|
||||
{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, I1 },
|
||||
{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, I1 },
|
||||
{"dla", "t,o(b)", 0x64000000, 0xfc000000, WR_t|RD_s, I3 }, /* daddiu */
|
||||
{"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, I3 },
|
||||
{"dli", "t,j", 0x24000000, 0xffe00000, WR_t, I3 }, /* addiu */
|
||||
{"dli", "t,i", 0x34000000, 0xffe00000, WR_t, I3 }, /* ori */
|
||||
{"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, I3 },
|
||||
{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, I1 },
|
||||
{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, I1 },
|
||||
{"dla", "t,o(b)", 0x64000000, 0xfc000000, WR_t|RD_s, I3 }, /* daddiu */
|
||||
{"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, I3 },
|
||||
{"dli", "t,j", 0x24000000, 0xffe00000, WR_t, I3 }, /* addiu */
|
||||
{"dli", "t,i", 0x34000000, 0xffe00000, WR_t, I3 }, /* ori */
|
||||
{"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, I3 },
|
||||
|
||||
{"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|WR_LO|RD_LO, V1 },
|
||||
{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, I3 },
|
||||
{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, I3 },
|
||||
{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I3 },
|
||||
{"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 },
|
||||
{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 },
|
||||
{"dmfc2", "t,S", 0x48200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 },
|
||||
{"dmtc2", "t,S", 0x48a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 },
|
||||
{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, I3 },
|
||||
{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, I3 },
|
||||
{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, I3 },
|
||||
{"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, I3 },
|
||||
{"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, I3 },
|
||||
{"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, I3 },
|
||||
{"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3},
|
||||
{"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3},
|
||||
{"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, I3 }, /* dsub 0 */
|
||||
{"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, I3 }, /* dsubu 0*/
|
||||
{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, I3 },
|
||||
{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, I3 },
|
||||
{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, I3 },
|
||||
{"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, I3 },
|
||||
{"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, I3 },
|
||||
{"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, I3 },
|
||||
{"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
|
||||
{"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
|
||||
{"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, I3 }, /* dsub 0 */
|
||||
{"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, I3 }, /* dsubu 0*/
|
||||
{"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
|
||||
{"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO, I3 },
|
||||
{"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO, I3 },
|
||||
{"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO, I3 },
|
||||
{"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO, I3 },
|
||||
{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I3 },
|
||||
{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 },
|
||||
{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 },
|
||||
{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
|
||||
{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 },
|
||||
{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */
|
||||
{"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 }, /* dsll32 */
|
||||
{"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, I3 },
|
||||
{"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
|
||||
{"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, I3 },
|
||||
{"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsrav */
|
||||
{"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, I3 }, /* dsra32 */
|
||||
{"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, I3 },
|
||||
{"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
|
||||
{"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, I3 },
|
||||
{"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsrlv */
|
||||
{"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, I3 }, /* dsrl32 */
|
||||
{"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, I3 },
|
||||
{"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
|
||||
{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, I3 },
|
||||
{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
|
||||
{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, I3 },
|
||||
{"eret", "", 0x42000018, 0xffffffff, 0, I3|M1|I32},
|
||||
{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, I3 },
|
||||
{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, I3 },
|
||||
{"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_D, I2 },
|
||||
{"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, I2 },
|
||||
{"flushi", "", 0xbc010000, 0xffffffff, 0, L1 },
|
||||
{"flushd", "", 0xbc020000, 0xffffffff, 0, L1 },
|
||||
{"flushid", "", 0xbc030000, 0xffffffff, 0, L1 },
|
||||
{"hibernate","", 0x42000023, 0xffffffff, 0, V1 },
|
||||
{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 },
|
||||
{"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 }, /* jr */
|
||||
{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 },
|
||||
{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 },
|
||||
{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
|
||||
{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 },
|
||||
{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */
|
||||
{"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 }, /* dsll32 */
|
||||
{"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, I3 },
|
||||
{"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
|
||||
{"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, I3 },
|
||||
{"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsrav */
|
||||
{"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, I3 }, /* dsra32 */
|
||||
{"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, I3 },
|
||||
{"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
|
||||
{"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, I3 },
|
||||
{"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsrlv */
|
||||
{"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, I3 }, /* dsrl32 */
|
||||
{"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, I3 },
|
||||
{"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
|
||||
{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, I3 },
|
||||
{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
|
||||
{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, I3 },
|
||||
{"eret", "", 0x42000018, 0xffffffff, 0, I3|I32|M1},
|
||||
{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, I3 },
|
||||
{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, I3 },
|
||||
{"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_D, I2 },
|
||||
{"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, I2 },
|
||||
{"flushi", "", 0xbc010000, 0xffffffff, 0, L1 },
|
||||
{"flushd", "", 0xbc020000, 0xffffffff, 0, L1 },
|
||||
{"flushid", "", 0xbc030000, 0xffffffff, 0, L1 },
|
||||
{"hibernate","", 0x42000023, 0xffffffff, 0, V1 },
|
||||
{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 },
|
||||
{"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 }, /* jr */
|
||||
/* SVR4 PIC code requires special handling for j, so it must be a
|
||||
macro. */
|
||||
{"j", "a", 0, (int) M_J_A, INSN_MACRO, I1 },
|
||||
{"j", "a", 0, (int) M_J_A, INSN_MACRO, I1 },
|
||||
/* This form of j is used by the disassembler and internally by the
|
||||
assembler, but will never match user input (because the line above
|
||||
will match first). */
|
||||
{"j", "a", 0x08000000, 0xfc000000, UBD, I1 },
|
||||
{"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, I1 },
|
||||
{"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, I1 },
|
||||
{"j", "a", 0x08000000, 0xfc000000, UBD, I1 },
|
||||
{"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, I1 },
|
||||
{"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, I1 },
|
||||
/* SVR4 PIC code requires special handling for jal, so it must be a
|
||||
macro. */
|
||||
{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, I1 },
|
||||
{"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, I1 },
|
||||
{"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, I1 },
|
||||
{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, I1 },
|
||||
{"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, I1 },
|
||||
{"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, I1 },
|
||||
/* This form of jal is used by the disassembler and internally by the
|
||||
assembler, but will never match user input (because the line above
|
||||
will match first). */
|
||||
{"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, I1 },
|
||||
{"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, I1 },
|
||||
/* jalx really should only be avaliable if mips16 is available,
|
||||
but for now make it I1. */
|
||||
{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, I1 },
|
||||
{"la", "t,o(b)", 0x24000000, 0xfc000000, WR_t|RD_s, I1 }, /* addiu */
|
||||
{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, I1 },
|
||||
{"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
|
||||
{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, I1 },
|
||||
{"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
|
||||
{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, I1 },
|
||||
{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, I3 },
|
||||
{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, I1 },
|
||||
{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, I1 },
|
||||
{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, I1 },
|
||||
{"la", "t,o(b)", 0x24000000, 0xfc000000, WR_t|RD_s, I1 }, /* addiu */
|
||||
{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, I1 },
|
||||
{"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
|
||||
{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, I1 },
|
||||
{"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
|
||||
{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, I1 },
|
||||
{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, I3 },
|
||||
{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, I1 },
|
||||
{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, I1 },
|
||||
{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 },
|
||||
{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 },
|
||||
{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, I2 },
|
||||
{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, I2 },
|
||||
{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, I2 },
|
||||
{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, I2 },
|
||||
{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 }, /* ldc1 */
|
||||
{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, I1 },
|
||||
{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, I1 },
|
||||
{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, I2 },
|
||||
{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, I2 },
|
||||
{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, I2 },
|
||||
{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, I2 },
|
||||
{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, I3 },
|
||||
{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, I3 },
|
||||
{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, I3 },
|
||||
{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, I3 },
|
||||
{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, I1 },
|
||||
{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, I1 },
|
||||
{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, I2 },
|
||||
{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, I2 },
|
||||
{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, I2 },
|
||||
{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, I2 },
|
||||
{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, I3 },
|
||||
{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, I3 },
|
||||
{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, I3 },
|
||||
{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, I3 },
|
||||
{"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 },
|
||||
{"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
|
||||
{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, I1 },
|
||||
{"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
|
||||
{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, I1 },
|
||||
{"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
|
||||
{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, I1 },
|
||||
{"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
|
||||
{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, I1 },
|
||||
/* li is at the start of the table. */
|
||||
{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, I1 },
|
||||
{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, I1 },
|
||||
{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, I1 },
|
||||
{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, I1 },
|
||||
{"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, I2 },
|
||||
{"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, I2 },
|
||||
{"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, I3 },
|
||||
{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, I3 },
|
||||
{"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, I1 },
|
||||
{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, I1 },
|
||||
{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, I1 },
|
||||
{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, I1 },
|
||||
{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, I1 },
|
||||
{"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, I2 },
|
||||
{"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, I2 },
|
||||
{"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, I3 },
|
||||
{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, I3 },
|
||||
{"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, I1 },
|
||||
{"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I5 },
|
||||
{"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
|
||||
{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, I1 },
|
||||
{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, I1 },
|
||||
{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, I1 },
|
||||
{"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
|
||||
{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, I1 },
|
||||
{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, I1 },
|
||||
{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, I1 },
|
||||
{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 },
|
||||
{"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 },
|
||||
{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 },
|
||||
{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 },
|
||||
{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 },
|
||||
{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 },
|
||||
{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 }, /* lwc1 */
|
||||
{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 },
|
||||
{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, I1 },
|
||||
{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, I1 },
|
||||
{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, I1 },
|
||||
{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, I1 },
|
||||
{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
|
||||
{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, I1 },
|
||||
{"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */
|
||||
{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, I2 }, /* as lwl */
|
||||
{"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
|
||||
{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, I1 },
|
||||
{"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */
|
||||
{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, I2 }, /* as lwr */
|
||||
{"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, I3 },
|
||||
{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, I3 },
|
||||
{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 },
|
||||
{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, I1 },
|
||||
{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, I1 },
|
||||
{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, I1 },
|
||||
{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, I1 },
|
||||
{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
|
||||
{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, I1 },
|
||||
{"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */
|
||||
{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, I2 }, /* as lwl */
|
||||
{"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
|
||||
{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, I1 },
|
||||
{"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */
|
||||
{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, I2 }, /* as lwr */
|
||||
{"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, I3 },
|
||||
{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, I3 },
|
||||
{"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 },
|
||||
{"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3|I32 },
|
||||
{"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3|I32 },
|
||||
{"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
|
||||
{"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
|
||||
{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
|
||||
{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 },
|
||||
{"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3 },
|
||||
{"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, P3 },
|
||||
{"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
|
||||
{"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
|
||||
{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
|
||||
{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 },
|
||||
{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, I32 },
|
||||
{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, G1|M1 },
|
||||
{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, G1|M1 },
|
||||
{"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1 },
|
||||
{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 },
|
||||
{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 },
|
||||
{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, I32 },
|
||||
{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, G1|M1},
|
||||
{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1},
|
||||
{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, G1|M1 },
|
||||
{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1 },
|
||||
{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, V1 },
|
||||
{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1 },
|
||||
{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, I32 },
|
||||
{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1},
|
||||
{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1},
|
||||
{"mfc1", "t,G,H", 0x44000000, 0xffe007f8, LCD|WR_t|RD_S|FP_S, I32},
|
||||
{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
|
||||
{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, I32 },
|
||||
{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
|
||||
{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, I32 },
|
||||
{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, I1 },
|
||||
{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, I1 },
|
||||
{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, I1 },
|
||||
{"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, I1 },
|
||||
{"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, I5 },
|
||||
{"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_D|FP_S, I4|M1},
|
||||
{"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|M1 },
|
||||
{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|M1 },
|
||||
{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1 },
|
||||
{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, I32 },
|
||||
{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 },
|
||||
{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 },
|
||||
{"mfc1", "t,G,H", 0x44000000, 0xffe007f8, LCD|WR_t|RD_S|FP_S, I32 },
|
||||
{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
|
||||
{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, I32 },
|
||||
{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
|
||||
{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, I32 },
|
||||
{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, I1 },
|
||||
{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, I1 },
|
||||
{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, I1 },
|
||||
{"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, I1 },
|
||||
{"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, I5 },
|
||||
{"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_D|FP_S, I4|I32|M1},
|
||||
{"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|I32|M1},
|
||||
{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|I32|M1},
|
||||
{"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5 },
|
||||
{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1|I32 },
|
||||
{"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s,L1 },
|
||||
{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|M1 },
|
||||
{"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|M1 },
|
||||
{"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC, I4|M1 },
|
||||
{"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|M1 },
|
||||
{"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|M1 },
|
||||
{"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5},
|
||||
{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1|I32 },
|
||||
{"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s,L1 },
|
||||
{"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|M1 },
|
||||
{"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|M1 },
|
||||
{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4|I32|M1},
|
||||
{"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, L1 },
|
||||
{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|I32|M1},
|
||||
{"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|I32|M1},
|
||||
{"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC, I4|I32|M1},
|
||||
{"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|I32|M1},
|
||||
{"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|I32|M1},
|
||||
{"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5 },
|
||||
{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4|I32|M1},
|
||||
{"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, L1 },
|
||||
{"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|I32|M1},
|
||||
{"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|I32|M1},
|
||||
/* move is at the top of the table. */
|
||||
{"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
|
||||
{"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
|
||||
{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
|
||||
{"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1 },
|
||||
{"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 },
|
||||
{"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, I32 },
|
||||
{"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,L1 },
|
||||
{"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, L1 },
|
||||
{"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, I32 },
|
||||
{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I1 },
|
||||
{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I32 },
|
||||
|
|
@ -594,27 +595,27 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, I32 },
|
||||
{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I1 },
|
||||
{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, I32 },
|
||||
{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, I1 },
|
||||
{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, I1 },
|
||||
{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, I1 },
|
||||
{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, I1 },
|
||||
{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
|
||||
{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
|
||||
{"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
|
||||
{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, P3|I32 },
|
||||
{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, I1 },
|
||||
{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, I1 },
|
||||
{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, I1 },
|
||||
{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, I1 },
|
||||
{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, I1 },
|
||||
{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, I1 },
|
||||
{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HI|WR_LO, I32|P3 },
|
||||
{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, I1 },
|
||||
{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, I1 },
|
||||
{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, I1 },
|
||||
{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, I1 },
|
||||
{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, I1 },
|
||||
{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, I1 },
|
||||
{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, I1},
|
||||
{"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1},
|
||||
{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M, I1},
|
||||
{"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1},
|
||||
{"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, I1 }, /* sub 0 */
|
||||
{"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, I1 }, /* subu 0 */
|
||||
{"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, I1 },
|
||||
{"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, I1 },
|
||||
{"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D,I5 },
|
||||
{"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, I1 }, /* sub 0 */
|
||||
{"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, I1 }, /* subu 0 */
|
||||
{"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, I1 },
|
||||
{"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, I1 },
|
||||
{"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D, I5 },
|
||||
{"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
|
||||
{"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
|
||||
{"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
|
||||
|
|
@ -629,21 +630,21 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, I1 },
|
||||
{"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, I1 },
|
||||
|
||||
{"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5},
|
||||
{"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5},
|
||||
{"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
|
||||
{"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
|
||||
|
||||
/* pref is at the start of the table. */
|
||||
{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 },
|
||||
|
||||
{"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5},
|
||||
{"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5},
|
||||
{"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
|
||||
{"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
|
||||
|
||||
{"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, I4 },
|
||||
{"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, I4 },
|
||||
{"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
|
||||
{"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
|
||||
{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, I1 },
|
||||
{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, I1 },
|
||||
{"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
|
||||
{"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO, I1 },
|
||||
{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, I1 },
|
||||
{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, I1 },
|
||||
{"rfe", "", 0x42000010, 0xffffffff, 0, I1|T3 },
|
||||
|
|
@ -669,6 +670,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, G2|M1 },
|
||||
{"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, G2|M1 },
|
||||
{"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, G2|M1 },
|
||||
{"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, I32 },
|
||||
{"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, I32 },
|
||||
{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
|
||||
{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
|
||||
|
|
@ -760,8 +762,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC, I2|G1 },
|
||||
{"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, I2 },
|
||||
{"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, I2 },
|
||||
{"syscall", "", 0x0000000c, 0xffffffff, TRAP, I1 },
|
||||
{"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, I1 },
|
||||
{"syscall", "", 0x0000000c, 0xffffffff, TRAP, I1 },
|
||||
{"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, I1 },
|
||||
{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, I2 },
|
||||
{"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
|
||||
{"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
|
||||
|
|
@ -772,29 +774,29 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
|
||||
{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgei */
|
||||
{"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, I2 },
|
||||
{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 },
|
||||
{"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
|
||||
{"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
|
||||
{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgeiu */
|
||||
{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 },
|
||||
{"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
|
||||
{"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
|
||||
{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgeiu */
|
||||
{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, I2 },
|
||||
{"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, I1|M1|I32 },
|
||||
{"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, I1|M1|I32 },
|
||||
{"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, I1|M1|I32 },
|
||||
{"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, I1|M1|I32 },
|
||||
{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 },
|
||||
{"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
|
||||
{"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
|
||||
{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tlti */
|
||||
{"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, I1|M1 },
|
||||
{"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, I1|M1 },
|
||||
{"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, I1|M1 },
|
||||
{"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, I1|M1 },
|
||||
{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 },
|
||||
{"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
|
||||
{"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
|
||||
{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tlti */
|
||||
{"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, I2 },
|
||||
{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 },
|
||||
{"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
|
||||
{"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
|
||||
{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tltiu */
|
||||
{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 },
|
||||
{"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
|
||||
{"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
|
||||
{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tltiu */
|
||||
{"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, I2 },
|
||||
{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 },
|
||||
{"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
|
||||
{"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
|
||||
{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tnei */
|
||||
{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 },
|
||||
{"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
|
||||
{"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
|
||||
{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tnei */
|
||||
{"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, I2 },
|
||||
{"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, I3 },
|
||||
{"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S, I3 },
|
||||
|
|
@ -821,18 +823,18 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
|
||||
{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, I1 },
|
||||
{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 },
|
||||
{"wait", "", 0x42000020, 0xffffffff, TRAP, I3|M1|I32 },
|
||||
{"wait", "J", 0x42000020, 0xfe00003f, TRAP, I32 },
|
||||
{"waiti", "", 0x42000020, 0xffffffff, TRAP, L1 },
|
||||
{"wait", "", 0x42000020, 0xffffffff, TRAP, I3|I32|M1},
|
||||
{"wait", "J", 0x42000020, 0xfe00003f, TRAP, I32 },
|
||||
{"waiti", "", 0x42000020, 0xffffffff, TRAP, L1 },
|
||||
{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, L1 },
|
||||
/* No hazard protection on coprocessor instructions--they shouldn't
|
||||
change the state of the processor and if they do it's up to the
|
||||
user to put in nops as necessary. These are at the end so that the
|
||||
disasembler recognizes more specific versions first. */
|
||||
{"c0", "C", 0x42000000, 0xfe000000, 0, I1 },
|
||||
{"c1", "C", 0x46000000, 0xfe000000, 0, I1 },
|
||||
{"c2", "C", 0x4a000000, 0xfe000000, 0, I1 },
|
||||
{"c3", "C", 0x4e000000, 0xfe000000, 0, I1 },
|
||||
{"c0", "C", 0x42000000, 0xfe000000, 0, I1 },
|
||||
{"c1", "C", 0x46000000, 0xfe000000, 0, I1 },
|
||||
{"c2", "C", 0x4a000000, 0xfe000000, 0, I1 },
|
||||
{"c3", "C", 0x4e000000, 0xfe000000, 0, I1 },
|
||||
{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, I1 },
|
||||
{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, I1 },
|
||||
{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, I1 },
|
||||
|
|
@ -841,7 +843,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
/* Conflicts with the 4650's "mul" instruction. Nobody's using the
|
||||
4010 any more, so move this insn out of the way. If the object
|
||||
format gave us more info, we could do this right. */
|
||||
{"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s,L1 },
|
||||
{"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s, L1 },
|
||||
};
|
||||
|
||||
#define MIPS_NUM_OPCODES \
|
||||
|
|
|
|||
Loading…
Reference in New Issue