opcodes/
* Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove special rules. * Makefile.in: Regenerate. * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize all fields. Reformat.
This commit is contained in:
Richard Sandiford
parent
a92713e60e
commit
e7ae278d04
@ -1,3 +1,11 @@
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2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
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* Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
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special rules.
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* Makefile.in: Regenerate.
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* mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
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all fields. Reformat.
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2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
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2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
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* mips16-opc.c: Include mips-formats.h.
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* mips16-opc.c: Include mips-formats.h.
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@ -577,45 +577,6 @@ $(srcdir)/msp430-decode.c: @MAINT@ $(srcdir)/msp430-decode.opc opc2c$(EXEEXT_FOR
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$(srcdir)/rl78-decode.c: @MAINT@ $(srcdir)/rl78-decode.opc opc2c$(EXEEXT_FOR_BUILD)
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$(srcdir)/rl78-decode.c: @MAINT@ $(srcdir)/rl78-decode.opc opc2c$(EXEEXT_FOR_BUILD)
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./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rl78-decode.opc > $(srcdir)/rl78-decode.c
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./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rl78-decode.opc > $(srcdir)/rl78-decode.c
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micromips-opc.lo: micromips-opc.c
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if am__fastdepCC
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$(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) \
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-MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ @archdefs@ $<
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mv -f $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Plo
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else
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if AMDEP
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source='$<' object='$@' libtool=yes @AMDEPBACKSLASH@
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DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
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endif
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$(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ @archdefs@ $<
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endif
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mips-opc.lo: mips-opc.c
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if am__fastdepCC
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$(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) \
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-MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ @archdefs@ $<
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mv -f $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Plo
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else
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if AMDEP
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source='$<' object='$@' libtool=yes @AMDEPBACKSLASH@
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DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
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endif
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$(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ @archdefs@ $<
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endif
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mips16-opc.lo: mips16-opc.c
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if am__fastdepCC
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$(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) \
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-MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ @archdefs@ $<
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mv -f $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Plo
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else
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if AMDEP
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source='$<' object='$@' libtool=yes @AMDEPBACKSLASH@
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DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
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endif
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$(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ @archdefs@ $<
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endif
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$(srcdir)/rx-decode.c: @MAINT@ $(srcdir)/rx-decode.opc opc2c$(EXEEXT_FOR_BUILD)
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$(srcdir)/rx-decode.c: @MAINT@ $(srcdir)/rx-decode.opc opc2c$(EXEEXT_FOR_BUILD)
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./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rx-decode.opc > $(srcdir)/rx-decode.c
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./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rx-decode.opc > $(srcdir)/rx-decode.c
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@ -1438,30 +1438,6 @@ $(srcdir)/msp430-decode.c: @MAINT@ $(srcdir)/msp430-decode.opc opc2c$(EXEEXT_FOR
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$(srcdir)/rl78-decode.c: @MAINT@ $(srcdir)/rl78-decode.opc opc2c$(EXEEXT_FOR_BUILD)
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$(srcdir)/rl78-decode.c: @MAINT@ $(srcdir)/rl78-decode.opc opc2c$(EXEEXT_FOR_BUILD)
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./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rl78-decode.opc > $(srcdir)/rl78-decode.c
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./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rl78-decode.opc > $(srcdir)/rl78-decode.c
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micromips-opc.lo: micromips-opc.c
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@am__fastdepCC_TRUE@ $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) \
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@am__fastdepCC_TRUE@ -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ @archdefs@ $<
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@am__fastdepCC_TRUE@ mv -f $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Plo
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@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=yes @AMDEPBACKSLASH@
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@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
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@am__fastdepCC_FALSE@ $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ @archdefs@ $<
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mips-opc.lo: mips-opc.c
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@am__fastdepCC_TRUE@ $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) \
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@am__fastdepCC_TRUE@ -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ @archdefs@ $<
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@am__fastdepCC_TRUE@ mv -f $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Plo
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@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=yes @AMDEPBACKSLASH@
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@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
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@am__fastdepCC_FALSE@ $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ @archdefs@ $<
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mips16-opc.lo: mips16-opc.c
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@am__fastdepCC_TRUE@ $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) \
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@am__fastdepCC_TRUE@ -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ @archdefs@ $<
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@am__fastdepCC_TRUE@ mv -f $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Plo
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@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=yes @AMDEPBACKSLASH@
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@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
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@am__fastdepCC_FALSE@ $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ @archdefs@ $<
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$(srcdir)/rx-decode.c: @MAINT@ $(srcdir)/rx-decode.opc opc2c$(EXEEXT_FOR_BUILD)
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$(srcdir)/rx-decode.c: @MAINT@ $(srcdir)/rx-decode.opc opc2c$(EXEEXT_FOR_BUILD)
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./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rx-decode.opc > $(srcdir)/rx-decode.c
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./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rx-decode.opc > $(srcdir)/rx-decode.c
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File diff suppressed because it is too large
Load Diff
3986
opcodes/mips-opc.c
3986
opcodes/mips-opc.c
File diff suppressed because it is too large
Load Diff
@ -179,183 +179,183 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
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const struct mips_opcode mips16_opcodes[] =
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const struct mips_opcode mips16_opcodes[] =
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{
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{
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/* name, args, match, mask, pinfo, pinfo2, membership */
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/* name, args, match, mask, pinfo, pinfo2, membership */
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{"nop", "", 0x6500, 0xffff, RD_Z, 0, I1 }, /* move $0,$Z */
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{"nop", "", 0x6500, 0xffff, RD_Z, 0, I1, 0, 0 }, /* move $0,$Z */
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{"la", "x,A", 0x0800, 0xf800, WR_x|RD_PC, 0, I1 },
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{"la", "x,A", 0x0800, 0xf800, WR_x|RD_PC, 0, I1, 0, 0 },
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{"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0, I1 },
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{"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 },
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{"addiu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0, I1 },
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{"addiu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0, I1, 0, 0 },
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{"addiu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0, I1 },
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{"addiu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0, I1, 0, 0 },
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{"addiu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, I1 },
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{"addiu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, I1, 0, 0 },
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{"addiu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, I1 },
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{"addiu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, I1, 0, 0 },
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{"addiu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0, I1 },
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{"addiu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0, I1, 0, 0 },
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{"addiu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0, I1 },
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{"addiu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0, I1, 0, 0 },
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{"addu", "z,v,y", 0xe001, 0xf803, WR_z|RD_x|RD_y, 0, I1 },
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{"addu", "z,v,y", 0xe001, 0xf803, WR_z|RD_x|RD_y, 0, I1, 0, 0 },
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{"addu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0, I1 },
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{"addu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0, I1, 0, 0 },
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{"addu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0, I1 },
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{"addu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0, I1, 0, 0 },
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{"addu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, I1 },
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{"addu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, I1, 0, 0 },
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{"addu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, I1 },
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{"addu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, I1, 0, 0 },
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{"addu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0, I1 },
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{"addu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0, I1, 0, 0 },
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{"addu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0, I1 },
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{"addu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0, I1, 0, 0 },
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{"and", "x,y", 0xe80c, 0xf81f, WR_x|RD_x|RD_y, 0, I1 },
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{"and", "x,y", 0xe80c, 0xf81f, WR_x|RD_x|RD_y, 0, I1, 0, 0 },
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{"b", "q", 0x1000, 0xf800, UBR, 0, I1 },
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{"b", "q", 0x1000, 0xf800, UBR, 0, I1, 0, 0 },
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{"beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO, 0, I1 },
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{"beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO, 0, I1, 0, 0 },
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{"beq", "x,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1 },
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{"beq", "x,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1, 0, 0 },
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{"beqz", "x,p", 0x2000, 0xf800, CBR|RD_x, 0, I1 },
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{"beqz", "x,p", 0x2000, 0xf800, CBR|RD_x, 0, I1, 0, 0 },
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{"bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO, 0, I1 },
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{"bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO, 0, I1, 0, 0 },
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{"bge", "x,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1 },
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{"bge", "x,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1, 0, 0 },
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{"bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1 },
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{"bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1, 0, 0 },
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{"bgeu", "x,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1 },
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{"bgeu", "x,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1, 0, 0 },
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{"bgt", "x,y,p", 0, (int) M_BGT, INSN_MACRO, 0, I1 },
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{"bgt", "x,y,p", 0, (int) M_BGT, INSN_MACRO, 0, I1, 0, 0 },
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{"bgt", "x,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1 },
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{"bgt", "x,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1, 0, 0 },
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{"bgtu", "x,y,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1 },
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{"bgtu", "x,y,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1, 0, 0 },
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{"bgtu", "x,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1 },
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{"bgtu", "x,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1, 0, 0 },
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{"ble", "x,y,p", 0, (int) M_BLE, INSN_MACRO, 0, I1 },
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{"ble", "x,y,p", 0, (int) M_BLE, INSN_MACRO, 0, I1, 0, 0 },
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{"ble", "x,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1 },
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{"ble", "x,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1, 0, 0 },
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{"bleu", "x,y,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1 },
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{"bleu", "x,y,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1, 0, 0 },
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{"bleu", "x,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1 },
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{"bleu", "x,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1, 0, 0 },
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{"blt", "x,y,p", 0, (int) M_BLT, INSN_MACRO, 0, I1 },
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{"blt", "x,y,p", 0, (int) M_BLT, INSN_MACRO, 0, I1, 0, 0 },
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{"blt", "x,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1 },
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{"blt", "x,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1, 0, 0 },
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{"bltu", "x,y,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1 },
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{"bltu", "x,y,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1, 0, 0 },
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{"bltu", "x,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1 },
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{"bltu", "x,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1, 0, 0 },
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{"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0, I1 },
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{"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0, I1, 0, 0 },
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{"bne", "x,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1 },
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{"bne", "x,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1, 0, 0 },
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{"bnez", "x,p", 0x2800, 0xf800, CBR|RD_x, 0, I1 },
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{"bnez", "x,p", 0x2800, 0xf800, CBR|RD_x, 0, I1, 0, 0 },
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{"break", "6", 0xe805, 0xf81f, TRAP, 0, I1 },
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{"break", "6", 0xe805, 0xf81f, TRAP, 0, I1, 0, 0 },
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{"bteqz", "p", 0x6000, 0xff00, CBR|RD_T, 0, I1 },
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{"bteqz", "p", 0x6000, 0xff00, CBR|RD_T, 0, I1, 0, 0 },
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{"btnez", "p", 0x6100, 0xff00, CBR|RD_T, 0, I1 },
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{"btnez", "p", 0x6100, 0xff00, CBR|RD_T, 0, I1, 0, 0 },
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{"cmpi", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0, I1 },
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{"cmpi", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0, I1, 0, 0 },
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{"cmp", "x,y", 0xe80a, 0xf81f, WR_T|RD_x|RD_y, 0, I1 },
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{"cmp", "x,y", 0xe80a, 0xf81f, WR_T|RD_x|RD_y, 0, I1, 0, 0 },
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{"cmp", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0, I1 },
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{"cmp", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0, I1, 0, 0 },
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{"dla", "y,E", 0xfe00, 0xff00, WR_y|RD_PC, 0, I3 },
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{"dla", "y,E", 0xfe00, 0xff00, WR_y|RD_PC, 0, I3, 0, 0 },
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{"daddiu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, 0, I3 },
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{"daddiu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, 0, I3, 0, 0 },
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{"daddiu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, 0, I3 },
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{"daddiu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, 0, I3, 0, 0 },
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{"daddiu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3 },
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{"daddiu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3, 0, 0 },
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{"daddiu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3 },
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{"daddiu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3, 0, 0 },
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{"daddiu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, 0, I3 },
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{"daddiu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, 0, I3, 0, 0 },
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{"daddiu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, 0, I3 },
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{"daddiu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, 0, I3, 0, 0 },
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{"daddu", "z,v,y", 0xe000, 0xf803, WR_z|RD_x|RD_y, 0, I3 },
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{"daddu", "z,v,y", 0xe000, 0xf803, WR_z|RD_x|RD_y, 0, I3, 0, 0 },
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{"daddu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, 0, I3 },
|
{"daddu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, 0, I3, 0, 0 },
|
||||||
{"daddu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, 0, I3 },
|
{"daddu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, 0, I3, 0, 0 },
|
||||||
{"daddu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3 },
|
{"daddu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3, 0, 0 },
|
||||||
{"daddu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3 },
|
{"daddu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3, 0, 0 },
|
||||||
{"daddu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, 0, I3 },
|
{"daddu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, 0, I3, 0, 0 },
|
||||||
{"daddu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, 0, I3 },
|
{"daddu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, 0, I3, 0, 0 },
|
||||||
{"ddiv", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 },
|
{"ddiv", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3, 0, 0 },
|
||||||
{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0, I1 },
|
{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0, I1, 0, 0 },
|
||||||
{"ddivu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 },
|
{"ddivu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3, 0, 0 },
|
||||||
{"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I1 },
|
{"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I1, 0, 0 },
|
||||||
{"div", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1 },
|
{"div", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1, 0, 0 },
|
||||||
{"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0, I1 },
|
{"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, 0 },
|
||||||
{"divu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1 },
|
{"divu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1, 0, 0 },
|
||||||
{"divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1 },
|
{"divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1, 0, 0 },
|
||||||
{"dmul", "z,v,y", 0, (int) M_DMUL, INSN_MACRO, 0, I3 },
|
{"dmul", "z,v,y", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, 0 },
|
||||||
{"dmult", "x,y", 0xe81c, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 },
|
{"dmult", "x,y", 0xe81c, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3, 0, 0 },
|
||||||
{"dmultu", "x,y", 0xe81d, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 },
|
{"dmultu", "x,y", 0xe81d, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3, 0, 0 },
|
||||||
{"drem", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 },
|
{"drem", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3, 0, 0 },
|
||||||
{"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0, I1 },
|
{"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0, I1, 0, 0 },
|
||||||
{"dremu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 },
|
{"dremu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3, 0, 0 },
|
||||||
{"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0, I1 },
|
{"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0, I1, 0, 0 },
|
||||||
{"dsllv", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
|
{"dsllv", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, 0, I3, 0, 0 },
|
||||||
{"dsll", "x,w,[", 0x3001, 0xf803, WR_x|RD_y, 0, I3 },
|
{"dsll", "x,w,[", 0x3001, 0xf803, WR_x|RD_y, 0, I3, 0, 0 },
|
||||||
{"dsll", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
|
{"dsll", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, 0, I3, 0, 0 },
|
||||||
{"dsrav", "y,x", 0xe817, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
|
{"dsrav", "y,x", 0xe817, 0xf81f, WR_y|RD_y|RD_x, 0, I3, 0, 0 },
|
||||||
{"dsra", "y,]", 0xe813, 0xf81f, WR_y|RD_y, 0, I3 },
|
{"dsra", "y,]", 0xe813, 0xf81f, WR_y|RD_y, 0, I3, 0, 0 },
|
||||||
{"dsra", "y,x", 0xe817, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
|
{"dsra", "y,x", 0xe817, 0xf81f, WR_y|RD_y|RD_x, 0, I3, 0, 0 },
|
||||||
{"dsrlv", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
|
{"dsrlv", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, 0, I3, 0, 0 },
|
||||||
{"dsrl", "y,]", 0xe808, 0xf81f, WR_y|RD_y, 0, I3 },
|
{"dsrl", "y,]", 0xe808, 0xf81f, WR_y|RD_y, 0, I3, 0, 0 },
|
||||||
{"dsrl", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
|
{"dsrl", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, 0, I3, 0, 0 },
|
||||||
{"dsubu", "z,v,y", 0xe002, 0xf803, WR_z|RD_x|RD_y, 0, I3 },
|
{"dsubu", "z,v,y", 0xe002, 0xf803, WR_z|RD_x|RD_y, 0, I3, 0, 0 },
|
||||||
{"dsubu", "y,x,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I1 },
|
{"dsubu", "y,x,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I1, 0, 0 },
|
||||||
{"dsubu", "y,I", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0, I1 },
|
{"dsubu", "y,I", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0, I1, 0, 0 },
|
||||||
{"exit", "L", 0xed09, 0xff1f, TRAP, 0, I1 },
|
{"exit", "L", 0xed09, 0xff1f, TRAP, 0, I1, 0, 0 },
|
||||||
{"exit", "L", 0xee09, 0xff1f, TRAP, 0, I1 },
|
{"exit", "L", 0xee09, 0xff1f, TRAP, 0, I1, 0, 0 },
|
||||||
{"exit", "", 0xef09, 0xffff, TRAP, 0, I1 },
|
{"exit", "", 0xef09, 0xffff, TRAP, 0, I1, 0, 0 },
|
||||||
{"exit", "L", 0xef09, 0xff1f, TRAP, 0, I1 },
|
{"exit", "L", 0xef09, 0xff1f, TRAP, 0, I1, 0, 0 },
|
||||||
{"entry", "", 0xe809, 0xffff, TRAP, 0, I1 },
|
{"entry", "", 0xe809, 0xffff, TRAP, 0, I1, 0, 0 },
|
||||||
{"entry", "l", 0xe809, 0xf81f, TRAP, 0, I1 },
|
{"entry", "l", 0xe809, 0xf81f, TRAP, 0, I1, 0, 0 },
|
||||||
{"extend", "e", 0xf000, 0xf800, 0, 0, I1 },
|
{"extend", "e", 0xf000, 0xf800, 0, 0, I1, 0, 0 },
|
||||||
{"jalr", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, I1 },
|
{"jalr", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, I1, 0, 0 },
|
||||||
{"jalr", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, I1 },
|
{"jalr", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, I1, 0, 0 },
|
||||||
{"jal", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, I1 },
|
{"jal", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, I1, 0, 0 },
|
||||||
{"jal", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, I1 },
|
{"jal", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, I1, 0, 0 },
|
||||||
{"jal", "a", 0x1800, 0xfc00, UBD|WR_31, 0, I1 },
|
{"jal", "a", 0x1800, 0xfc00, UBD|WR_31, 0, I1, 0, 0 },
|
||||||
{"jalx", "i", 0x1c00, 0xfc00, UBD|WR_31, 0, I1 },
|
{"jalx", "i", 0x1c00, 0xfc00, UBD|WR_31, 0, I1, 0, 0 },
|
||||||
{"jr", "x", 0xe800, 0xf8ff, UBD|RD_x, 0, I1 },
|
{"jr", "x", 0xe800, 0xf8ff, UBD|RD_x, 0, I1, 0, 0 },
|
||||||
{"jr", "R", 0xe820, 0xffff, UBD|RD_31, 0, I1 },
|
{"jr", "R", 0xe820, 0xffff, UBD|RD_31, 0, I1, 0, 0 },
|
||||||
{"j", "x", 0xe800, 0xf8ff, UBD|RD_x, 0, I1 },
|
{"j", "x", 0xe800, 0xf8ff, UBD|RD_x, 0, I1, 0, 0 },
|
||||||
{"j", "R", 0xe820, 0xffff, UBD|RD_31, 0, I1 },
|
{"j", "R", 0xe820, 0xffff, UBD|RD_31, 0, I1, 0, 0 },
|
||||||
/* MIPS16e compact branches. We keep them near the ordinary branches
|
/* MIPS16e compact branches. We keep them near the ordinary branches
|
||||||
so that we easily find them when converting a normal branch to a
|
so that we easily find them when converting a normal branch to a
|
||||||
compact one. */
|
compact one. */
|
||||||
{"jalrc", "x", 0xe8c0, 0xf8ff, UBR|WR_31|RD_x|NODS, 0, I32 },
|
{"jalrc", "x", 0xe8c0, 0xf8ff, UBR|WR_31|RD_x|NODS, 0, I32, 0, 0 },
|
||||||
{"jalrc", "R,x", 0xe8c0, 0xf8ff, UBR|WR_31|RD_x|NODS, 0, I32 },
|
{"jalrc", "R,x", 0xe8c0, 0xf8ff, UBR|WR_31|RD_x|NODS, 0, I32, 0, 0 },
|
||||||
{"jrc", "x", 0xe880, 0xf8ff, UBR|RD_x|NODS, 0, I32 },
|
{"jrc", "x", 0xe880, 0xf8ff, UBR|RD_x|NODS, 0, I32, 0, 0 },
|
||||||
{"jrc", "R", 0xe8a0, 0xffff, UBR|RD_31|NODS, 0, I32 },
|
{"jrc", "R", 0xe8a0, 0xffff, UBR|RD_31|NODS, 0, I32, 0, 0 },
|
||||||
{"lb", "y,5(x)", 0x8000, 0xf800, WR_y|RD_x, 0, I1 },
|
{"lb", "y,5(x)", 0x8000, 0xf800, WR_y|RD_x, 0, I1, 0, 0 },
|
||||||
{"lbu", "y,5(x)", 0xa000, 0xf800, WR_y|RD_x, 0, I1 },
|
{"lbu", "y,5(x)", 0xa000, 0xf800, WR_y|RD_x, 0, I1, 0, 0 },
|
||||||
{"ld", "y,D(x)", 0x3800, 0xf800, WR_y|RD_x, 0, I3 },
|
{"ld", "y,D(x)", 0x3800, 0xf800, WR_y|RD_x, 0, I3, 0, 0 },
|
||||||
{"ld", "y,B", 0xfc00, 0xff00, WR_y|RD_PC, 0, I3 },
|
{"ld", "y,B", 0xfc00, 0xff00, WR_y|RD_PC, 0, I3, 0, 0 },
|
||||||
{"ld", "y,D(P)", 0xfc00, 0xff00, WR_y|RD_PC, 0, I3 },
|
{"ld", "y,D(P)", 0xfc00, 0xff00, WR_y|RD_PC, 0, I3, 0, 0 },
|
||||||
{"ld", "y,D(S)", 0xf800, 0xff00, WR_y|RD_SP, 0, I3 },
|
{"ld", "y,D(S)", 0xf800, 0xff00, WR_y|RD_SP, 0, I3, 0, 0 },
|
||||||
{"lh", "y,H(x)", 0x8800, 0xf800, WR_y|RD_x, 0, I1 },
|
{"lh", "y,H(x)", 0x8800, 0xf800, WR_y|RD_x, 0, I1, 0, 0 },
|
||||||
{"lhu", "y,H(x)", 0xa800, 0xf800, WR_y|RD_x, 0, I1 },
|
{"lhu", "y,H(x)", 0xa800, 0xf800, WR_y|RD_x, 0, I1, 0, 0 },
|
||||||
{"li", "x,U", 0x6800, 0xf800, WR_x, 0, I1 },
|
{"li", "x,U", 0x6800, 0xf800, WR_x, 0, I1, 0, 0 },
|
||||||
{"lw", "y,W(x)", 0x9800, 0xf800, WR_y|RD_x, 0, I1 },
|
{"lw", "y,W(x)", 0x9800, 0xf800, WR_y|RD_x, 0, I1, 0, 0 },
|
||||||
{"lw", "x,A", 0xb000, 0xf800, WR_x|RD_PC, 0, I1 },
|
{"lw", "x,A", 0xb000, 0xf800, WR_x|RD_PC, 0, I1, 0, 0 },
|
||||||
{"lw", "x,V(P)", 0xb000, 0xf800, WR_x|RD_PC, 0, I1 },
|
{"lw", "x,V(P)", 0xb000, 0xf800, WR_x|RD_PC, 0, I1, 0, 0 },
|
||||||
{"lw", "x,V(S)", 0x9000, 0xf800, WR_x|RD_SP, 0, I1 },
|
{"lw", "x,V(S)", 0x9000, 0xf800, WR_x|RD_SP, 0, I1, 0, 0 },
|
||||||
{"lwu", "y,W(x)", 0xb800, 0xf800, WR_y|RD_x, 0, I3 },
|
{"lwu", "y,W(x)", 0xb800, 0xf800, WR_y|RD_x, 0, I3, 0, 0 },
|
||||||
{"mfhi", "x", 0xe810, 0xf8ff, WR_x|RD_HI, 0, I1 },
|
{"mfhi", "x", 0xe810, 0xf8ff, WR_x|RD_HI, 0, I1, 0, 0 },
|
||||||
{"mflo", "x", 0xe812, 0xf8ff, WR_x|RD_LO, 0, I1 },
|
{"mflo", "x", 0xe812, 0xf8ff, WR_x|RD_LO, 0, I1, 0, 0 },
|
||||||
{"move", "y,X", 0x6700, 0xff00, WR_y|RD_X, 0, I1 },
|
{"move", "y,X", 0x6700, 0xff00, WR_y|RD_X, 0, I1, 0, 0 },
|
||||||
{"move", "Y,Z", 0x6500, 0xff00, WR_Y|RD_Z, 0, I1 },
|
{"move", "Y,Z", 0x6500, 0xff00, WR_Y|RD_Z, 0, I1, 0, 0 },
|
||||||
{"mul", "z,v,y", 0, (int) M_MUL, INSN_MACRO, 0, I1 },
|
{"mul", "z,v,y", 0, (int) M_MUL, INSN_MACRO, 0, I1, 0, 0 },
|
||||||
{"mult", "x,y", 0xe818, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1 },
|
{"mult", "x,y", 0xe818, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1, 0, 0 },
|
||||||
{"multu", "x,y", 0xe819, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1 },
|
{"multu", "x,y", 0xe819, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1, 0, 0 },
|
||||||
{"neg", "x,w", 0xe80b, 0xf81f, WR_x|RD_y, 0, I1 },
|
{"neg", "x,w", 0xe80b, 0xf81f, WR_x|RD_y, 0, I1, 0, 0 },
|
||||||
{"not", "x,w", 0xe80f, 0xf81f, WR_x|RD_y, 0, I1 },
|
{"not", "x,w", 0xe80f, 0xf81f, WR_x|RD_y, 0, I1, 0, 0 },
|
||||||
{"or", "x,y", 0xe80d, 0xf81f, WR_x|RD_x|RD_y, 0, I1 },
|
{"or", "x,y", 0xe80d, 0xf81f, WR_x|RD_x|RD_y, 0, I1, 0, 0 },
|
||||||
{"rem", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1 },
|
{"rem", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1, 0, 0 },
|
||||||
{"rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO, 0, I1 },
|
{"rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO, 0, I1, 0, 0 },
|
||||||
{"remu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1 },
|
{"remu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1, 0, 0 },
|
||||||
{"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0, I1 },
|
{"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, 0 },
|
||||||
{"sb", "y,5(x)", 0xc000, 0xf800, RD_y|RD_x, 0, I1 },
|
{"sb", "y,5(x)", 0xc000, 0xf800, RD_y|RD_x, 0, I1, 0, 0 },
|
||||||
{"sd", "y,D(x)", 0x7800, 0xf800, RD_y|RD_x, 0, I3 },
|
{"sd", "y,D(x)", 0x7800, 0xf800, RD_y|RD_x, 0, I3, 0, 0 },
|
||||||
{"sd", "y,D(S)", 0xf900, 0xff00, RD_y|RD_PC, 0, I3 },
|
{"sd", "y,D(S)", 0xf900, 0xff00, RD_y|RD_PC, 0, I3, 0, 0 },
|
||||||
{"sd", "R,C(S)", 0xfa00, 0xff00, RD_31|RD_PC, 0, I1 },
|
{"sd", "R,C(S)", 0xfa00, 0xff00, RD_31|RD_PC, 0, I1, 0, 0 },
|
||||||
{"sh", "y,H(x)", 0xc800, 0xf800, RD_y|RD_x, 0, I1 },
|
{"sh", "y,H(x)", 0xc800, 0xf800, RD_y|RD_x, 0, I1, 0, 0 },
|
||||||
{"sllv", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0, I1 },
|
{"sllv", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0, I1, 0, 0 },
|
||||||
{"sll", "x,w,<", 0x3000, 0xf803, WR_x|RD_y, 0, I1 },
|
{"sll", "x,w,<", 0x3000, 0xf803, WR_x|RD_y, 0, I1, 0, 0 },
|
||||||
{"sll", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0, I1 },
|
{"sll", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0, I1, 0, 0 },
|
||||||
{"slti", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0, I1 },
|
{"slti", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0, I1, 0, 0 },
|
||||||
{"slt", "x,y", 0xe802, 0xf81f, WR_T|RD_x|RD_y, 0, I1 },
|
{"slt", "x,y", 0xe802, 0xf81f, WR_T|RD_x|RD_y, 0, I1, 0, 0 },
|
||||||
{"slt", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0, I1 },
|
{"slt", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0, I1, 0, 0 },
|
||||||
{"sltiu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0, I1 },
|
{"sltiu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0, I1, 0, 0 },
|
||||||
{"sltu", "x,y", 0xe803, 0xf81f, WR_T|RD_x|RD_y, 0, I1 },
|
{"sltu", "x,y", 0xe803, 0xf81f, WR_T|RD_x|RD_y, 0, I1, 0, 0 },
|
||||||
{"sltu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0, I1 },
|
{"sltu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0, I1, 0, 0 },
|
||||||
{"srav", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0, I1 },
|
{"srav", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0, I1, 0, 0 },
|
||||||
{"sra", "x,w,<", 0x3003, 0xf803, WR_x|RD_y, 0, I1 },
|
{"sra", "x,w,<", 0x3003, 0xf803, WR_x|RD_y, 0, I1, 0, 0 },
|
||||||
{"sra", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0, I1 },
|
{"sra", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0, I1, 0, 0 },
|
||||||
{"srlv", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0, I1 },
|
{"srlv", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0, I1, 0, 0 },
|
||||||
{"srl", "x,w,<", 0x3002, 0xf803, WR_x|RD_y, 0, I1 },
|
{"srl", "x,w,<", 0x3002, 0xf803, WR_x|RD_y, 0, I1, 0, 0 },
|
||||||
{"srl", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0, I1 },
|
{"srl", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0, I1, 0, 0 },
|
||||||
{"subu", "z,v,y", 0xe003, 0xf803, WR_z|RD_x|RD_y, 0, I1 },
|
{"subu", "z,v,y", 0xe003, 0xf803, WR_z|RD_x|RD_y, 0, I1, 0, 0 },
|
||||||
{"subu", "y,x,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 },
|
{"subu", "y,x,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1, 0, 0 },
|
||||||
{"subu", "x,I", 0, (int) M_SUBU_I_2, INSN_MACRO,0, I1 },
|
{"subu", "x,I", 0, (int) M_SUBU_I_2, INSN_MACRO, 0, I1, 0, 0 },
|
||||||
{"sw", "y,W(x)", 0xd800, 0xf800, RD_y|RD_x, 0, I1 },
|
{"sw", "y,W(x)", 0xd800, 0xf800, RD_y|RD_x, 0, I1, 0, 0 },
|
||||||
{"sw", "x,V(S)", 0xd000, 0xf800, RD_x|RD_SP, 0, I1 },
|
{"sw", "x,V(S)", 0xd000, 0xf800, RD_x|RD_SP, 0, I1, 0, 0 },
|
||||||
{"sw", "R,V(S)", 0x6200, 0xff00, RD_31|RD_SP, 0, I1 },
|
{"sw", "R,V(S)", 0x6200, 0xff00, RD_31|RD_SP, 0, I1, 0, 0 },
|
||||||
{"xor", "x,y", 0xe80e, 0xf81f, WR_x|RD_x|RD_y, 0, I1 },
|
{"xor", "x,y", 0xe80e, 0xf81f, WR_x|RD_x|RD_y, 0, I1, 0, 0 },
|
||||||
/* MIPS16e additions */
|
/* MIPS16e additions */
|
||||||
{"restore", "M", 0x6400, 0xff80, WR_31|RD_SP|WR_SP|NODS, 0, I32 },
|
{"restore", "M", 0x6400, 0xff80, WR_31|RD_SP|WR_SP|NODS, 0, I32, 0, 0 },
|
||||||
{"save", "m", 0x6480, 0xff80, RD_31|RD_SP|WR_SP|NODS, 0, I32 },
|
{"save", "m", 0x6480, 0xff80, RD_31|RD_SP|WR_SP|NODS, 0, I32, 0, 0 },
|
||||||
{"sdbbp", "6", 0xe801, 0xf81f, TRAP, 0, I32 },
|
{"sdbbp", "6", 0xe801, 0xf81f, TRAP, 0, I32, 0, 0 },
|
||||||
{"seb", "x", 0xe891, 0xf8ff, WR_x|RD_x, 0, I32 },
|
{"seb", "x", 0xe891, 0xf8ff, WR_x|RD_x, 0, I32, 0, 0 },
|
||||||
{"seh", "x", 0xe8b1, 0xf8ff, WR_x|RD_x, 0, I32 },
|
{"seh", "x", 0xe8b1, 0xf8ff, WR_x|RD_x, 0, I32, 0, 0 },
|
||||||
{"sew", "x", 0xe8d1, 0xf8ff, WR_x|RD_x, 0, I64 },
|
{"sew", "x", 0xe8d1, 0xf8ff, WR_x|RD_x, 0, I64, 0, 0 },
|
||||||
{"zeb", "x", 0xe811, 0xf8ff, WR_x|RD_x, 0, I32 },
|
{"zeb", "x", 0xe811, 0xf8ff, WR_x|RD_x, 0, I32, 0, 0 },
|
||||||
{"zeh", "x", 0xe831, 0xf8ff, WR_x|RD_x, 0, I32 },
|
{"zeh", "x", 0xe831, 0xf8ff, WR_x|RD_x, 0, I32, 0, 0 },
|
||||||
{"zew", "x", 0xe851, 0xf8ff, WR_x|RD_x, 0, I64 },
|
{"zew", "x", 0xe851, 0xf8ff, WR_x|RD_x, 0, I64, 0, 0 },
|
||||||
};
|
};
|
||||||
|
|
||||||
const int bfd_mips16_num_opcodes =
|
const int bfd_mips16_num_opcodes =
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user