More instruction tests.
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Thu Feb 19 11:15:45 1998 Nick Clifton <nickc@cygnus.com>
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Thu Feb 19 11:15:45 1998 Nick Clifton <nickc@cygnus.com>
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* sim/m32r/testutils.inc (mvaddr_h_gr): new macro to load an
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address into a general register.
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* sim/m32r/or3.cgs: Test OR3 instruction.
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* sim/m32r/or3.cgs: Test OR3 instruction.
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* sim/m32r/rach.cgs: Test RACH instruction.
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* sim/m32r/rach.cgs: Test RACH instruction.
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* sim/m32r/rem.cgs: Test REM instruction.
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* sim/m32r/rem.cgs: Test REM instruction.
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# m32r testcase for mvfc $dr,$scr
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# mach(): m32r m32rx
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.include "testutils.inc"
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start
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.global mvfc
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mvfc:
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mvi_h_condbit 0
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mvi_h_gr r4, 2
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mvfc r4, cr1
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test_h_gr r4, 0x80000000
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pass
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# m32r testcase for remu $dr,$sr
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# mach(): m32r m32rx
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.include "testutils.inc"
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start
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.global remu
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remu:
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mvi_h_gr r4, -17
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mvi_h_gr r5, 7
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remu r4, r5
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test_h_gr r4, 4
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; test_h_gr r4, -3
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pass
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# m32r testcase for rte
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# mach(): m32r m32rx
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.include "testutils.inc"
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start
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.global rte
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rte:
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mvi_h_gr r4, 0x80030000 ; C set, interrupt disabled, using interrupt stack
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mvtc r4, cr0
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mvaddr_h_gr r4, ok
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mvtc r4, cr6
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; rte
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fail
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ok:
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mvfc r4, cr0
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test_h_gr r4, 0x03030000 ; C clear, interrupts enabled, user stack
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pass
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