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2003-10-06 Dave Brolley <brolley@redhat.com> 

* profile-fr550.[ch]: New files.
        * configure.in: Move frv handling to alphabetically correct placement.
        * Makefile.in: Add fr550 support.
        * frv-sim.h,frv.c,interrups.c,memory.c,mloop.in,pipeline.c,
        profile.[ch],registers.c,traps.c: Add fr550 support.
        * arch.c,arch.h,cpu.c,cpu.h,cpuall.h,model.h,decode.c,decode.h,sem.c:
        Regenerate.
This commit is contained in:
Dave Brolley 2003-10-08 18:19:33 +00:00
parent 7c3f9ad027
commit e930b1f54f
25 changed files with 24030 additions and 495 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
sim/frv/ChangeLog
View File

@ -1,3 +1,13 @@
2003-10-06 Dave Brolley <brolley@redhat.com>
* profile-fr550.[ch]: New files.
* configure.in: Move frv handling to alphabetically correct placement.
* Makefile.in: Add fr550 support.
* frv-sim.h,frv.c,interrups.c,memory.c,mloop.in,pipeline.c,
profile.[ch],registers.c,traps.c: Add fr550 support.
* arch.c,arch.h,cpu.c,cpu.h,cpuall.h,model.h,decode.c,decode.h,sem.c:
Regenerate.
2003-09-25 Dave Brolley <brolley@redhat.com>
* reset.c (frv_initialize): Call frv_register_control_init first.

9
sim/frv/Makefile.in
View File

@ -1,5 +1,5 @@
# Makefile template for Configure for the frv simulator
# Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
# Copyright (C) 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
# Contributed by Red Hat.
#
# This program is free software; you can redistribute it and/or modify
@ -35,7 +35,7 @@ SIM_OBJS = \
sim-if.o arch.o \
$(FRV_OBJS) \
traps.o interrupts.o memory.o cache.o pipeline.o \
profile.o profile-fr400.o profile-fr500.o options.o \
profile.o profile-fr400.o profile-fr500.o profile-fr550.o options.o \
devices.o reset.o registers.o \
$(CONFIG_DEVICES)
@ -78,9 +78,10 @@ cache.o: cache.c $(FRVBF_INCLUDE_DEPS)
options.o: options.c $(FRVBF_INCLUDE_DEPS)
reset.o: reset.c $(FRVBF_INCLUDE_DEPS)
registers.o: registers.c $(FRVBF_INCLUDE_DEPS)
profile.o: profile.c profile-fr400.h profile-fr500.h $(FRVBF_INCLUDE_DEPS)
profile.o: profile.c profile-fr400.h profile-fr500.h profile-fr550.h $(FRVBF_INCLUDE_DEPS)
profile-fr400.o: profile-fr400.c profile-fr400.h $(FRVBF_INCLUDE_DEPS)
profile-fr500.o: profile-fr500.c profile-fr500.h $(FRVBF_INCLUDE_DEPS)
profile-fr550.o: profile-fr550.c profile-fr550.h $(FRVBF_INCLUDE_DEPS)
sim-if.o: sim-if.c $(FRVBF_INCLUDE_DEPS) $(srcdir)/../common/sim-core.h eng.h
@ -120,7 +121,7 @@ arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(srcdir)/../../cpu/frv.cpu
$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
cpu=frvbf mach=frv,fr500,fr400,tomcat,simple SUFFIX= \
cpu=frvbf mach=frv,fr550,fr500,fr400,tomcat,simple SUFFIX= \
archfile=$(srcdir)/../../cpu/frv.cpu \
FLAGS="with-scache with-profile=fn with-generic-write with-parallel-only" \
EXTRAFILES="$(CGEN_CPU_SEM)"

3
sim/frv/arch.c
View File

@ -30,6 +30,9 @@ const MACH *sim_machs[] =
#ifdef HAVE_CPU_FRVBF
& frv_mach,
#endif
#ifdef HAVE_CPU_FRVBF
& fr550_mach,
#endif
#ifdef HAVE_CPU_FRVBF
& fr500_mach,
#endif

68
sim/frv/arch.h
View File

@ -29,40 +29,52 @@ with this program; if not, write to the Free Software Foundation, Inc.,
/* Enum declaration for model types. */
typedef enum model_type {
MODEL_FRV, MODEL_FR500, MODEL_TOMCAT, MODEL_FR400
, MODEL_SIMPLE, MODEL_MAX
MODEL_FRV, MODEL_FR550, MODEL_FR500, MODEL_TOMCAT
, MODEL_FR400, MODEL_SIMPLE, MODEL_MAX
} MODEL_TYPE;
#define MAX_MODELS ((int) MODEL_MAX)
/* Enum declaration for unit types. */
typedef enum unit_type {
UNIT_NONE, UNIT_FRV_U_EXEC, UNIT_FR500_U_COMMIT, UNIT_FR500_U_DCUL
, UNIT_FR500_U_ICUL, UNIT_FR500_U_DCPL, UNIT_FR500_U_ICPL, UNIT_FR500_U_DCF
, UNIT_FR500_U_DCI, UNIT_FR500_U_ICI, UNIT_FR500_U_MEMBAR, UNIT_FR500_U_BARRIER
, UNIT_FR500_U_MEDIA_DUAL_BTOHE, UNIT_FR500_U_MEDIA_DUAL_HTOB, UNIT_FR500_U_MEDIA_DUAL_BTOH, UNIT_FR500_U_MEDIA_DUAL_UNPACK
, UNIT_FR500_U_MEDIA_DUAL_EXPAND, UNIT_FR500_U_MEDIA_QUAD_COMPLEX, UNIT_FR500_U_MEDIA_QUAD_MUL, UNIT_FR500_U_MEDIA_DUAL_MUL
, UNIT_FR500_U_MEDIA_QUAD_ARITH, UNIT_FR500_U_MEDIA, UNIT_FR500_U_FLOAT_DUAL_CONVERT, UNIT_FR500_U_FLOAT_CONVERT
, UNIT_FR500_U_FLOAT_DUAL_COMPARE, UNIT_FR500_U_FLOAT_COMPARE, UNIT_FR500_U_FLOAT_DUAL_SQRT, UNIT_FR500_U_FLOAT_SQRT
, UNIT_FR500_U_FLOAT_DIV, UNIT_FR500_U_FLOAT_DUAL_ARITH, UNIT_FR500_U_FLOAT_ARITH, UNIT_FR500_U_GR2SPR
, UNIT_FR500_U_GR2FR, UNIT_FR500_U_SPR2GR, UNIT_FR500_U_FR2GR, UNIT_FR500_U_FR2FR
, UNIT_FR500_U_SWAP, UNIT_FR500_U_FR_R_STORE, UNIT_FR500_U_FR_STORE, UNIT_FR500_U_FR_LOAD
, UNIT_FR500_U_GR_R_STORE, UNIT_FR500_U_GR_STORE, UNIT_FR500_U_GR_LOAD, UNIT_FR500_U_SET_HILO
, UNIT_FR500_U_CLRFR, UNIT_FR500_U_CLRGR, UNIT_FR500_U_CHECK, UNIT_FR500_U_TRAP
, UNIT_FR500_U_BRANCH, UNIT_FR500_U_IDIV, UNIT_FR500_U_IMUL, UNIT_FR500_U_INTEGER
, UNIT_FR500_U_EXEC, UNIT_TOMCAT_U_EXEC, UNIT_FR400_U_DCUL, UNIT_FR400_U_ICUL
, UNIT_FR400_U_DCPL, UNIT_FR400_U_ICPL, UNIT_FR400_U_DCF, UNIT_FR400_U_DCI
, UNIT_FR400_U_ICI, UNIT_FR400_U_MEMBAR, UNIT_FR400_U_BARRIER, UNIT_FR400_U_MEDIA_DUAL_HTOB
, UNIT_FR400_U_MEDIA_DUAL_EXPAND, UNIT_FR400_U_MEDIA_7, UNIT_FR400_U_MEDIA_6, UNIT_FR400_U_MEDIA_4_ACC_DUAL
, UNIT_FR400_U_MEDIA_4_ACCG, UNIT_FR400_U_MEDIA_4, UNIT_FR400_U_MEDIA_3_QUAD, UNIT_FR400_U_MEDIA_3_DUAL
, UNIT_FR400_U_MEDIA_3, UNIT_FR400_U_MEDIA_2_ADD_SUB_DUAL, UNIT_FR400_U_MEDIA_2_ADD_SUB, UNIT_FR400_U_MEDIA_2_ACC_DUAL
, UNIT_FR400_U_MEDIA_2_ACC, UNIT_FR400_U_MEDIA_2_QUAD, UNIT_FR400_U_MEDIA_2, UNIT_FR400_U_MEDIA_HILO
, UNIT_FR400_U_MEDIA_1_QUAD, UNIT_FR400_U_MEDIA_1, UNIT_FR400_U_GR2SPR, UNIT_FR400_U_GR2FR
, UNIT_FR400_U_SPR2GR, UNIT_FR400_U_FR2GR, UNIT_FR400_U_SWAP, UNIT_FR400_U_FR_STORE
, UNIT_FR400_U_FR_LOAD, UNIT_FR400_U_GR_STORE, UNIT_FR400_U_GR_LOAD, UNIT_FR400_U_SET_HILO
, UNIT_FR400_U_CHECK, UNIT_FR400_U_TRAP, UNIT_FR400_U_BRANCH, UNIT_FR400_U_IDIV
, UNIT_FR400_U_IMUL, UNIT_FR400_U_INTEGER, UNIT_FR400_U_EXEC, UNIT_SIMPLE_U_EXEC
, UNIT_MAX
UNIT_NONE, UNIT_FRV_U_EXEC, UNIT_FR550_U_MEDIA_4_QUAD, UNIT_FR550_U_MEDIA_4_ADD_SUB_DUAL
, UNIT_FR550_U_MEDIA_4_ADD_SUB, UNIT_FR550_U_MEDIA_4_ACC_DUAL, UNIT_FR550_U_MEDIA_4_ACC, UNIT_FR550_U_MEDIA_4
, UNIT_FR550_U_MEDIA_SET, UNIT_FR550_U_MEDIA_3_MCLRACC, UNIT_FR550_U_MEDIA_3_WTACC, UNIT_FR550_U_MEDIA_3_ACC_DUAL
, UNIT_FR550_U_MEDIA_3_ACC, UNIT_FR550_U_MEDIA_3_DUAL, UNIT_FR550_U_MEDIA_DUAL_EXPAND, UNIT_FR550_U_MEDIA_QUAD
, UNIT_FR550_U_MEDIA, UNIT_FR550_U_FLOAT_CONVERT, UNIT_FR550_U_COMMIT, UNIT_FR550_U_DCUL
, UNIT_FR550_U_ICUL, UNIT_FR550_U_DCPL, UNIT_FR550_U_ICPL, UNIT_FR550_U_DCF
, UNIT_FR550_U_DCI, UNIT_FR550_U_ICI, UNIT_FR550_U_CLRFR, UNIT_FR550_U_CLRGR
, UNIT_FR550_U_FR2FR, UNIT_FR550_U_SWAP, UNIT_FR550_U_FR_STORE, UNIT_FR550_U_FR_LOAD
, UNIT_FR550_U_GR_STORE, UNIT_FR550_U_GR_LOAD, UNIT_FR550_U_SET_HILO, UNIT_FR550_U_GR2SPR
, UNIT_FR550_U_SPR2GR, UNIT_FR550_U_GR2FR, UNIT_FR550_U_FR2GR, UNIT_FR550_U_FLOAT_DUAL_COMPARE
, UNIT_FR550_U_FLOAT_COMPARE, UNIT_FR550_U_FLOAT_SQRT, UNIT_FR550_U_FLOAT_DIV, UNIT_FR550_U_FLOAT_DUAL_ARITH
, UNIT_FR550_U_FLOAT_ARITH, UNIT_FR550_U_CHECK, UNIT_FR550_U_TRAP, UNIT_FR550_U_BRANCH
, UNIT_FR550_U_IDIV, UNIT_FR550_U_IMUL, UNIT_FR550_U_INTEGER, UNIT_FR550_U_EXEC
, UNIT_FR500_U_COMMIT, UNIT_FR500_U_DCUL, UNIT_FR500_U_ICUL, UNIT_FR500_U_DCPL
, UNIT_FR500_U_ICPL, UNIT_FR500_U_DCF, UNIT_FR500_U_DCI, UNIT_FR500_U_ICI
, UNIT_FR500_U_MEMBAR, UNIT_FR500_U_BARRIER, UNIT_FR500_U_MEDIA_DUAL_BTOHE, UNIT_FR500_U_MEDIA_DUAL_HTOB
, UNIT_FR500_U_MEDIA_DUAL_BTOH, UNIT_FR500_U_MEDIA_DUAL_UNPACK, UNIT_FR500_U_MEDIA_DUAL_EXPAND, UNIT_FR500_U_MEDIA_QUAD_COMPLEX
, UNIT_FR500_U_MEDIA_QUAD_MUL, UNIT_FR500_U_MEDIA_DUAL_MUL, UNIT_FR500_U_MEDIA_QUAD_ARITH, UNIT_FR500_U_MEDIA
, UNIT_FR500_U_FLOAT_DUAL_CONVERT, UNIT_FR500_U_FLOAT_CONVERT, UNIT_FR500_U_FLOAT_DUAL_COMPARE, UNIT_FR500_U_FLOAT_COMPARE
, UNIT_FR500_U_FLOAT_DUAL_SQRT, UNIT_FR500_U_FLOAT_SQRT, UNIT_FR500_U_FLOAT_DIV, UNIT_FR500_U_FLOAT_DUAL_ARITH
, UNIT_FR500_U_FLOAT_ARITH, UNIT_FR500_U_GR2SPR, UNIT_FR500_U_GR2FR, UNIT_FR500_U_SPR2GR
, UNIT_FR500_U_FR2GR, UNIT_FR500_U_FR2FR, UNIT_FR500_U_SWAP, UNIT_FR500_U_FR_R_STORE
, UNIT_FR500_U_FR_STORE, UNIT_FR500_U_FR_LOAD, UNIT_FR500_U_GR_R_STORE, UNIT_FR500_U_GR_STORE
, UNIT_FR500_U_GR_LOAD, UNIT_FR500_U_SET_HILO, UNIT_FR500_U_CLRFR, UNIT_FR500_U_CLRGR
, UNIT_FR500_U_CHECK, UNIT_FR500_U_TRAP, UNIT_FR500_U_BRANCH, UNIT_FR500_U_IDIV
, UNIT_FR500_U_IMUL, UNIT_FR500_U_INTEGER, UNIT_FR500_U_EXEC, UNIT_TOMCAT_U_EXEC
, UNIT_FR400_U_DCUL, UNIT_FR400_U_ICUL, UNIT_FR400_U_DCPL, UNIT_FR400_U_ICPL
, UNIT_FR400_U_DCF, UNIT_FR400_U_DCI, UNIT_FR400_U_ICI, UNIT_FR400_U_MEMBAR
, UNIT_FR400_U_BARRIER, UNIT_FR400_U_MEDIA_DUAL_HTOB, UNIT_FR400_U_MEDIA_DUAL_EXPAND, UNIT_FR400_U_MEDIA_7
, UNIT_FR400_U_MEDIA_6, UNIT_FR400_U_MEDIA_4_ACC_DUAL, UNIT_FR400_U_MEDIA_4_ACCG, UNIT_FR400_U_MEDIA_4
, UNIT_FR400_U_MEDIA_3_QUAD, UNIT_FR400_U_MEDIA_3_DUAL, UNIT_FR400_U_MEDIA_3, UNIT_FR400_U_MEDIA_2_ADD_SUB_DUAL
, UNIT_FR400_U_MEDIA_2_ADD_SUB, UNIT_FR400_U_MEDIA_2_ACC_DUAL, UNIT_FR400_U_MEDIA_2_ACC, UNIT_FR400_U_MEDIA_2_QUAD
, UNIT_FR400_U_MEDIA_2, UNIT_FR400_U_MEDIA_HILO, UNIT_FR400_U_MEDIA_1_QUAD, UNIT_FR400_U_MEDIA_1
, UNIT_FR400_U_GR2SPR, UNIT_FR400_U_GR2FR, UNIT_FR400_U_SPR2GR, UNIT_FR400_U_FR2GR
, UNIT_FR400_U_SWAP, UNIT_FR400_U_FR_STORE, UNIT_FR400_U_FR_LOAD, UNIT_FR400_U_GR_STORE
, UNIT_FR400_U_GR_LOAD, UNIT_FR400_U_SET_HILO, UNIT_FR400_U_CHECK, UNIT_FR400_U_TRAP
, UNIT_FR400_U_BRANCH, UNIT_FR400_U_IDIV, UNIT_FR400_U_IMUL, UNIT_FR400_U_INTEGER
, UNIT_FR400_U_EXEC, UNIT_SIMPLE_U_EXEC, UNIT_MAX
} UNIT_TYPE;
#define MAX_UNITS (1)

116
sim/frv/cache.c
View File

@ -1,5 +1,5 @@
/* frv cache model.
Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright (C) 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
Contributed by Red Hat.
This file is part of the GNU simulators.
@ -38,20 +38,30 @@ frv_cache_init (SIM_CPU *cpu, FRV_CACHE *cache)
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
if (cache->sets == 0)
cache->sets = 128;
if (cache->ways == 0)
cache->ways = 2;
if (cache->configured_sets == 0)
cache->configured_sets = 128;
if (cache->configured_ways == 0)
cache->configured_ways = 2;
if (cache->line_size == 0)
cache->line_size = 32;
if (cache->memory_latency == 0)
cache->memory_latency = 20;
break;
case bfd_mach_fr550:
if (cache->configured_sets == 0)
cache->configured_sets = 128;
if (cache->configured_ways == 0)
cache->configured_ways = 4;
if (cache->line_size == 0)
cache->line_size = 64;
if (cache->memory_latency == 0)
cache->memory_latency = 20;
break;
default:
if (cache->sets == 0)
cache->sets = 64;
if (cache->ways == 0)
cache->ways = 4;
if (cache->configured_sets == 0)
cache->configured_sets = 64;
if (cache->configured_ways == 0)
cache->configured_ways = 4;
if (cache->line_size == 0)
cache->line_size = 64;
if (cache->memory_latency == 0)
@ -59,6 +69,8 @@ frv_cache_init (SIM_CPU *cpu, FRV_CACHE *cache)
break;
}
frv_cache_reconfigure (cpu, cache);
/* First allocate the cache storage based on the given dimensions. */
elements = cache->sets * cache->ways;
cache->tag_storage = (FRV_CACHE_TAG *)
@ -95,6 +107,40 @@ frv_cache_term (FRV_CACHE *cache)
free (cache->pipeline[LD].status.return_buffer.data);
}
/* Reset the cache configuration based on registers in the cpu. */
void
frv_cache_reconfigure (SIM_CPU *current_cpu, FRV_CACHE *cache)
{
int ihsr8;
int icdm;
SIM_DESC sd;
/* Set defaults for fields which are not initialized. */
sd = CPU_STATE (current_cpu);
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr550:
if (cache == CPU_INSN_CACHE (current_cpu))
{
ihsr8 = GET_IHSR8 ();
icdm = GET_IHSR8_ICDM (ihsr8);
/* If IHSR8.ICDM is set, then the cache becomes a one way cache. */
if (icdm)
{
cache->sets = cache->sets * cache->ways;
cache->ways = 1;
break;
}
}
/* fall through */
default:
/* Set the cache to its original settings. */
cache->sets = cache->configured_sets;
cache->ways = cache->configured_ways;
break;
}
}
/* Determine whether the given cache is enabled. */
int
frv_cache_enabled (FRV_CACHE *cache)
@ -108,6 +154,44 @@ frv_cache_enabled (FRV_CACHE *cache)
return 0;
}
/* Determine whether the given address is RAM access, assuming that HSR0.RME
is set. */
static int
ram_access (FRV_CACHE *cache, USI address)
{
int ihsr8;
int cwe;
USI start, end, way_size;
SIM_CPU *current_cpu = cache->cpu;
SIM_DESC sd = CPU_STATE (current_cpu);
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr550:
/* IHSR8.DCWE or IHSR8.ICWE deternines which ways get RAM access. */
ihsr8 = GET_IHSR8 ();
if (cache == CPU_INSN_CACHE (current_cpu))
{
start = 0xfe000000;
end = 0xfe008000;
cwe = GET_IHSR8_ICWE (ihsr8);
}
else
{
start = 0xfe400000;
end = 0xfe408000;
cwe = GET_IHSR8_DCWE (ihsr8);
}
way_size = (end - start) / 4;
end -= way_size * cwe;
return address >= start && address < end;
default:
break;
}
return 1; /* RAM access */
}
/* Determine whether the given address should be accessed without using
the cache. */
static int
@ -124,6 +208,17 @@ non_cache_access (FRV_CACHE *cache, USI address)
if (address >= 0xff000000
|| address >= 0xfe000000 && address <= 0xfeffffff)
return 1; /* non-cache access */
case bfd_mach_fr550:
if (address >= 0xff000000
|| address >= 0xfeff0000 && address <= 0xfeffffff)
return 1; /* non-cache access */
if (cache == CPU_INSN_CACHE (current_cpu))
{
if (address >= 0xfe000000 && address <= 0xfe007fff)
return 1; /* non-cache access */
}
else if (address >= 0xfe400000 && address <= 0xfe407fff)
return 1; /* non-cache access */
default:
if (address >= 0xff000000
|| address >= 0xfeff0000 && address <= 0xfeffffff)
@ -139,7 +234,7 @@ non_cache_access (FRV_CACHE *cache, USI address)
hsr0 = GET_HSR0 ();
if (GET_HSR0_RME (hsr0))
return 1; /* non-cache access */
return ram_access (cache, address);
return 0; /* cache-access */
}
@ -1531,7 +1626,6 @@ frv_cache_read_passive_SI (FRV_CACHE *cache, SI address, SI *value)
/* A cache line was available for the data.
Extract the target data from the line. */
offset = address & (cache->line_size - 1);
offset &= ~3;
*value = T2H_4 (*(SI *)(tag->line + offset));
return 1;
}

17
sim/frv/cache.h
View File

@ -1,5 +1,5 @@
/* Cache support for the FRV simulator
Copyright (C) 1999, 2000 Free Software Foundation, Inc.
Copyright (C) 1999, 2000, 2003 Free Software Foundation, Inc.
Contributed by Red Hat.
This file is part of the GNU Simulators.
@ -165,6 +165,8 @@ typedef struct {
*/
typedef struct {
SIM_CPU *cpu;
unsigned configured_ways; /* Number of ways configured in each set. */
unsigned configured_sets; /* Number of sets configured in the cache. */
unsigned ways; /* Number of ways in each set. */
unsigned sets; /* Number of sets in the cache. */
unsigned line_size; /* Size of each cache line. */
@ -200,14 +202,15 @@ typedef struct {
#define CACHE_RETURN_DATA(cache, slot, address, mode, N) ( \
T2H_##N (*(mode *)(& (cache)->pipeline[slot].status.return_buffer.data \
[((address) & ((cache)->line_size - 1) \
& ~(sizeof (mode) - 1))])) \
[((address) & ((cache)->line_size - 1))])) \
)
#define CACHE_RETURN_DATA_ADDRESS(cache, slot, address, N) ( \
((void *)& (cache)->pipeline[slot].status.return_buffer.data[(address) \
& ((cache)->line_size - 1) \
& ~((N) - 1)]) \
& ((cache)->line_size - 1)]) \
)
#define DATA_CROSSES_CACHE_LINE(cache, address, size) ( \
((address) & ((cache)->line_size - 1)) + (size) > (cache)->line_size \
)
#define CACHE_INITIALIZED(cache) ((cache)->data_storage != NULL)
@ -217,6 +220,8 @@ void
frv_cache_init (SIM_CPU *, FRV_CACHE *);
void
frv_cache_term (FRV_CACHE *);
void
frv_cache_reconfigure (SIM_CPU *, FRV_CACHE *);
int
frv_cache_enabled (FRV_CACHE *);

16
sim/frv/cpu.c
View File

@ -620,6 +620,22 @@ frvbf_h_acc40U_set (SIM_CPU *current_cpu, UINT regno, UDI newval)
SET_H_ACC40U (regno, newval);
}
/* Get the value of h-iacc0. */
DI
frvbf_h_iacc0_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_IACC0 (regno);
}
/* Set a value for h-iacc0. */
void
frvbf_h_iacc0_set (SIM_CPU *current_cpu, UINT regno, DI newval)
{
SET_H_IACC0 (regno, newval);
}
/* Get the value of h-iccr. */
UQI

125
sim/frv/cpu.h
View File

@ -30,7 +30,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#define MAX_LIW_INSNS 1
/* Maximum number of instructions that can be executed in parallel. */
#define MAX_PARALLEL_INSNS 4
#define MAX_PARALLEL_INSNS 8
/* CPU state information. */
typedef struct {
@ -257,6 +257,14 @@ CPU (h_spr[(((index)) + (1472))]) = ANDDI (SRLDI ((x), 32), 255);\
CPU (h_spr[(((index)) + (1408))]) = TRUNCDISI ((x));\
}\
;} while (0)
#define GET_H_IACC0(index) ORDI (SLLDI (EXTSIDI (GET_H_SPR (((UINT) 280))), 32), ZEXTSIDI (GET_H_SPR (((UINT) 281))))
#define SET_H_IACC0(index, x) \
do { \
{\
SET_H_SPR (((UINT) 280), TRUNCDISI (SRLDI ((x), 32)));\
SET_H_SPR (((UINT) 281), TRUNCDISI ((x)));\
}\
;} while (0)
/* Cover fns for register access. */
USI frvbf_h_pc_get (SIM_CPU *);
@ -333,6 +341,8 @@ DI frvbf_h_acc40S_get (SIM_CPU *, UINT);
void frvbf_h_acc40S_set (SIM_CPU *, UINT, DI);
UDI frvbf_h_acc40U_get (SIM_CPU *, UINT);
void frvbf_h_acc40U_set (SIM_CPU *, UINT, UDI);
DI frvbf_h_iacc0_get (SIM_CPU *, UINT);
void frvbf_h_iacc0_set (SIM_CPU *, UINT, DI);
UQI frvbf_h_iccr_get (SIM_CPU *, UINT);
void frvbf_h_iccr_set (SIM_CPU *, UINT, UQI);
UQI frvbf_h_fccr_get (SIM_CPU *, UINT);
@ -348,6 +358,19 @@ typedef struct {
int empty;
} MODEL_FRV_DATA;
typedef struct {
DI prev_fr_load;
DI prev_fr_complex_1;
DI prev_fr_complex_2;
DI prev_ccr_complex;
DI prev_acc_mmac;
DI cur_fr_load;
DI cur_fr_complex_1;
DI cur_fr_complex_2;
SI cur_ccr_complex;
DI cur_acc_mmac;
} MODEL_FR550_DATA;
typedef struct {
DI prev_fpop;
DI prev_media;
@ -548,6 +571,13 @@ union sem_fields {
unsigned char in_GRi;
unsigned char out_GRdoublek;
} sfmt_smuli;
struct { /* */
UINT f_GRj;
UINT f_GRk;
unsigned char in_GRj;
unsigned char in_h_iacc0_DI_0;
unsigned char out_GRk;
} sfmt_scutss;
struct { /* */
UINT f_ACC40Si;
UINT f_FRj;
@ -612,6 +642,14 @@ union sem_fields {
unsigned char in_GRk;
unsigned char out_GRk;
} sfmt_swapi;
struct { /* */
UINT f_GRi;
UINT f_GRj;
unsigned char in_GRi;
unsigned char in_GRj;
unsigned char in_h_iacc0_DI_0;
unsigned char out_h_iacc0_DI_0;
} sfmt_smass;
struct { /* */
INT f_s6;
UINT f_FRi;
@ -1571,6 +1609,57 @@ struct scache {
f_ope2 = EXTRACT_LSB0_UINT (insn, 32, 9, 4); \
f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
#define EXTRACT_IFMT_SMU_VARS \
UINT f_pack; \
UINT f_rd_null; \
UINT f_op; \
UINT f_GRi; \
UINT f_ope1; \
UINT f_GRj; \
unsigned int length;
#define EXTRACT_IFMT_SMU_CODE \
length = 4; \
f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
f_rd_null = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
#define EXTRACT_IFMT_SLASS_VARS \
UINT f_pack; \
UINT f_GRk; \
UINT f_op; \
UINT f_GRi; \
UINT f_ope1; \
UINT f_GRj; \
unsigned int length;
#define EXTRACT_IFMT_SLASS_CODE \
length = 4; \
f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
#define EXTRACT_IFMT_SCUTSS_VARS \
UINT f_pack; \
UINT f_GRk; \
UINT f_op; \
UINT f_rs_null; \
UINT f_ope1; \
UINT f_GRj; \
unsigned int length;
#define EXTRACT_IFMT_SCUTSS_CODE \
length = 4; \
f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
f_rs_null = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
#define EXTRACT_IFMT_CADD_VARS \
UINT f_pack; \
UINT f_GRk; \
@ -1800,23 +1889,6 @@ struct scache {
f_misc_null_4 = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
f_s16 = EXTRACT_LSB0_INT (insn, 32, 15, 16); \
#define EXTRACT_IFMT_LDSB_VARS \
UINT f_pack; \
UINT f_GRk; \
UINT f_op; \
UINT f_GRi; \
UINT f_ope1; \
UINT f_GRj; \
unsigned int length;
#define EXTRACT_IFMT_LDSB_CODE \
length = 4; \
f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
#define EXTRACT_IFMT_LDBF_VARS \
UINT f_pack; \
UINT f_FRk; \
@ -3058,23 +3130,6 @@ struct scache {
f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
#define EXTRACT_IFMT_ICI_VARS \
UINT f_pack; \
UINT f_rd_null; \
UINT f_op; \
UINT f_GRi; \
UINT f_ope1; \
UINT f_GRj; \
unsigned int length;
#define EXTRACT_IFMT_ICI_CODE \
length = 4; \
f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
f_rd_null = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
#define EXTRACT_IFMT_ICEI_VARS \
UINT f_pack; \
UINT f_misc_null_1; \

1
sim/frv/cpuall.h
View File

@ -35,6 +35,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#endif
extern const MACH frv_mach;
extern const MACH fr550_mach;
extern const MACH fr500_mach;
extern const MACH tomcat_mach;
extern const MACH fr400_mach;

112
sim/frv/decode.c
View File

@ -58,9 +58,14 @@ static const struct insn_sem frvbf_insn_sem[] =
{ FRV_INSN_NUDIV, FRVBF_INSN_NUDIV, FRVBF_SFMT_SDIV },
{ FRV_INSN_SMUL, FRVBF_INSN_SMUL, FRVBF_SFMT_SMUL },
{ FRV_INSN_UMUL, FRVBF_INSN_UMUL, FRVBF_SFMT_SMUL },
{ FRV_INSN_SMU, FRVBF_INSN_SMU, FRVBF_SFMT_SMU },
{ FRV_INSN_SMASS, FRVBF_INSN_SMASS, FRVBF_SFMT_SMASS },
{ FRV_INSN_SMSSS, FRVBF_INSN_SMSSS, FRVBF_SFMT_SMASS },
{ FRV_INSN_SLL, FRVBF_INSN_SLL, FRVBF_SFMT_ADD },
{ FRV_INSN_SRL, FRVBF_INSN_SRL, FRVBF_SFMT_ADD },
{ FRV_INSN_SRA, FRVBF_INSN_SRA, FRVBF_SFMT_ADD },
{ FRV_INSN_SLASS, FRVBF_INSN_SLASS, FRVBF_SFMT_ADD },
{ FRV_INSN_SCUTSS, FRVBF_INSN_SCUTSS, FRVBF_SFMT_SCUTSS },
{ FRV_INSN_SCAN, FRVBF_INSN_SCAN, FRVBF_SFMT_ADD },
{ FRV_INSN_CADD, FRVBF_INSN_CADD, FRVBF_SFMT_CADD },
{ FRV_INSN_CSUB, FRVBF_INSN_CSUB, FRVBF_SFMT_CADD },
@ -98,6 +103,8 @@ static const struct insn_sem frvbf_insn_sem[] =
{ FRV_INSN_SUBX, FRVBF_INSN_SUBX, FRVBF_SFMT_ADDX },
{ FRV_INSN_ADDXCC, FRVBF_INSN_ADDXCC, FRVBF_SFMT_ADDCC },
{ FRV_INSN_SUBXCC, FRVBF_INSN_SUBXCC, FRVBF_SFMT_ADDCC },
{ FRV_INSN_ADDSS, FRVBF_INSN_ADDSS, FRVBF_SFMT_ADD },
{ FRV_INSN_SUBSS, FRVBF_INSN_SUBSS, FRVBF_SFMT_ADD },
{ FRV_INSN_ADDI, FRVBF_INSN_ADDI, FRVBF_SFMT_ADDI },
{ FRV_INSN_SUBI, FRVBF_INSN_SUBI, FRVBF_SFMT_ADDI },
{ FRV_INSN_ANDI, FRVBF_INSN_ANDI, FRVBF_SFMT_ADDI },
@ -1408,6 +1415,21 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
case 67 : itype = FRVBF_INSN_NLDUHI; goto extract_sfmt_nldsbi;
case 68 : itype = FRVBF_INSN_NLDI; goto extract_sfmt_nldsbi;
case 69 : itype = FRVBF_INSN_NLDDI; goto extract_sfmt_nlddi;
case 70 :
{
unsigned int val = (((insn >> 6) & (7 << 0)));
switch (val)
{
case 0 : itype = FRVBF_INSN_ADDSS; goto extract_sfmt_add;
case 1 : itype = FRVBF_INSN_SUBSS; goto extract_sfmt_add;
case 2 : itype = FRVBF_INSN_SLASS; goto extract_sfmt_add;
case 4 : itype = FRVBF_INSN_SCUTSS; goto extract_sfmt_scutss;
case 5 : itype = FRVBF_INSN_SMU; goto extract_sfmt_smu;
case 6 : itype = FRVBF_INSN_SMASS; goto extract_sfmt_smass;
case 7 : itype = FRVBF_INSN_SMSSS; goto extract_sfmt_smass;
default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
}
}
case 71 : itype = FRVBF_INSN_SCANI; goto extract_sfmt_addi;
case 72 : itype = FRVBF_INSN_NLDBFI; goto extract_sfmt_nldbfi;
case 73 : itype = FRVBF_INSN_NLDHFI; goto extract_sfmt_nldbfi;
@ -2290,7 +2312,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
{
const IDESC *idesc = &frvbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addcc.f
#define FLD(f) abuf->fields.sfmt_scutss.f
UINT f_GRk;
UINT f_GRj;
@ -2374,6 +2396,94 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
FLD (out_GRdoublek) = f_GRk;
}
#endif
#undef FLD
return idesc;
}
extract_sfmt_smu:
{
const IDESC *idesc = &frvbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_smass.f
UINT f_GRi;
UINT f_GRj;
f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
/* Record the fields for the semantic handler. */
FLD (f_GRi) = f_GRi;
FLD (f_GRj) = f_GRj;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_smu", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
#if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */
if (PROFILE_MODEL_P (current_cpu))
{
FLD (in_GRi) = f_GRi;
FLD (in_GRj) = f_GRj;
FLD (out_h_iacc0_DI_0) = 0;
}
#endif
#undef FLD
return idesc;
}
extract_sfmt_smass:
{
const IDESC *idesc = &frvbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_smass.f
UINT f_GRi;
UINT f_GRj;
f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
/* Record the fields for the semantic handler. */
FLD (f_GRi) = f_GRi;
FLD (f_GRj) = f_GRj;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_smass", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0));
#if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */
if (PROFILE_MODEL_P (current_cpu))
{
FLD (in_GRi) = f_GRi;
FLD (in_GRj) = f_GRj;
FLD (in_h_iacc0_DI_0) = 0;
FLD (out_h_iacc0_DI_0) = 0;
}
#endif
#undef FLD
return idesc;
}
extract_sfmt_scutss:
{
const IDESC *idesc = &frvbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_scutss.f
UINT f_GRk;
UINT f_GRj;
f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
/* Record the fields for the semantic handler. */
FLD (f_GRj) = f_GRj;
FLD (f_GRk) = f_GRk;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_scutss", "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0));
#if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */
if (PROFILE_MODEL_P (current_cpu))
{
FLD (in_GRj) = f_GRj;
FLD (in_h_iacc0_DI_0) = 0;
FLD (out_GRk) = f_GRk;
}
#endif
#undef FLD
return idesc;
}

548
sim/frv/decode.h
View File

@ -38,264 +38,316 @@ typedef enum frvbf_insn_type {
, FRVBF_INSN_X_CHAIN, FRVBF_INSN_X_BEGIN, FRVBF_INSN_ADD, FRVBF_INSN_SUB
, FRVBF_INSN_AND, FRVBF_INSN_OR, FRVBF_INSN_XOR, FRVBF_INSN_NOT
, FRVBF_INSN_SDIV, FRVBF_INSN_NSDIV, FRVBF_INSN_UDIV, FRVBF_INSN_NUDIV
, FRVBF_INSN_SMUL, FRVBF_INSN_UMUL, FRVBF_INSN_SLL, FRVBF_INSN_SRL
, FRVBF_INSN_SRA, FRVBF_INSN_SCAN, FRVBF_INSN_CADD, FRVBF_INSN_CSUB
, FRVBF_INSN_CAND, FRVBF_INSN_COR, FRVBF_INSN_CXOR, FRVBF_INSN_CNOT
, FRVBF_INSN_CSMUL, FRVBF_INSN_CSDIV, FRVBF_INSN_CUDIV, FRVBF_INSN_CSLL
, FRVBF_INSN_CSRL, FRVBF_INSN_CSRA, FRVBF_INSN_CSCAN, FRVBF_INSN_ADDCC
, FRVBF_INSN_SUBCC, FRVBF_INSN_ANDCC, FRVBF_INSN_ORCC, FRVBF_INSN_XORCC
, FRVBF_INSN_SLLCC, FRVBF_INSN_SRLCC, FRVBF_INSN_SRACC, FRVBF_INSN_SMULCC
, FRVBF_INSN_UMULCC, FRVBF_INSN_CADDCC, FRVBF_INSN_CSUBCC, FRVBF_INSN_CSMULCC
, FRVBF_INSN_CANDCC, FRVBF_INSN_CORCC, FRVBF_INSN_CXORCC, FRVBF_INSN_CSLLCC
, FRVBF_INSN_CSRLCC, FRVBF_INSN_CSRACC, FRVBF_INSN_ADDX, FRVBF_INSN_SUBX
, FRVBF_INSN_ADDXCC, FRVBF_INSN_SUBXCC, FRVBF_INSN_ADDI, FRVBF_INSN_SUBI
, FRVBF_INSN_ANDI, FRVBF_INSN_ORI, FRVBF_INSN_XORI, FRVBF_INSN_SDIVI
, FRVBF_INSN_NSDIVI, FRVBF_INSN_UDIVI, FRVBF_INSN_NUDIVI, FRVBF_INSN_SMULI
, FRVBF_INSN_UMULI, FRVBF_INSN_SLLI, FRVBF_INSN_SRLI, FRVBF_INSN_SRAI
, FRVBF_INSN_SCANI, FRVBF_INSN_ADDICC, FRVBF_INSN_SUBICC, FRVBF_INSN_ANDICC
, FRVBF_INSN_ORICC, FRVBF_INSN_XORICC, FRVBF_INSN_SMULICC, FRVBF_INSN_UMULICC
, FRVBF_INSN_SLLICC, FRVBF_INSN_SRLICC, FRVBF_INSN_SRAICC, FRVBF_INSN_ADDXI
, FRVBF_INSN_SUBXI, FRVBF_INSN_ADDXICC, FRVBF_INSN_SUBXICC, FRVBF_INSN_CMPB
, FRVBF_INSN_CMPBA, FRVBF_INSN_SETLO, FRVBF_INSN_SETHI, FRVBF_INSN_SETLOS
, FRVBF_INSN_LDSB, FRVBF_INSN_LDUB, FRVBF_INSN_LDSH, FRVBF_INSN_LDUH
, FRVBF_INSN_LD, FRVBF_INSN_LDBF, FRVBF_INSN_LDHF, FRVBF_INSN_LDF
, FRVBF_INSN_LDC, FRVBF_INSN_NLDSB, FRVBF_INSN_NLDUB, FRVBF_INSN_NLDSH
, FRVBF_INSN_NLDUH, FRVBF_INSN_NLD, FRVBF_INSN_NLDBF, FRVBF_INSN_NLDHF
, FRVBF_INSN_NLDF, FRVBF_INSN_LDD, FRVBF_INSN_LDDF, FRVBF_INSN_LDDC
, FRVBF_INSN_NLDD, FRVBF_INSN_NLDDF, FRVBF_INSN_LDQ, FRVBF_INSN_LDQF
, FRVBF_INSN_LDQC, FRVBF_INSN_NLDQ, FRVBF_INSN_NLDQF, FRVBF_INSN_LDSBU
, FRVBF_INSN_LDUBU, FRVBF_INSN_LDSHU, FRVBF_INSN_LDUHU, FRVBF_INSN_LDU
, FRVBF_INSN_NLDSBU, FRVBF_INSN_NLDUBU, FRVBF_INSN_NLDSHU, FRVBF_INSN_NLDUHU
, FRVBF_INSN_NLDU, FRVBF_INSN_LDBFU, FRVBF_INSN_LDHFU, FRVBF_INSN_LDFU
, FRVBF_INSN_LDCU, FRVBF_INSN_NLDBFU, FRVBF_INSN_NLDHFU, FRVBF_INSN_NLDFU
, FRVBF_INSN_LDDU, FRVBF_INSN_NLDDU, FRVBF_INSN_LDDFU, FRVBF_INSN_LDDCU
, FRVBF_INSN_NLDDFU, FRVBF_INSN_LDQU, FRVBF_INSN_NLDQU, FRVBF_INSN_LDQFU
, FRVBF_INSN_LDQCU, FRVBF_INSN_NLDQFU, FRVBF_INSN_LDSBI, FRVBF_INSN_LDSHI
, FRVBF_INSN_LDI, FRVBF_INSN_LDUBI, FRVBF_INSN_LDUHI, FRVBF_INSN_LDBFI
, FRVBF_INSN_LDHFI, FRVBF_INSN_LDFI, FRVBF_INSN_NLDSBI, FRVBF_INSN_NLDUBI
, FRVBF_INSN_NLDSHI, FRVBF_INSN_NLDUHI, FRVBF_INSN_NLDI, FRVBF_INSN_NLDBFI
, FRVBF_INSN_NLDHFI, FRVBF_INSN_NLDFI, FRVBF_INSN_LDDI, FRVBF_INSN_LDDFI
, FRVBF_INSN_NLDDI, FRVBF_INSN_NLDDFI, FRVBF_INSN_LDQI, FRVBF_INSN_LDQFI
, FRVBF_INSN_NLDQFI, FRVBF_INSN_STB, FRVBF_INSN_STH, FRVBF_INSN_ST
, FRVBF_INSN_STBF, FRVBF_INSN_STHF, FRVBF_INSN_STF, FRVBF_INSN_STC
, FRVBF_INSN_RSTB, FRVBF_INSN_RSTH, FRVBF_INSN_RST, FRVBF_INSN_RSTBF
, FRVBF_INSN_RSTHF, FRVBF_INSN_RSTF, FRVBF_INSN_STD, FRVBF_INSN_STDF
, FRVBF_INSN_STDC, FRVBF_INSN_RSTD, FRVBF_INSN_RSTDF, FRVBF_INSN_STQ
, FRVBF_INSN_STQF, FRVBF_INSN_STQC, FRVBF_INSN_RSTQ, FRVBF_INSN_RSTQF
, FRVBF_INSN_STBU, FRVBF_INSN_STHU, FRVBF_INSN_STU, FRVBF_INSN_STBFU
, FRVBF_INSN_STHFU, FRVBF_INSN_STFU, FRVBF_INSN_STCU, FRVBF_INSN_STDU
, FRVBF_INSN_STDFU, FRVBF_INSN_STDCU, FRVBF_INSN_STQU, FRVBF_INSN_STQFU
, FRVBF_INSN_STQCU, FRVBF_INSN_CLDSB, FRVBF_INSN_CLDUB, FRVBF_INSN_CLDSH
, FRVBF_INSN_CLDUH, FRVBF_INSN_CLD, FRVBF_INSN_CLDBF, FRVBF_INSN_CLDHF
, FRVBF_INSN_CLDF, FRVBF_INSN_CLDD, FRVBF_INSN_CLDDF, FRVBF_INSN_CLDQ
, FRVBF_INSN_CLDSBU, FRVBF_INSN_CLDUBU, FRVBF_INSN_CLDSHU, FRVBF_INSN_CLDUHU
, FRVBF_INSN_CLDU, FRVBF_INSN_CLDBFU, FRVBF_INSN_CLDHFU, FRVBF_INSN_CLDFU
, FRVBF_INSN_CLDDU, FRVBF_INSN_CLDDFU, FRVBF_INSN_CLDQU, FRVBF_INSN_CSTB
, FRVBF_INSN_CSTH, FRVBF_INSN_CST, FRVBF_INSN_CSTBF, FRVBF_INSN_CSTHF
, FRVBF_INSN_CSTF, FRVBF_INSN_CSTD, FRVBF_INSN_CSTDF, FRVBF_INSN_CSTQ
, FRVBF_INSN_CSTBU, FRVBF_INSN_CSTHU, FRVBF_INSN_CSTU, FRVBF_INSN_CSTBFU
, FRVBF_INSN_CSTHFU, FRVBF_INSN_CSTFU, FRVBF_INSN_CSTDU, FRVBF_INSN_CSTDFU
, FRVBF_INSN_STBI, FRVBF_INSN_STHI, FRVBF_INSN_STI, FRVBF_INSN_STBFI
, FRVBF_INSN_STHFI, FRVBF_INSN_STFI, FRVBF_INSN_STDI, FRVBF_INSN_STDFI
, FRVBF_INSN_STQI, FRVBF_INSN_STQFI, FRVBF_INSN_SWAP, FRVBF_INSN_SWAPI
, FRVBF_INSN_CSWAP, FRVBF_INSN_MOVGF, FRVBF_INSN_MOVFG, FRVBF_INSN_MOVGFD
, FRVBF_INSN_MOVFGD, FRVBF_INSN_MOVGFQ, FRVBF_INSN_MOVFGQ, FRVBF_INSN_CMOVGF
, FRVBF_INSN_CMOVFG, FRVBF_INSN_CMOVGFD, FRVBF_INSN_CMOVFGD, FRVBF_INSN_MOVGS
, FRVBF_INSN_MOVSG, FRVBF_INSN_BRA, FRVBF_INSN_BNO, FRVBF_INSN_BEQ
, FRVBF_INSN_BNE, FRVBF_INSN_BLE, FRVBF_INSN_BGT, FRVBF_INSN_BLT
, FRVBF_INSN_BGE, FRVBF_INSN_BLS, FRVBF_INSN_BHI, FRVBF_INSN_BC
, FRVBF_INSN_BNC, FRVBF_INSN_BN, FRVBF_INSN_BP, FRVBF_INSN_BV
, FRVBF_INSN_BNV, FRVBF_INSN_FBRA, FRVBF_INSN_FBNO, FRVBF_INSN_FBNE
, FRVBF_INSN_FBEQ, FRVBF_INSN_FBLG, FRVBF_INSN_FBUE, FRVBF_INSN_FBUL
, FRVBF_INSN_FBGE, FRVBF_INSN_FBLT, FRVBF_INSN_FBUGE, FRVBF_INSN_FBUG
, FRVBF_INSN_FBLE, FRVBF_INSN_FBGT, FRVBF_INSN_FBULE, FRVBF_INSN_FBU
, FRVBF_INSN_FBO, FRVBF_INSN_BCTRLR, FRVBF_INSN_BRALR, FRVBF_INSN_BNOLR
, FRVBF_INSN_BEQLR, FRVBF_INSN_BNELR, FRVBF_INSN_BLELR, FRVBF_INSN_BGTLR
, FRVBF_INSN_BLTLR, FRVBF_INSN_BGELR, FRVBF_INSN_BLSLR, FRVBF_INSN_BHILR
, FRVBF_INSN_BCLR, FRVBF_INSN_BNCLR, FRVBF_INSN_BNLR, FRVBF_INSN_BPLR
, FRVBF_INSN_BVLR, FRVBF_INSN_BNVLR, FRVBF_INSN_FBRALR, FRVBF_INSN_FBNOLR
, FRVBF_INSN_FBEQLR, FRVBF_INSN_FBNELR, FRVBF_INSN_FBLGLR, FRVBF_INSN_FBUELR
, FRVBF_INSN_FBULLR, FRVBF_INSN_FBGELR, FRVBF_INSN_FBLTLR, FRVBF_INSN_FBUGELR
, FRVBF_INSN_FBUGLR, FRVBF_INSN_FBLELR, FRVBF_INSN_FBGTLR, FRVBF_INSN_FBULELR
, FRVBF_INSN_FBULR, FRVBF_INSN_FBOLR, FRVBF_INSN_BCRALR, FRVBF_INSN_BCNOLR
, FRVBF_INSN_BCEQLR, FRVBF_INSN_BCNELR, FRVBF_INSN_BCLELR, FRVBF_INSN_BCGTLR
, FRVBF_INSN_BCLTLR, FRVBF_INSN_BCGELR, FRVBF_INSN_BCLSLR, FRVBF_INSN_BCHILR
, FRVBF_INSN_BCCLR, FRVBF_INSN_BCNCLR, FRVBF_INSN_BCNLR, FRVBF_INSN_BCPLR
, FRVBF_INSN_BCVLR, FRVBF_INSN_BCNVLR, FRVBF_INSN_FCBRALR, FRVBF_INSN_FCBNOLR
, FRVBF_INSN_FCBEQLR, FRVBF_INSN_FCBNELR, FRVBF_INSN_FCBLGLR, FRVBF_INSN_FCBUELR
, FRVBF_INSN_FCBULLR, FRVBF_INSN_FCBGELR, FRVBF_INSN_FCBLTLR, FRVBF_INSN_FCBUGELR
, FRVBF_INSN_FCBUGLR, FRVBF_INSN_FCBLELR, FRVBF_INSN_FCBGTLR, FRVBF_INSN_FCBULELR
, FRVBF_INSN_FCBULR, FRVBF_INSN_FCBOLR, FRVBF_INSN_JMPL, FRVBF_INSN_CALLL
, FRVBF_INSN_JMPIL, FRVBF_INSN_CALLIL, FRVBF_INSN_CALL, FRVBF_INSN_RETT
, FRVBF_INSN_REI, FRVBF_INSN_TRA, FRVBF_INSN_TNO, FRVBF_INSN_TEQ
, FRVBF_INSN_TNE, FRVBF_INSN_TLE, FRVBF_INSN_TGT, FRVBF_INSN_TLT
, FRVBF_INSN_TGE, FRVBF_INSN_TLS, FRVBF_INSN_THI, FRVBF_INSN_TC
, FRVBF_INSN_TNC, FRVBF_INSN_TN, FRVBF_INSN_TP, FRVBF_INSN_TV
, FRVBF_INSN_TNV, FRVBF_INSN_FTRA, FRVBF_INSN_FTNO, FRVBF_INSN_FTNE
, FRVBF_INSN_FTEQ, FRVBF_INSN_FTLG, FRVBF_INSN_FTUE, FRVBF_INSN_FTUL
, FRVBF_INSN_FTGE, FRVBF_INSN_FTLT, FRVBF_INSN_FTUGE, FRVBF_INSN_FTUG
, FRVBF_INSN_FTLE, FRVBF_INSN_FTGT, FRVBF_INSN_FTULE, FRVBF_INSN_FTU
, FRVBF_INSN_FTO, FRVBF_INSN_TIRA, FRVBF_INSN_TINO, FRVBF_INSN_TIEQ
, FRVBF_INSN_TINE, FRVBF_INSN_TILE, FRVBF_INSN_TIGT, FRVBF_INSN_TILT
, FRVBF_INSN_TIGE, FRVBF_INSN_TILS, FRVBF_INSN_TIHI, FRVBF_INSN_TIC
, FRVBF_INSN_TINC, FRVBF_INSN_TIN, FRVBF_INSN_TIP, FRVBF_INSN_TIV
, FRVBF_INSN_TINV, FRVBF_INSN_FTIRA, FRVBF_INSN_FTINO, FRVBF_INSN_FTINE
, FRVBF_INSN_FTIEQ, FRVBF_INSN_FTILG, FRVBF_INSN_FTIUE, FRVBF_INSN_FTIUL
, FRVBF_INSN_FTIGE, FRVBF_INSN_FTILT, FRVBF_INSN_FTIUGE, FRVBF_INSN_FTIUG
, FRVBF_INSN_FTILE, FRVBF_INSN_FTIGT, FRVBF_INSN_FTIULE, FRVBF_INSN_FTIU
, FRVBF_INSN_FTIO, FRVBF_INSN_BREAK, FRVBF_INSN_MTRAP, FRVBF_INSN_ANDCR
, FRVBF_INSN_ORCR, FRVBF_INSN_XORCR, FRVBF_INSN_NANDCR, FRVBF_INSN_NORCR
, FRVBF_INSN_ANDNCR, FRVBF_INSN_ORNCR, FRVBF_INSN_NANDNCR, FRVBF_INSN_NORNCR
, FRVBF_INSN_NOTCR, FRVBF_INSN_CKRA, FRVBF_INSN_CKNO, FRVBF_INSN_CKEQ
, FRVBF_INSN_CKNE, FRVBF_INSN_CKLE, FRVBF_INSN_CKGT, FRVBF_INSN_CKLT
, FRVBF_INSN_CKGE, FRVBF_INSN_CKLS, FRVBF_INSN_CKHI, FRVBF_INSN_CKC
, FRVBF_INSN_CKNC, FRVBF_INSN_CKN, FRVBF_INSN_CKP, FRVBF_INSN_CKV
, FRVBF_INSN_CKNV, FRVBF_INSN_FCKRA, FRVBF_INSN_FCKNO, FRVBF_INSN_FCKNE
, FRVBF_INSN_FCKEQ, FRVBF_INSN_FCKLG, FRVBF_INSN_FCKUE, FRVBF_INSN_FCKUL
, FRVBF_INSN_FCKGE, FRVBF_INSN_FCKLT, FRVBF_INSN_FCKUGE, FRVBF_INSN_FCKUG
, FRVBF_INSN_FCKLE, FRVBF_INSN_FCKGT, FRVBF_INSN_FCKULE, FRVBF_INSN_FCKU
, FRVBF_INSN_FCKO, FRVBF_INSN_CCKRA, FRVBF_INSN_CCKNO, FRVBF_INSN_CCKEQ
, FRVBF_INSN_CCKNE, FRVBF_INSN_CCKLE, FRVBF_INSN_CCKGT, FRVBF_INSN_CCKLT
, FRVBF_INSN_CCKGE, FRVBF_INSN_CCKLS, FRVBF_INSN_CCKHI, FRVBF_INSN_CCKC
, FRVBF_INSN_CCKNC, FRVBF_INSN_CCKN, FRVBF_INSN_CCKP, FRVBF_INSN_CCKV
, FRVBF_INSN_CCKNV, FRVBF_INSN_CFCKRA, FRVBF_INSN_CFCKNO, FRVBF_INSN_CFCKNE
, FRVBF_INSN_CFCKEQ, FRVBF_INSN_CFCKLG, FRVBF_INSN_CFCKUE, FRVBF_INSN_CFCKUL
, FRVBF_INSN_CFCKGE, FRVBF_INSN_CFCKLT, FRVBF_INSN_CFCKUGE, FRVBF_INSN_CFCKUG
, FRVBF_INSN_CFCKLE, FRVBF_INSN_CFCKGT, FRVBF_INSN_CFCKULE, FRVBF_INSN_CFCKU
, FRVBF_INSN_CFCKO, FRVBF_INSN_CJMPL, FRVBF_INSN_CCALLL, FRVBF_INSN_ICI
, FRVBF_INSN_DCI, FRVBF_INSN_ICEI, FRVBF_INSN_DCEI, FRVBF_INSN_DCF
, FRVBF_INSN_DCEF, FRVBF_INSN_WITLB, FRVBF_INSN_WDTLB, FRVBF_INSN_ITLBI
, FRVBF_INSN_DTLBI, FRVBF_INSN_ICPL, FRVBF_INSN_DCPL, FRVBF_INSN_ICUL
, FRVBF_INSN_DCUL, FRVBF_INSN_BAR, FRVBF_INSN_MEMBAR, FRVBF_INSN_COP1
, FRVBF_INSN_COP2, FRVBF_INSN_CLRGR, FRVBF_INSN_CLRFR, FRVBF_INSN_CLRGA
, FRVBF_INSN_CLRFA, FRVBF_INSN_COMMITGR, FRVBF_INSN_COMMITFR, FRVBF_INSN_COMMITGA
, FRVBF_INSN_COMMITFA, FRVBF_INSN_FITOS, FRVBF_INSN_FSTOI, FRVBF_INSN_FITOD
, FRVBF_INSN_FDTOI, FRVBF_INSN_FDITOS, FRVBF_INSN_FDSTOI, FRVBF_INSN_NFDITOS
, FRVBF_INSN_NFDSTOI, FRVBF_INSN_CFITOS, FRVBF_INSN_CFSTOI, FRVBF_INSN_NFITOS
, FRVBF_INSN_NFSTOI, FRVBF_INSN_FMOVS, FRVBF_INSN_FMOVD, FRVBF_INSN_FDMOVS
, FRVBF_INSN_CFMOVS, FRVBF_INSN_FNEGS, FRVBF_INSN_FNEGD, FRVBF_INSN_FDNEGS
, FRVBF_INSN_CFNEGS, FRVBF_INSN_FABSS, FRVBF_INSN_FABSD, FRVBF_INSN_FDABSS
, FRVBF_INSN_CFABSS, FRVBF_INSN_FSQRTS, FRVBF_INSN_FDSQRTS, FRVBF_INSN_NFDSQRTS
, FRVBF_INSN_FSQRTD, FRVBF_INSN_CFSQRTS, FRVBF_INSN_NFSQRTS, FRVBF_INSN_FADDS
, FRVBF_INSN_FSUBS, FRVBF_INSN_FMULS, FRVBF_INSN_FDIVS, FRVBF_INSN_FADDD
, FRVBF_INSN_FSUBD, FRVBF_INSN_FMULD, FRVBF_INSN_FDIVD, FRVBF_INSN_CFADDS
, FRVBF_INSN_CFSUBS, FRVBF_INSN_CFMULS, FRVBF_INSN_CFDIVS, FRVBF_INSN_NFADDS
, FRVBF_INSN_NFSUBS, FRVBF_INSN_NFMULS, FRVBF_INSN_NFDIVS, FRVBF_INSN_FCMPS
, FRVBF_INSN_FCMPD, FRVBF_INSN_CFCMPS, FRVBF_INSN_FDCMPS, FRVBF_INSN_FMADDS
, FRVBF_INSN_FMSUBS, FRVBF_INSN_FMADDD, FRVBF_INSN_FMSUBD, FRVBF_INSN_FDMADDS
, FRVBF_INSN_NFDMADDS, FRVBF_INSN_CFMADDS, FRVBF_INSN_CFMSUBS, FRVBF_INSN_NFMADDS
, FRVBF_INSN_NFMSUBS, FRVBF_INSN_FMAS, FRVBF_INSN_FMSS, FRVBF_INSN_FDMAS
, FRVBF_INSN_FDMSS, FRVBF_INSN_NFDMAS, FRVBF_INSN_NFDMSS, FRVBF_INSN_CFMAS
, FRVBF_INSN_CFMSS, FRVBF_INSN_FMAD, FRVBF_INSN_FMSD, FRVBF_INSN_NFMAS
, FRVBF_INSN_NFMSS, FRVBF_INSN_FDADDS, FRVBF_INSN_FDSUBS, FRVBF_INSN_FDMULS
, FRVBF_INSN_FDDIVS, FRVBF_INSN_FDSADS, FRVBF_INSN_FDMULCS, FRVBF_INSN_NFDMULCS
, FRVBF_INSN_NFDADDS, FRVBF_INSN_NFDSUBS, FRVBF_INSN_NFDMULS, FRVBF_INSN_NFDDIVS
, FRVBF_INSN_NFDSADS, FRVBF_INSN_NFDCMPS, FRVBF_INSN_MHSETLOS, FRVBF_INSN_MHSETHIS
, FRVBF_INSN_MHDSETS, FRVBF_INSN_MHSETLOH, FRVBF_INSN_MHSETHIH, FRVBF_INSN_MHDSETH
, FRVBF_INSN_MAND, FRVBF_INSN_MOR, FRVBF_INSN_MXOR, FRVBF_INSN_CMAND
, FRVBF_INSN_CMOR, FRVBF_INSN_CMXOR, FRVBF_INSN_MNOT, FRVBF_INSN_CMNOT
, FRVBF_INSN_MROTLI, FRVBF_INSN_MROTRI, FRVBF_INSN_MWCUT, FRVBF_INSN_MWCUTI
, FRVBF_INSN_MCUT, FRVBF_INSN_MCUTI, FRVBF_INSN_MCUTSS, FRVBF_INSN_MCUTSSI
, FRVBF_INSN_MDCUTSSI, FRVBF_INSN_MAVEH, FRVBF_INSN_MSLLHI, FRVBF_INSN_MSRLHI
, FRVBF_INSN_MSRAHI, FRVBF_INSN_MDROTLI, FRVBF_INSN_MCPLHI, FRVBF_INSN_MCPLI
, FRVBF_INSN_MSATHS, FRVBF_INSN_MQSATHS, FRVBF_INSN_MSATHU, FRVBF_INSN_MCMPSH
, FRVBF_INSN_MCMPUH, FRVBF_INSN_MABSHS, FRVBF_INSN_MADDHSS, FRVBF_INSN_MADDHUS
, FRVBF_INSN_MSUBHSS, FRVBF_INSN_MSUBHUS, FRVBF_INSN_CMADDHSS, FRVBF_INSN_CMADDHUS
, FRVBF_INSN_CMSUBHSS, FRVBF_INSN_CMSUBHUS, FRVBF_INSN_MQADDHSS, FRVBF_INSN_MQADDHUS
, FRVBF_INSN_MQSUBHSS, FRVBF_INSN_MQSUBHUS, FRVBF_INSN_CMQADDHSS, FRVBF_INSN_CMQADDHUS
, FRVBF_INSN_CMQSUBHSS, FRVBF_INSN_CMQSUBHUS, FRVBF_INSN_MADDACCS, FRVBF_INSN_MSUBACCS
, FRVBF_INSN_MDADDACCS, FRVBF_INSN_MDSUBACCS, FRVBF_INSN_MASACCS, FRVBF_INSN_MDASACCS
, FRVBF_INSN_MMULHS, FRVBF_INSN_MMULHU, FRVBF_INSN_MMULXHS, FRVBF_INSN_MMULXHU
, FRVBF_INSN_CMMULHS, FRVBF_INSN_CMMULHU, FRVBF_INSN_MQMULHS, FRVBF_INSN_MQMULHU
, FRVBF_INSN_MQMULXHS, FRVBF_INSN_MQMULXHU, FRVBF_INSN_CMQMULHS, FRVBF_INSN_CMQMULHU
, FRVBF_INSN_MMACHS, FRVBF_INSN_MMACHU, FRVBF_INSN_MMRDHS, FRVBF_INSN_MMRDHU
, FRVBF_INSN_CMMACHS, FRVBF_INSN_CMMACHU, FRVBF_INSN_MQMACHS, FRVBF_INSN_MQMACHU
, FRVBF_INSN_CMQMACHS, FRVBF_INSN_CMQMACHU, FRVBF_INSN_MQXMACHS, FRVBF_INSN_MQXMACXHS
, FRVBF_INSN_MQMACXHS, FRVBF_INSN_MCPXRS, FRVBF_INSN_MCPXRU, FRVBF_INSN_MCPXIS
, FRVBF_INSN_MCPXIU, FRVBF_INSN_CMCPXRS, FRVBF_INSN_CMCPXRU, FRVBF_INSN_CMCPXIS
, FRVBF_INSN_CMCPXIU, FRVBF_INSN_MQCPXRS, FRVBF_INSN_MQCPXRU, FRVBF_INSN_MQCPXIS
, FRVBF_INSN_MQCPXIU, FRVBF_INSN_MEXPDHW, FRVBF_INSN_CMEXPDHW, FRVBF_INSN_MEXPDHD
, FRVBF_INSN_CMEXPDHD, FRVBF_INSN_MPACKH, FRVBF_INSN_MDPACKH, FRVBF_INSN_MUNPACKH
, FRVBF_INSN_MDUNPACKH, FRVBF_INSN_MBTOH, FRVBF_INSN_CMBTOH, FRVBF_INSN_MHTOB
, FRVBF_INSN_CMHTOB, FRVBF_INSN_MBTOHE, FRVBF_INSN_CMBTOHE, FRVBF_INSN_MNOP
, FRVBF_INSN_MCLRACC_0, FRVBF_INSN_MCLRACC_1, FRVBF_INSN_MRDACC, FRVBF_INSN_MRDACCG
, FRVBF_INSN_MWTACC, FRVBF_INSN_MWTACCG, FRVBF_INSN_MCOP1, FRVBF_INSN_MCOP2
, FRVBF_INSN_FNOP, FRVBF_INSN__MAX
, FRVBF_INSN_SMUL, FRVBF_INSN_UMUL, FRVBF_INSN_SMU, FRVBF_INSN_SMASS
, FRVBF_INSN_SMSSS, FRVBF_INSN_SLL, FRVBF_INSN_SRL, FRVBF_INSN_SRA
, FRVBF_INSN_SLASS, FRVBF_INSN_SCUTSS, FRVBF_INSN_SCAN, FRVBF_INSN_CADD
, FRVBF_INSN_CSUB, FRVBF_INSN_CAND, FRVBF_INSN_COR, FRVBF_INSN_CXOR
, FRVBF_INSN_CNOT, FRVBF_INSN_CSMUL, FRVBF_INSN_CSDIV, FRVBF_INSN_CUDIV
, FRVBF_INSN_CSLL, FRVBF_INSN_CSRL, FRVBF_INSN_CSRA, FRVBF_INSN_CSCAN
, FRVBF_INSN_ADDCC, FRVBF_INSN_SUBCC, FRVBF_INSN_ANDCC, FRVBF_INSN_ORCC
, FRVBF_INSN_XORCC, FRVBF_INSN_SLLCC, FRVBF_INSN_SRLCC, FRVBF_INSN_SRACC
, FRVBF_INSN_SMULCC, FRVBF_INSN_UMULCC, FRVBF_INSN_CADDCC, FRVBF_INSN_CSUBCC
, FRVBF_INSN_CSMULCC, FRVBF_INSN_CANDCC, FRVBF_INSN_CORCC, FRVBF_INSN_CXORCC
, FRVBF_INSN_CSLLCC, FRVBF_INSN_CSRLCC, FRVBF_INSN_CSRACC, FRVBF_INSN_ADDX
, FRVBF_INSN_SUBX, FRVBF_INSN_ADDXCC, FRVBF_INSN_SUBXCC, FRVBF_INSN_ADDSS
, FRVBF_INSN_SUBSS, FRVBF_INSN_ADDI, FRVBF_INSN_SUBI, FRVBF_INSN_ANDI
, FRVBF_INSN_ORI, FRVBF_INSN_XORI, FRVBF_INSN_SDIVI, FRVBF_INSN_NSDIVI
, FRVBF_INSN_UDIVI, FRVBF_INSN_NUDIVI, FRVBF_INSN_SMULI, FRVBF_INSN_UMULI
, FRVBF_INSN_SLLI, FRVBF_INSN_SRLI, FRVBF_INSN_SRAI, FRVBF_INSN_SCANI
, FRVBF_INSN_ADDICC, FRVBF_INSN_SUBICC, FRVBF_INSN_ANDICC, FRVBF_INSN_ORICC
, FRVBF_INSN_XORICC, FRVBF_INSN_SMULICC, FRVBF_INSN_UMULICC, FRVBF_INSN_SLLICC
, FRVBF_INSN_SRLICC, FRVBF_INSN_SRAICC, FRVBF_INSN_ADDXI, FRVBF_INSN_SUBXI
, FRVBF_INSN_ADDXICC, FRVBF_INSN_SUBXICC, FRVBF_INSN_CMPB, FRVBF_INSN_CMPBA
, FRVBF_INSN_SETLO, FRVBF_INSN_SETHI, FRVBF_INSN_SETLOS, FRVBF_INSN_LDSB
, FRVBF_INSN_LDUB, FRVBF_INSN_LDSH, FRVBF_INSN_LDUH, FRVBF_INSN_LD
, FRVBF_INSN_LDBF, FRVBF_INSN_LDHF, FRVBF_INSN_LDF, FRVBF_INSN_LDC
, FRVBF_INSN_NLDSB, FRVBF_INSN_NLDUB, FRVBF_INSN_NLDSH, FRVBF_INSN_NLDUH
, FRVBF_INSN_NLD, FRVBF_INSN_NLDBF, FRVBF_INSN_NLDHF, FRVBF_INSN_NLDF
, FRVBF_INSN_LDD, FRVBF_INSN_LDDF, FRVBF_INSN_LDDC, FRVBF_INSN_NLDD
, FRVBF_INSN_NLDDF, FRVBF_INSN_LDQ, FRVBF_INSN_LDQF, FRVBF_INSN_LDQC
, FRVBF_INSN_NLDQ, FRVBF_INSN_NLDQF, FRVBF_INSN_LDSBU, FRVBF_INSN_LDUBU
, FRVBF_INSN_LDSHU, FRVBF_INSN_LDUHU, FRVBF_INSN_LDU, FRVBF_INSN_NLDSBU
, FRVBF_INSN_NLDUBU, FRVBF_INSN_NLDSHU, FRVBF_INSN_NLDUHU, FRVBF_INSN_NLDU
, FRVBF_INSN_LDBFU, FRVBF_INSN_LDHFU, FRVBF_INSN_LDFU, FRVBF_INSN_LDCU
, FRVBF_INSN_NLDBFU, FRVBF_INSN_NLDHFU, FRVBF_INSN_NLDFU, FRVBF_INSN_LDDU
, FRVBF_INSN_NLDDU, FRVBF_INSN_LDDFU, FRVBF_INSN_LDDCU, FRVBF_INSN_NLDDFU
, FRVBF_INSN_LDQU, FRVBF_INSN_NLDQU, FRVBF_INSN_LDQFU, FRVBF_INSN_LDQCU
, FRVBF_INSN_NLDQFU, FRVBF_INSN_LDSBI, FRVBF_INSN_LDSHI, FRVBF_INSN_LDI
, FRVBF_INSN_LDUBI, FRVBF_INSN_LDUHI, FRVBF_INSN_LDBFI, FRVBF_INSN_LDHFI
, FRVBF_INSN_LDFI, FRVBF_INSN_NLDSBI, FRVBF_INSN_NLDUBI, FRVBF_INSN_NLDSHI
, FRVBF_INSN_NLDUHI, FRVBF_INSN_NLDI, FRVBF_INSN_NLDBFI, FRVBF_INSN_NLDHFI
, FRVBF_INSN_NLDFI, FRVBF_INSN_LDDI, FRVBF_INSN_LDDFI, FRVBF_INSN_NLDDI
, FRVBF_INSN_NLDDFI, FRVBF_INSN_LDQI, FRVBF_INSN_LDQFI, FRVBF_INSN_NLDQFI
, FRVBF_INSN_STB, FRVBF_INSN_STH, FRVBF_INSN_ST, FRVBF_INSN_STBF
, FRVBF_INSN_STHF, FRVBF_INSN_STF, FRVBF_INSN_STC, FRVBF_INSN_RSTB
, FRVBF_INSN_RSTH, FRVBF_INSN_RST, FRVBF_INSN_RSTBF, FRVBF_INSN_RSTHF
, FRVBF_INSN_RSTF, FRVBF_INSN_STD, FRVBF_INSN_STDF, FRVBF_INSN_STDC
, FRVBF_INSN_RSTD, FRVBF_INSN_RSTDF, FRVBF_INSN_STQ, FRVBF_INSN_STQF
, FRVBF_INSN_STQC, FRVBF_INSN_RSTQ, FRVBF_INSN_RSTQF, FRVBF_INSN_STBU
, FRVBF_INSN_STHU, FRVBF_INSN_STU, FRVBF_INSN_STBFU, FRVBF_INSN_STHFU
, FRVBF_INSN_STFU, FRVBF_INSN_STCU, FRVBF_INSN_STDU, FRVBF_INSN_STDFU
, FRVBF_INSN_STDCU, FRVBF_INSN_STQU, FRVBF_INSN_STQFU, FRVBF_INSN_STQCU
, FRVBF_INSN_CLDSB, FRVBF_INSN_CLDUB, FRVBF_INSN_CLDSH, FRVBF_INSN_CLDUH
, FRVBF_INSN_CLD, FRVBF_INSN_CLDBF, FRVBF_INSN_CLDHF, FRVBF_INSN_CLDF
, FRVBF_INSN_CLDD, FRVBF_INSN_CLDDF, FRVBF_INSN_CLDQ, FRVBF_INSN_CLDSBU
, FRVBF_INSN_CLDUBU, FRVBF_INSN_CLDSHU, FRVBF_INSN_CLDUHU, FRVBF_INSN_CLDU
, FRVBF_INSN_CLDBFU, FRVBF_INSN_CLDHFU, FRVBF_INSN_CLDFU, FRVBF_INSN_CLDDU
, FRVBF_INSN_CLDDFU, FRVBF_INSN_CLDQU, FRVBF_INSN_CSTB, FRVBF_INSN_CSTH
, FRVBF_INSN_CST, FRVBF_INSN_CSTBF, FRVBF_INSN_CSTHF, FRVBF_INSN_CSTF
, FRVBF_INSN_CSTD, FRVBF_INSN_CSTDF, FRVBF_INSN_CSTQ, FRVBF_INSN_CSTBU
, FRVBF_INSN_CSTHU, FRVBF_INSN_CSTU, FRVBF_INSN_CSTBFU, FRVBF_INSN_CSTHFU
, FRVBF_INSN_CSTFU, FRVBF_INSN_CSTDU, FRVBF_INSN_CSTDFU, FRVBF_INSN_STBI
, FRVBF_INSN_STHI, FRVBF_INSN_STI, FRVBF_INSN_STBFI, FRVBF_INSN_STHFI
, FRVBF_INSN_STFI, FRVBF_INSN_STDI, FRVBF_INSN_STDFI, FRVBF_INSN_STQI
, FRVBF_INSN_STQFI, FRVBF_INSN_SWAP, FRVBF_INSN_SWAPI, FRVBF_INSN_CSWAP
, FRVBF_INSN_MOVGF, FRVBF_INSN_MOVFG, FRVBF_INSN_MOVGFD, FRVBF_INSN_MOVFGD
, FRVBF_INSN_MOVGFQ, FRVBF_INSN_MOVFGQ, FRVBF_INSN_CMOVGF, FRVBF_INSN_CMOVFG
, FRVBF_INSN_CMOVGFD, FRVBF_INSN_CMOVFGD, FRVBF_INSN_MOVGS, FRVBF_INSN_MOVSG
, FRVBF_INSN_BRA, FRVBF_INSN_BNO, FRVBF_INSN_BEQ, FRVBF_INSN_BNE
, FRVBF_INSN_BLE, FRVBF_INSN_BGT, FRVBF_INSN_BLT, FRVBF_INSN_BGE
, FRVBF_INSN_BLS, FRVBF_INSN_BHI, FRVBF_INSN_BC, FRVBF_INSN_BNC
, FRVBF_INSN_BN, FRVBF_INSN_BP, FRVBF_INSN_BV, FRVBF_INSN_BNV
, FRVBF_INSN_FBRA, FRVBF_INSN_FBNO, FRVBF_INSN_FBNE, FRVBF_INSN_FBEQ
, FRVBF_INSN_FBLG, FRVBF_INSN_FBUE, FRVBF_INSN_FBUL, FRVBF_INSN_FBGE
, FRVBF_INSN_FBLT, FRVBF_INSN_FBUGE, FRVBF_INSN_FBUG, FRVBF_INSN_FBLE
, FRVBF_INSN_FBGT, FRVBF_INSN_FBULE, FRVBF_INSN_FBU, FRVBF_INSN_FBO
, FRVBF_INSN_BCTRLR, FRVBF_INSN_BRALR, FRVBF_INSN_BNOLR, FRVBF_INSN_BEQLR
, FRVBF_INSN_BNELR, FRVBF_INSN_BLELR, FRVBF_INSN_BGTLR, FRVBF_INSN_BLTLR
, FRVBF_INSN_BGELR, FRVBF_INSN_BLSLR, FRVBF_INSN_BHILR, FRVBF_INSN_BCLR
, FRVBF_INSN_BNCLR, FRVBF_INSN_BNLR, FRVBF_INSN_BPLR, FRVBF_INSN_BVLR
, FRVBF_INSN_BNVLR, FRVBF_INSN_FBRALR, FRVBF_INSN_FBNOLR, FRVBF_INSN_FBEQLR
, FRVBF_INSN_FBNELR, FRVBF_INSN_FBLGLR, FRVBF_INSN_FBUELR, FRVBF_INSN_FBULLR
, FRVBF_INSN_FBGELR, FRVBF_INSN_FBLTLR, FRVBF_INSN_FBUGELR, FRVBF_INSN_FBUGLR
, FRVBF_INSN_FBLELR, FRVBF_INSN_FBGTLR, FRVBF_INSN_FBULELR, FRVBF_INSN_FBULR
, FRVBF_INSN_FBOLR, FRVBF_INSN_BCRALR, FRVBF_INSN_BCNOLR, FRVBF_INSN_BCEQLR
, FRVBF_INSN_BCNELR, FRVBF_INSN_BCLELR, FRVBF_INSN_BCGTLR, FRVBF_INSN_BCLTLR
, FRVBF_INSN_BCGELR, FRVBF_INSN_BCLSLR, FRVBF_INSN_BCHILR, FRVBF_INSN_BCCLR
, FRVBF_INSN_BCNCLR, FRVBF_INSN_BCNLR, FRVBF_INSN_BCPLR, FRVBF_INSN_BCVLR
, FRVBF_INSN_BCNVLR, FRVBF_INSN_FCBRALR, FRVBF_INSN_FCBNOLR, FRVBF_INSN_FCBEQLR
, FRVBF_INSN_FCBNELR, FRVBF_INSN_FCBLGLR, FRVBF_INSN_FCBUELR, FRVBF_INSN_FCBULLR
, FRVBF_INSN_FCBGELR, FRVBF_INSN_FCBLTLR, FRVBF_INSN_FCBUGELR, FRVBF_INSN_FCBUGLR
, FRVBF_INSN_FCBLELR, FRVBF_INSN_FCBGTLR, FRVBF_INSN_FCBULELR, FRVBF_INSN_FCBULR
, FRVBF_INSN_FCBOLR, FRVBF_INSN_JMPL, FRVBF_INSN_CALLL, FRVBF_INSN_JMPIL
, FRVBF_INSN_CALLIL, FRVBF_INSN_CALL, FRVBF_INSN_RETT, FRVBF_INSN_REI
, FRVBF_INSN_TRA, FRVBF_INSN_TNO, FRVBF_INSN_TEQ, FRVBF_INSN_TNE
, FRVBF_INSN_TLE, FRVBF_INSN_TGT, FRVBF_INSN_TLT, FRVBF_INSN_TGE
, FRVBF_INSN_TLS, FRVBF_INSN_THI, FRVBF_INSN_TC, FRVBF_INSN_TNC
, FRVBF_INSN_TN, FRVBF_INSN_TP, FRVBF_INSN_TV, FRVBF_INSN_TNV
, FRVBF_INSN_FTRA, FRVBF_INSN_FTNO, FRVBF_INSN_FTNE, FRVBF_INSN_FTEQ
, FRVBF_INSN_FTLG, FRVBF_INSN_FTUE, FRVBF_INSN_FTUL, FRVBF_INSN_FTGE
, FRVBF_INSN_FTLT, FRVBF_INSN_FTUGE, FRVBF_INSN_FTUG, FRVBF_INSN_FTLE
, FRVBF_INSN_FTGT, FRVBF_INSN_FTULE, FRVBF_INSN_FTU, FRVBF_INSN_FTO
, FRVBF_INSN_TIRA, FRVBF_INSN_TINO, FRVBF_INSN_TIEQ, FRVBF_INSN_TINE
, FRVBF_INSN_TILE, FRVBF_INSN_TIGT, FRVBF_INSN_TILT, FRVBF_INSN_TIGE
, FRVBF_INSN_TILS, FRVBF_INSN_TIHI, FRVBF_INSN_TIC, FRVBF_INSN_TINC
, FRVBF_INSN_TIN, FRVBF_INSN_TIP, FRVBF_INSN_TIV, FRVBF_INSN_TINV
, FRVBF_INSN_FTIRA, FRVBF_INSN_FTINO, FRVBF_INSN_FTINE, FRVBF_INSN_FTIEQ
, FRVBF_INSN_FTILG, FRVBF_INSN_FTIUE, FRVBF_INSN_FTIUL, FRVBF_INSN_FTIGE
, FRVBF_INSN_FTILT, FRVBF_INSN_FTIUGE, FRVBF_INSN_FTIUG, FRVBF_INSN_FTILE
, FRVBF_INSN_FTIGT, FRVBF_INSN_FTIULE, FRVBF_INSN_FTIU, FRVBF_INSN_FTIO
, FRVBF_INSN_BREAK, FRVBF_INSN_MTRAP, FRVBF_INSN_ANDCR, FRVBF_INSN_ORCR
, FRVBF_INSN_XORCR, FRVBF_INSN_NANDCR, FRVBF_INSN_NORCR, FRVBF_INSN_ANDNCR
, FRVBF_INSN_ORNCR, FRVBF_INSN_NANDNCR, FRVBF_INSN_NORNCR, FRVBF_INSN_NOTCR
, FRVBF_INSN_CKRA, FRVBF_INSN_CKNO, FRVBF_INSN_CKEQ, FRVBF_INSN_CKNE
, FRVBF_INSN_CKLE, FRVBF_INSN_CKGT, FRVBF_INSN_CKLT, FRVBF_INSN_CKGE
, FRVBF_INSN_CKLS, FRVBF_INSN_CKHI, FRVBF_INSN_CKC, FRVBF_INSN_CKNC
, FRVBF_INSN_CKN, FRVBF_INSN_CKP, FRVBF_INSN_CKV, FRVBF_INSN_CKNV
, FRVBF_INSN_FCKRA, FRVBF_INSN_FCKNO, FRVBF_INSN_FCKNE, FRVBF_INSN_FCKEQ
, FRVBF_INSN_FCKLG, FRVBF_INSN_FCKUE, FRVBF_INSN_FCKUL, FRVBF_INSN_FCKGE
, FRVBF_INSN_FCKLT, FRVBF_INSN_FCKUGE, FRVBF_INSN_FCKUG, FRVBF_INSN_FCKLE
, FRVBF_INSN_FCKGT, FRVBF_INSN_FCKULE, FRVBF_INSN_FCKU, FRVBF_INSN_FCKO
, FRVBF_INSN_CCKRA, FRVBF_INSN_CCKNO, FRVBF_INSN_CCKEQ, FRVBF_INSN_CCKNE
, FRVBF_INSN_CCKLE, FRVBF_INSN_CCKGT, FRVBF_INSN_CCKLT, FRVBF_INSN_CCKGE
, FRVBF_INSN_CCKLS, FRVBF_INSN_CCKHI, FRVBF_INSN_CCKC, FRVBF_INSN_CCKNC
, FRVBF_INSN_CCKN, FRVBF_INSN_CCKP, FRVBF_INSN_CCKV, FRVBF_INSN_CCKNV
, FRVBF_INSN_CFCKRA, FRVBF_INSN_CFCKNO, FRVBF_INSN_CFCKNE, FRVBF_INSN_CFCKEQ
, FRVBF_INSN_CFCKLG, FRVBF_INSN_CFCKUE, FRVBF_INSN_CFCKUL, FRVBF_INSN_CFCKGE
, FRVBF_INSN_CFCKLT, FRVBF_INSN_CFCKUGE, FRVBF_INSN_CFCKUG, FRVBF_INSN_CFCKLE
, FRVBF_INSN_CFCKGT, FRVBF_INSN_CFCKULE, FRVBF_INSN_CFCKU, FRVBF_INSN_CFCKO
, FRVBF_INSN_CJMPL, FRVBF_INSN_CCALLL, FRVBF_INSN_ICI, FRVBF_INSN_DCI
, FRVBF_INSN_ICEI, FRVBF_INSN_DCEI, FRVBF_INSN_DCF, FRVBF_INSN_DCEF
, FRVBF_INSN_WITLB, FRVBF_INSN_WDTLB, FRVBF_INSN_ITLBI, FRVBF_INSN_DTLBI
, FRVBF_INSN_ICPL, FRVBF_INSN_DCPL, FRVBF_INSN_ICUL, FRVBF_INSN_DCUL
, FRVBF_INSN_BAR, FRVBF_INSN_MEMBAR, FRVBF_INSN_COP1, FRVBF_INSN_COP2
, FRVBF_INSN_CLRGR, FRVBF_INSN_CLRFR, FRVBF_INSN_CLRGA, FRVBF_INSN_CLRFA
, FRVBF_INSN_COMMITGR, FRVBF_INSN_COMMITFR, FRVBF_INSN_COMMITGA, FRVBF_INSN_COMMITFA
, FRVBF_INSN_FITOS, FRVBF_INSN_FSTOI, FRVBF_INSN_FITOD, FRVBF_INSN_FDTOI
, FRVBF_INSN_FDITOS, FRVBF_INSN_FDSTOI, FRVBF_INSN_NFDITOS, FRVBF_INSN_NFDSTOI
, FRVBF_INSN_CFITOS, FRVBF_INSN_CFSTOI, FRVBF_INSN_NFITOS, FRVBF_INSN_NFSTOI
, FRVBF_INSN_FMOVS, FRVBF_INSN_FMOVD, FRVBF_INSN_FDMOVS, FRVBF_INSN_CFMOVS
, FRVBF_INSN_FNEGS, FRVBF_INSN_FNEGD, FRVBF_INSN_FDNEGS, FRVBF_INSN_CFNEGS
, FRVBF_INSN_FABSS, FRVBF_INSN_FABSD, FRVBF_INSN_FDABSS, FRVBF_INSN_CFABSS
, FRVBF_INSN_FSQRTS, FRVBF_INSN_FDSQRTS, FRVBF_INSN_NFDSQRTS, FRVBF_INSN_FSQRTD
, FRVBF_INSN_CFSQRTS, FRVBF_INSN_NFSQRTS, FRVBF_INSN_FADDS, FRVBF_INSN_FSUBS
, FRVBF_INSN_FMULS, FRVBF_INSN_FDIVS, FRVBF_INSN_FADDD, FRVBF_INSN_FSUBD
, FRVBF_INSN_FMULD, FRVBF_INSN_FDIVD, FRVBF_INSN_CFADDS, FRVBF_INSN_CFSUBS
, FRVBF_INSN_CFMULS, FRVBF_INSN_CFDIVS, FRVBF_INSN_NFADDS, FRVBF_INSN_NFSUBS
, FRVBF_INSN_NFMULS, FRVBF_INSN_NFDIVS, FRVBF_INSN_FCMPS, FRVBF_INSN_FCMPD
, FRVBF_INSN_CFCMPS, FRVBF_INSN_FDCMPS, FRVBF_INSN_FMADDS, FRVBF_INSN_FMSUBS
, FRVBF_INSN_FMADDD, FRVBF_INSN_FMSUBD, FRVBF_INSN_FDMADDS, FRVBF_INSN_NFDMADDS
, FRVBF_INSN_CFMADDS, FRVBF_INSN_CFMSUBS, FRVBF_INSN_NFMADDS, FRVBF_INSN_NFMSUBS
, FRVBF_INSN_FMAS, FRVBF_INSN_FMSS, FRVBF_INSN_FDMAS, FRVBF_INSN_FDMSS
, FRVBF_INSN_NFDMAS, FRVBF_INSN_NFDMSS, FRVBF_INSN_CFMAS, FRVBF_INSN_CFMSS
, FRVBF_INSN_FMAD, FRVBF_INSN_FMSD, FRVBF_INSN_NFMAS, FRVBF_INSN_NFMSS
, FRVBF_INSN_FDADDS, FRVBF_INSN_FDSUBS, FRVBF_INSN_FDMULS, FRVBF_INSN_FDDIVS
, FRVBF_INSN_FDSADS, FRVBF_INSN_FDMULCS, FRVBF_INSN_NFDMULCS, FRVBF_INSN_NFDADDS
, FRVBF_INSN_NFDSUBS, FRVBF_INSN_NFDMULS, FRVBF_INSN_NFDDIVS, FRVBF_INSN_NFDSADS
, FRVBF_INSN_NFDCMPS, FRVBF_INSN_MHSETLOS, FRVBF_INSN_MHSETHIS, FRVBF_INSN_MHDSETS
, FRVBF_INSN_MHSETLOH, FRVBF_INSN_MHSETHIH, FRVBF_INSN_MHDSETH, FRVBF_INSN_MAND
, FRVBF_INSN_MOR, FRVBF_INSN_MXOR, FRVBF_INSN_CMAND, FRVBF_INSN_CMOR
, FRVBF_INSN_CMXOR, FRVBF_INSN_MNOT, FRVBF_INSN_CMNOT, FRVBF_INSN_MROTLI
, FRVBF_INSN_MROTRI, FRVBF_INSN_MWCUT, FRVBF_INSN_MWCUTI, FRVBF_INSN_MCUT
, FRVBF_INSN_MCUTI, FRVBF_INSN_MCUTSS, FRVBF_INSN_MCUTSSI, FRVBF_INSN_MDCUTSSI
, FRVBF_INSN_MAVEH, FRVBF_INSN_MSLLHI, FRVBF_INSN_MSRLHI, FRVBF_INSN_MSRAHI
, FRVBF_INSN_MDROTLI, FRVBF_INSN_MCPLHI, FRVBF_INSN_MCPLI, FRVBF_INSN_MSATHS
, FRVBF_INSN_MQSATHS, FRVBF_INSN_MSATHU, FRVBF_INSN_MCMPSH, FRVBF_INSN_MCMPUH
, FRVBF_INSN_MABSHS, FRVBF_INSN_MADDHSS, FRVBF_INSN_MADDHUS, FRVBF_INSN_MSUBHSS
, FRVBF_INSN_MSUBHUS, FRVBF_INSN_CMADDHSS, FRVBF_INSN_CMADDHUS, FRVBF_INSN_CMSUBHSS
, FRVBF_INSN_CMSUBHUS, FRVBF_INSN_MQADDHSS, FRVBF_INSN_MQADDHUS, FRVBF_INSN_MQSUBHSS
, FRVBF_INSN_MQSUBHUS, FRVBF_INSN_CMQADDHSS, FRVBF_INSN_CMQADDHUS, FRVBF_INSN_CMQSUBHSS
, FRVBF_INSN_CMQSUBHUS, FRVBF_INSN_MADDACCS, FRVBF_INSN_MSUBACCS, FRVBF_INSN_MDADDACCS
, FRVBF_INSN_MDSUBACCS, FRVBF_INSN_MASACCS, FRVBF_INSN_MDASACCS, FRVBF_INSN_MMULHS
, FRVBF_INSN_MMULHU, FRVBF_INSN_MMULXHS, FRVBF_INSN_MMULXHU, FRVBF_INSN_CMMULHS
, FRVBF_INSN_CMMULHU, FRVBF_INSN_MQMULHS, FRVBF_INSN_MQMULHU, FRVBF_INSN_MQMULXHS
, FRVBF_INSN_MQMULXHU, FRVBF_INSN_CMQMULHS, FRVBF_INSN_CMQMULHU, FRVBF_INSN_MMACHS
, FRVBF_INSN_MMACHU, FRVBF_INSN_MMRDHS, FRVBF_INSN_MMRDHU, FRVBF_INSN_CMMACHS
, FRVBF_INSN_CMMACHU, FRVBF_INSN_MQMACHS, FRVBF_INSN_MQMACHU, FRVBF_INSN_CMQMACHS
, FRVBF_INSN_CMQMACHU, FRVBF_INSN_MQXMACHS, FRVBF_INSN_MQXMACXHS, FRVBF_INSN_MQMACXHS
, FRVBF_INSN_MCPXRS, FRVBF_INSN_MCPXRU, FRVBF_INSN_MCPXIS, FRVBF_INSN_MCPXIU
, FRVBF_INSN_CMCPXRS, FRVBF_INSN_CMCPXRU, FRVBF_INSN_CMCPXIS, FRVBF_INSN_CMCPXIU
, FRVBF_INSN_MQCPXRS, FRVBF_INSN_MQCPXRU, FRVBF_INSN_MQCPXIS, FRVBF_INSN_MQCPXIU
, FRVBF_INSN_MEXPDHW, FRVBF_INSN_CMEXPDHW, FRVBF_INSN_MEXPDHD, FRVBF_INSN_CMEXPDHD
, FRVBF_INSN_MPACKH, FRVBF_INSN_MDPACKH, FRVBF_INSN_MUNPACKH, FRVBF_INSN_MDUNPACKH
, FRVBF_INSN_MBTOH, FRVBF_INSN_CMBTOH, FRVBF_INSN_MHTOB, FRVBF_INSN_CMHTOB
, FRVBF_INSN_MBTOHE, FRVBF_INSN_CMBTOHE, FRVBF_INSN_MNOP, FRVBF_INSN_MCLRACC_0
, FRVBF_INSN_MCLRACC_1, FRVBF_INSN_MRDACC, FRVBF_INSN_MRDACCG, FRVBF_INSN_MWTACC
, FRVBF_INSN_MWTACCG, FRVBF_INSN_MCOP1, FRVBF_INSN_MCOP2, FRVBF_INSN_FNOP
, FRVBF_INSN__MAX
} FRVBF_INSN_TYPE;
/* Enum declaration for semantic formats in cpu family frvbf. */
typedef enum frvbf_sfmt_type {
FRVBF_SFMT_EMPTY, FRVBF_SFMT_ADD, FRVBF_SFMT_NOT, FRVBF_SFMT_SDIV
, FRVBF_SFMT_SMUL, FRVBF_SFMT_CADD, FRVBF_SFMT_CNOT, FRVBF_SFMT_CSMUL
, FRVBF_SFMT_CSDIV, FRVBF_SFMT_ADDCC, FRVBF_SFMT_ANDCC, FRVBF_SFMT_SMULCC
, FRVBF_SFMT_CADDCC, FRVBF_SFMT_CSMULCC, FRVBF_SFMT_ADDX, FRVBF_SFMT_ADDI
, FRVBF_SFMT_SDIVI, FRVBF_SFMT_SMULI, FRVBF_SFMT_ADDICC, FRVBF_SFMT_ANDICC
, FRVBF_SFMT_SMULICC, FRVBF_SFMT_ADDXI, FRVBF_SFMT_CMPB, FRVBF_SFMT_SETLO
, FRVBF_SFMT_SETHI, FRVBF_SFMT_SETLOS, FRVBF_SFMT_LDSB, FRVBF_SFMT_LDBF
, FRVBF_SFMT_LDC, FRVBF_SFMT_NLDSB, FRVBF_SFMT_NLDBF, FRVBF_SFMT_LDD
, FRVBF_SFMT_LDDF, FRVBF_SFMT_LDDC, FRVBF_SFMT_NLDD, FRVBF_SFMT_NLDDF
, FRVBF_SFMT_LDQ, FRVBF_SFMT_LDQF, FRVBF_SFMT_LDQC, FRVBF_SFMT_NLDQ
, FRVBF_SFMT_NLDQF, FRVBF_SFMT_LDSBU, FRVBF_SFMT_NLDSBU, FRVBF_SFMT_LDBFU
, FRVBF_SFMT_LDCU, FRVBF_SFMT_NLDBFU, FRVBF_SFMT_LDDU, FRVBF_SFMT_NLDDU
, FRVBF_SFMT_LDDFU, FRVBF_SFMT_LDDCU, FRVBF_SFMT_NLDDFU, FRVBF_SFMT_LDQU
, FRVBF_SFMT_NLDQU, FRVBF_SFMT_LDQFU, FRVBF_SFMT_LDQCU, FRVBF_SFMT_NLDQFU
, FRVBF_SFMT_LDSBI, FRVBF_SFMT_LDBFI, FRVBF_SFMT_NLDSBI, FRVBF_SFMT_NLDBFI
, FRVBF_SFMT_LDDI, FRVBF_SFMT_LDDFI, FRVBF_SFMT_NLDDI, FRVBF_SFMT_NLDDFI
, FRVBF_SFMT_LDQI, FRVBF_SFMT_LDQFI, FRVBF_SFMT_NLDQFI, FRVBF_SFMT_STB
, FRVBF_SFMT_STBF, FRVBF_SFMT_STC, FRVBF_SFMT_RSTB, FRVBF_SFMT_RSTBF
, FRVBF_SFMT_STD, FRVBF_SFMT_STDF, FRVBF_SFMT_STDC, FRVBF_SFMT_RSTD
, FRVBF_SFMT_RSTDF, FRVBF_SFMT_STBU, FRVBF_SFMT_STBFU, FRVBF_SFMT_STCU
, FRVBF_SFMT_STDU, FRVBF_SFMT_STDFU, FRVBF_SFMT_STDCU, FRVBF_SFMT_STQU
, FRVBF_SFMT_CLDSB, FRVBF_SFMT_CLDBF, FRVBF_SFMT_CLDD, FRVBF_SFMT_CLDDF
, FRVBF_SFMT_CLDQ, FRVBF_SFMT_CLDSBU, FRVBF_SFMT_CLDBFU, FRVBF_SFMT_CLDDU
, FRVBF_SFMT_CLDDFU, FRVBF_SFMT_CLDQU, FRVBF_SFMT_CSTB, FRVBF_SFMT_CSTBF
, FRVBF_SFMT_CSTD, FRVBF_SFMT_CSTDF, FRVBF_SFMT_CSTBU, FRVBF_SFMT_CSTBFU
, FRVBF_SFMT_CSTDU, FRVBF_SFMT_CSTDFU, FRVBF_SFMT_STBI, FRVBF_SFMT_STBFI
, FRVBF_SFMT_STDI, FRVBF_SFMT_STDFI, FRVBF_SFMT_SWAP, FRVBF_SFMT_SWAPI
, FRVBF_SFMT_CSWAP, FRVBF_SFMT_MOVGF, FRVBF_SFMT_MOVFG, FRVBF_SFMT_MOVGFD
, FRVBF_SFMT_MOVFGD, FRVBF_SFMT_MOVGFQ, FRVBF_SFMT_MOVFGQ, FRVBF_SFMT_CMOVGF
, FRVBF_SFMT_CMOVFG, FRVBF_SFMT_CMOVGFD, FRVBF_SFMT_CMOVFGD, FRVBF_SFMT_MOVGS
, FRVBF_SFMT_MOVSG, FRVBF_SFMT_BRA, FRVBF_SFMT_BNO, FRVBF_SFMT_BEQ
, FRVBF_SFMT_FBNE, FRVBF_SFMT_BCTRLR, FRVBF_SFMT_BRALR, FRVBF_SFMT_BNOLR
, FRVBF_SFMT_BEQLR, FRVBF_SFMT_FBEQLR, FRVBF_SFMT_BCRALR, FRVBF_SFMT_BCNOLR
, FRVBF_SFMT_BCEQLR, FRVBF_SFMT_FCBEQLR, FRVBF_SFMT_JMPL, FRVBF_SFMT_JMPIL
, FRVBF_SFMT_CALL, FRVBF_SFMT_RETT, FRVBF_SFMT_REI, FRVBF_SFMT_TRA
, FRVBF_SFMT_TEQ, FRVBF_SFMT_FTNE, FRVBF_SFMT_TIRA, FRVBF_SFMT_TIEQ
, FRVBF_SFMT_FTINE, FRVBF_SFMT_BREAK, FRVBF_SFMT_ANDCR, FRVBF_SFMT_NOTCR
, FRVBF_SFMT_CKRA, FRVBF_SFMT_CKEQ, FRVBF_SFMT_FCKRA, FRVBF_SFMT_FCKNE
, FRVBF_SFMT_CCKRA, FRVBF_SFMT_CCKEQ, FRVBF_SFMT_CFCKRA, FRVBF_SFMT_CFCKNE
, FRVBF_SFMT_CJMPL, FRVBF_SFMT_ICI, FRVBF_SFMT_ICEI, FRVBF_SFMT_ICPL
, FRVBF_SFMT_ICUL, FRVBF_SFMT_CLRGR, FRVBF_SFMT_CLRFR, FRVBF_SFMT_COMMITGR
, FRVBF_SFMT_COMMITFR, FRVBF_SFMT_FITOS, FRVBF_SFMT_FSTOI, FRVBF_SFMT_FITOD
, FRVBF_SFMT_FDTOI, FRVBF_SFMT_FDITOS, FRVBF_SFMT_FDSTOI, FRVBF_SFMT_CFITOS
, FRVBF_SFMT_CFSTOI, FRVBF_SFMT_NFITOS, FRVBF_SFMT_NFSTOI, FRVBF_SFMT_FMOVS
, FRVBF_SFMT_FMOVD, FRVBF_SFMT_FDMOVS, FRVBF_SFMT_CFMOVS, FRVBF_SFMT_NFSQRTS
, FRVBF_SFMT_FADDS, FRVBF_SFMT_FADDD, FRVBF_SFMT_CFADDS, FRVBF_SFMT_NFADDS
, FRVBF_SFMT_FCMPS, FRVBF_SFMT_FCMPD, FRVBF_SFMT_CFCMPS, FRVBF_SFMT_FDCMPS
, FRVBF_SFMT_FMADDS, FRVBF_SFMT_FMADDD, FRVBF_SFMT_FDMADDS, FRVBF_SFMT_CFMADDS
, FRVBF_SFMT_NFMADDS, FRVBF_SFMT_FMAS, FRVBF_SFMT_FDMAS, FRVBF_SFMT_CFMAS
, FRVBF_SFMT_NFDCMPS, FRVBF_SFMT_MHSETLOS, FRVBF_SFMT_MHSETHIS, FRVBF_SFMT_MHDSETS
, FRVBF_SFMT_MHSETLOH, FRVBF_SFMT_MHSETHIH, FRVBF_SFMT_MHDSETH, FRVBF_SFMT_MAND
, FRVBF_SFMT_CMAND, FRVBF_SFMT_MNOT, FRVBF_SFMT_CMNOT, FRVBF_SFMT_MROTLI
, FRVBF_SFMT_MWCUT, FRVBF_SFMT_MWCUTI, FRVBF_SFMT_MCUT, FRVBF_SFMT_MCUTI
, FRVBF_SFMT_MDCUTSSI, FRVBF_SFMT_MSLLHI, FRVBF_SFMT_MDROTLI, FRVBF_SFMT_MCPLHI
, FRVBF_SFMT_MCPLI, FRVBF_SFMT_MSATHS, FRVBF_SFMT_MQSATHS, FRVBF_SFMT_MCMPSH
, FRVBF_SFMT_MABSHS, FRVBF_SFMT_CMADDHSS, FRVBF_SFMT_CMQADDHSS, FRVBF_SFMT_MADDACCS
, FRVBF_SFMT_MDADDACCS, FRVBF_SFMT_MASACCS, FRVBF_SFMT_MDASACCS, FRVBF_SFMT_MMULHS
, FRVBF_SFMT_CMMULHS, FRVBF_SFMT_MQMULHS, FRVBF_SFMT_CMQMULHS, FRVBF_SFMT_MMACHS
, FRVBF_SFMT_MMACHU, FRVBF_SFMT_CMMACHS, FRVBF_SFMT_CMMACHU, FRVBF_SFMT_MQMACHS
, FRVBF_SFMT_MQMACHU, FRVBF_SFMT_CMQMACHS, FRVBF_SFMT_CMQMACHU, FRVBF_SFMT_MCPXRS
, FRVBF_SFMT_CMCPXRS, FRVBF_SFMT_MQCPXRS, FRVBF_SFMT_MEXPDHW, FRVBF_SFMT_CMEXPDHW
, FRVBF_SFMT_MEXPDHD, FRVBF_SFMT_CMEXPDHD, FRVBF_SFMT_MPACKH, FRVBF_SFMT_MDPACKH
, FRVBF_SFMT_MUNPACKH, FRVBF_SFMT_MDUNPACKH, FRVBF_SFMT_MBTOH, FRVBF_SFMT_CMBTOH
, FRVBF_SFMT_MHTOB, FRVBF_SFMT_CMHTOB, FRVBF_SFMT_MBTOHE, FRVBF_SFMT_CMBTOHE
, FRVBF_SFMT_MCLRACC_0, FRVBF_SFMT_MRDACC, FRVBF_SFMT_MRDACCG, FRVBF_SFMT_MWTACC
, FRVBF_SFMT_MWTACCG
, FRVBF_SFMT_SMUL, FRVBF_SFMT_SMU, FRVBF_SFMT_SMASS, FRVBF_SFMT_SCUTSS
, FRVBF_SFMT_CADD, FRVBF_SFMT_CNOT, FRVBF_SFMT_CSMUL, FRVBF_SFMT_CSDIV
, FRVBF_SFMT_ADDCC, FRVBF_SFMT_ANDCC, FRVBF_SFMT_SMULCC, FRVBF_SFMT_CADDCC
, FRVBF_SFMT_CSMULCC, FRVBF_SFMT_ADDX, FRVBF_SFMT_ADDI, FRVBF_SFMT_SDIVI
, FRVBF_SFMT_SMULI, FRVBF_SFMT_ADDICC, FRVBF_SFMT_ANDICC, FRVBF_SFMT_SMULICC
, FRVBF_SFMT_ADDXI, FRVBF_SFMT_CMPB, FRVBF_SFMT_SETLO, FRVBF_SFMT_SETHI
, FRVBF_SFMT_SETLOS, FRVBF_SFMT_LDSB, FRVBF_SFMT_LDBF, FRVBF_SFMT_LDC
, FRVBF_SFMT_NLDSB, FRVBF_SFMT_NLDBF, FRVBF_SFMT_LDD, FRVBF_SFMT_LDDF
, FRVBF_SFMT_LDDC, FRVBF_SFMT_NLDD, FRVBF_SFMT_NLDDF, FRVBF_SFMT_LDQ
, FRVBF_SFMT_LDQF, FRVBF_SFMT_LDQC, FRVBF_SFMT_NLDQ, FRVBF_SFMT_NLDQF
, FRVBF_SFMT_LDSBU, FRVBF_SFMT_NLDSBU, FRVBF_SFMT_LDBFU, FRVBF_SFMT_LDCU
, FRVBF_SFMT_NLDBFU, FRVBF_SFMT_LDDU, FRVBF_SFMT_NLDDU, FRVBF_SFMT_LDDFU
, FRVBF_SFMT_LDDCU, FRVBF_SFMT_NLDDFU, FRVBF_SFMT_LDQU, FRVBF_SFMT_NLDQU
, FRVBF_SFMT_LDQFU, FRVBF_SFMT_LDQCU, FRVBF_SFMT_NLDQFU, FRVBF_SFMT_LDSBI
, FRVBF_SFMT_LDBFI, FRVBF_SFMT_NLDSBI, FRVBF_SFMT_NLDBFI, FRVBF_SFMT_LDDI
, FRVBF_SFMT_LDDFI, FRVBF_SFMT_NLDDI, FRVBF_SFMT_NLDDFI, FRVBF_SFMT_LDQI
, FRVBF_SFMT_LDQFI, FRVBF_SFMT_NLDQFI, FRVBF_SFMT_STB, FRVBF_SFMT_STBF
, FRVBF_SFMT_STC, FRVBF_SFMT_RSTB, FRVBF_SFMT_RSTBF, FRVBF_SFMT_STD
, FRVBF_SFMT_STDF, FRVBF_SFMT_STDC, FRVBF_SFMT_RSTD, FRVBF_SFMT_RSTDF
, FRVBF_SFMT_STBU, FRVBF_SFMT_STBFU, FRVBF_SFMT_STCU, FRVBF_SFMT_STDU
, FRVBF_SFMT_STDFU, FRVBF_SFMT_STDCU, FRVBF_SFMT_STQU, FRVBF_SFMT_CLDSB
, FRVBF_SFMT_CLDBF, FRVBF_SFMT_CLDD, FRVBF_SFMT_CLDDF, FRVBF_SFMT_CLDQ
, FRVBF_SFMT_CLDSBU, FRVBF_SFMT_CLDBFU, FRVBF_SFMT_CLDDU, FRVBF_SFMT_CLDDFU
, FRVBF_SFMT_CLDQU, FRVBF_SFMT_CSTB, FRVBF_SFMT_CSTBF, FRVBF_SFMT_CSTD
, FRVBF_SFMT_CSTDF, FRVBF_SFMT_CSTBU, FRVBF_SFMT_CSTBFU, FRVBF_SFMT_CSTDU
, FRVBF_SFMT_CSTDFU, FRVBF_SFMT_STBI, FRVBF_SFMT_STBFI, FRVBF_SFMT_STDI
, FRVBF_SFMT_STDFI, FRVBF_SFMT_SWAP, FRVBF_SFMT_SWAPI, FRVBF_SFMT_CSWAP
, FRVBF_SFMT_MOVGF, FRVBF_SFMT_MOVFG, FRVBF_SFMT_MOVGFD, FRVBF_SFMT_MOVFGD
, FRVBF_SFMT_MOVGFQ, FRVBF_SFMT_MOVFGQ, FRVBF_SFMT_CMOVGF, FRVBF_SFMT_CMOVFG
, FRVBF_SFMT_CMOVGFD, FRVBF_SFMT_CMOVFGD, FRVBF_SFMT_MOVGS, FRVBF_SFMT_MOVSG
, FRVBF_SFMT_BRA, FRVBF_SFMT_BNO, FRVBF_SFMT_BEQ, FRVBF_SFMT_FBNE
, FRVBF_SFMT_BCTRLR, FRVBF_SFMT_BRALR, FRVBF_SFMT_BNOLR, FRVBF_SFMT_BEQLR
, FRVBF_SFMT_FBEQLR, FRVBF_SFMT_BCRALR, FRVBF_SFMT_BCNOLR, FRVBF_SFMT_BCEQLR
, FRVBF_SFMT_FCBEQLR, FRVBF_SFMT_JMPL, FRVBF_SFMT_JMPIL, FRVBF_SFMT_CALL
, FRVBF_SFMT_RETT, FRVBF_SFMT_REI, FRVBF_SFMT_TRA, FRVBF_SFMT_TEQ
, FRVBF_SFMT_FTNE, FRVBF_SFMT_TIRA, FRVBF_SFMT_TIEQ, FRVBF_SFMT_FTINE
, FRVBF_SFMT_BREAK, FRVBF_SFMT_ANDCR, FRVBF_SFMT_NOTCR, FRVBF_SFMT_CKRA
, FRVBF_SFMT_CKEQ, FRVBF_SFMT_FCKRA, FRVBF_SFMT_FCKNE, FRVBF_SFMT_CCKRA
, FRVBF_SFMT_CCKEQ, FRVBF_SFMT_CFCKRA, FRVBF_SFMT_CFCKNE, FRVBF_SFMT_CJMPL
, FRVBF_SFMT_ICI, FRVBF_SFMT_ICEI, FRVBF_SFMT_ICPL, FRVBF_SFMT_ICUL
, FRVBF_SFMT_CLRGR, FRVBF_SFMT_CLRFR, FRVBF_SFMT_COMMITGR, FRVBF_SFMT_COMMITFR
, FRVBF_SFMT_FITOS, FRVBF_SFMT_FSTOI, FRVBF_SFMT_FITOD, FRVBF_SFMT_FDTOI
, FRVBF_SFMT_FDITOS, FRVBF_SFMT_FDSTOI, FRVBF_SFMT_CFITOS, FRVBF_SFMT_CFSTOI
, FRVBF_SFMT_NFITOS, FRVBF_SFMT_NFSTOI, FRVBF_SFMT_FMOVS, FRVBF_SFMT_FMOVD
, FRVBF_SFMT_FDMOVS, FRVBF_SFMT_CFMOVS, FRVBF_SFMT_NFSQRTS, FRVBF_SFMT_FADDS
, FRVBF_SFMT_FADDD, FRVBF_SFMT_CFADDS, FRVBF_SFMT_NFADDS, FRVBF_SFMT_FCMPS
, FRVBF_SFMT_FCMPD, FRVBF_SFMT_CFCMPS, FRVBF_SFMT_FDCMPS, FRVBF_SFMT_FMADDS
, FRVBF_SFMT_FMADDD, FRVBF_SFMT_FDMADDS, FRVBF_SFMT_CFMADDS, FRVBF_SFMT_NFMADDS
, FRVBF_SFMT_FMAS, FRVBF_SFMT_FDMAS, FRVBF_SFMT_CFMAS, FRVBF_SFMT_NFDCMPS
, FRVBF_SFMT_MHSETLOS, FRVBF_SFMT_MHSETHIS, FRVBF_SFMT_MHDSETS, FRVBF_SFMT_MHSETLOH
, FRVBF_SFMT_MHSETHIH, FRVBF_SFMT_MHDSETH, FRVBF_SFMT_MAND, FRVBF_SFMT_CMAND
, FRVBF_SFMT_MNOT, FRVBF_SFMT_CMNOT, FRVBF_SFMT_MROTLI, FRVBF_SFMT_MWCUT
, FRVBF_SFMT_MWCUTI, FRVBF_SFMT_MCUT, FRVBF_SFMT_MCUTI, FRVBF_SFMT_MDCUTSSI
, FRVBF_SFMT_MSLLHI, FRVBF_SFMT_MDROTLI, FRVBF_SFMT_MCPLHI, FRVBF_SFMT_MCPLI
, FRVBF_SFMT_MSATHS, FRVBF_SFMT_MQSATHS, FRVBF_SFMT_MCMPSH, FRVBF_SFMT_MABSHS
, FRVBF_SFMT_CMADDHSS, FRVBF_SFMT_CMQADDHSS, FRVBF_SFMT_MADDACCS, FRVBF_SFMT_MDADDACCS
, FRVBF_SFMT_MASACCS, FRVBF_SFMT_MDASACCS, FRVBF_SFMT_MMULHS, FRVBF_SFMT_CMMULHS
, FRVBF_SFMT_MQMULHS, FRVBF_SFMT_CMQMULHS, FRVBF_SFMT_MMACHS, FRVBF_SFMT_MMACHU
, FRVBF_SFMT_CMMACHS, FRVBF_SFMT_CMMACHU, FRVBF_SFMT_MQMACHS, FRVBF_SFMT_MQMACHU
, FRVBF_SFMT_CMQMACHS, FRVBF_SFMT_CMQMACHU, FRVBF_SFMT_MCPXRS, FRVBF_SFMT_CMCPXRS
, FRVBF_SFMT_MQCPXRS, FRVBF_SFMT_MEXPDHW, FRVBF_SFMT_CMEXPDHW, FRVBF_SFMT_MEXPDHD
, FRVBF_SFMT_CMEXPDHD, FRVBF_SFMT_MPACKH, FRVBF_SFMT_MDPACKH, FRVBF_SFMT_MUNPACKH
, FRVBF_SFMT_MDUNPACKH, FRVBF_SFMT_MBTOH, FRVBF_SFMT_CMBTOH, FRVBF_SFMT_MHTOB
, FRVBF_SFMT_CMHTOB, FRVBF_SFMT_MBTOHE, FRVBF_SFMT_CMBTOHE, FRVBF_SFMT_MCLRACC_0
, FRVBF_SFMT_MRDACC, FRVBF_SFMT_MRDACCG, FRVBF_SFMT_MWTACC, FRVBF_SFMT_MWTACCG
} FRVBF_SFMT_TYPE;
/* Function unit handlers (user written). */
extern int frvbf_model_frv_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int frvbf_model_fr550_u_media_4_quad (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintieven*/, INT /*FRintjeven*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/);
extern int frvbf_model_fr550_u_media_4_add_sub_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
extern int frvbf_model_fr550_u_media_4_add_sub (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
extern int frvbf_model_fr550_u_media_4_acc_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
extern int frvbf_model_fr550_u_media_4_acc (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
extern int frvbf_model_fr550_u_media_4 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/);
extern int frvbf_model_fr550_u_media_set (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintk*/);
extern int frvbf_model_fr550_u_media_3_mclracc (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int frvbf_model_fr550_u_media_3_wtacc (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*ACC40Sk*/);
extern int frvbf_model_fr550_u_media_3_acc_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*FRintkeven*/);
extern int frvbf_model_fr550_u_media_3_acc (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintj*/, INT /*ACC40Si*/, INT /*FRintk*/);
extern int frvbf_model_fr550_u_media_3_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintk*/);
extern int frvbf_model_fr550_u_media_dual_expand (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintkeven*/);
extern int frvbf_model_fr550_u_media_quad (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintieven*/, INT /*FRintjeven*/, INT /*FRintkeven*/);
extern int frvbf_model_fr550_u_media (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FRintk*/);
extern int frvbf_model_fr550_u_float_convert (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRj*/, INT /*FRintj*/, INT /*FRdoublej*/, INT /*FRk*/, INT /*FRintk*/, INT /*FRdoublek*/);
extern int frvbf_model_fr550_u_commit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRk*/, INT /*FRk*/);
extern int frvbf_model_fr550_u_dcul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
extern int frvbf_model_fr550_u_icul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
extern int frvbf_model_fr550_u_dcpl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
extern int frvbf_model_fr550_u_icpl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
extern int frvbf_model_fr550_u_dcf (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
extern int frvbf_model_fr550_u_dci (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
extern int frvbf_model_fr550_u_ici (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
extern int frvbf_model_fr550_u_clrfr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRk*/);
extern int frvbf_model_fr550_u_clrgr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRk*/);
extern int frvbf_model_fr550_u_fr2fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRk*/);
extern int frvbf_model_fr550_u_swap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/);
extern int frvbf_model_fr550_u_fr_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*FRintk*/, INT /*FRdoublek*/);
extern int frvbf_model_fr550_u_fr_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*FRintk*/, INT /*FRdoublek*/);
extern int frvbf_model_fr550_u_gr_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*GRdoublek*/);
extern int frvbf_model_fr550_u_gr_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*GRdoublek*/);
extern int frvbf_model_fr550_u_set_hilo (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRkhi*/, INT /*GRklo*/);
extern int frvbf_model_fr550_u_gr2spr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRj*/, INT /*spr*/);
extern int frvbf_model_fr550_u_spr2gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*spr*/, INT /*GRj*/);
extern int frvbf_model_fr550_u_gr2fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRj*/, INT /*FRintk*/);
extern int frvbf_model_fr550_u_fr2gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintk*/, INT /*GRj*/);
extern int frvbf_model_fr550_u_float_dual_compare (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRj*/, INT /*FCCi_2*/);
extern int frvbf_model_fr550_u_float_compare (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRj*/, INT /*FRdoublei*/, INT /*FRdoublej*/, INT /*FCCi_2*/);
extern int frvbf_model_fr550_u_float_sqrt (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRj*/, INT /*FRdoublej*/, INT /*FRk*/, INT /*FRdoublek*/);
extern int frvbf_model_fr550_u_float_div (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRj*/, INT /*FRk*/);
extern int frvbf_model_fr550_u_float_dual_arith (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRj*/, INT /*FRdoublei*/, INT /*FRdoublej*/, INT /*FRk*/, INT /*FRdoublek*/);
extern int frvbf_model_fr550_u_float_arith (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRi*/, INT /*FRj*/, INT /*FRdoublei*/, INT /*FRdoublej*/, INT /*FRk*/, INT /*FRdoublek*/);
extern int frvbf_model_fr550_u_check (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ICCi_3*/, INT /*FCCi_3*/);
extern int frvbf_model_fr550_u_trap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*ICCi_2*/, INT /*FCCi_2*/);
extern int frvbf_model_fr550_u_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*ICCi_2*/, INT /*FCCi_2*/);
extern int frvbf_model_fr550_u_idiv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*ICCi_1*/);
extern int frvbf_model_fr550_u_imul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRdoublek*/, INT /*ICCi_1*/);
extern int frvbf_model_fr550_u_integer (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*ICCi_1*/);
extern int frvbf_model_fr550_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int frvbf_model_fr500_u_commit (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRk*/, INT /*FRk*/);
extern int frvbf_model_fr500_u_dcul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
extern int frvbf_model_fr500_u_icul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);

21
sim/frv/frv-sim.h
View File

@ -1,6 +1,6 @@
/* collection of junk waiting time to sort out
Copyright (C) 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
Contributed by Red Hat.
Contributed by Red Hat
This file is part of the GNU Simulators.
@ -104,8 +104,11 @@ extern void frvbf_switch_supervisor_user_context (SIM_CPU *);
extern QI frvbf_set_icc_for_shift_left (SIM_CPU *, SI, SI, QI);
extern QI frvbf_set_icc_for_shift_right (SIM_CPU *, SI, SI, QI);
/* Insn semantics. */
extern void frvbf_signed_integer_divide (SIM_CPU *, SI, SI, int, int);
extern void frvbf_unsigned_integer_divide (SIM_CPU *, USI, USI, int, int);
extern SI frvbf_shift_left_arith_saturate (SIM_CPU *, SI, SI);
extern SI frvbf_iacc_cut (SIM_CPU *, DI, SI);
extern void frvbf_clear_accumulators (SIM_CPU *, SI, int);
@ -149,6 +152,7 @@ struct _device { int foo; };
/* maintain the address of the start of the previous VLIW insn sequence. */
extern IADDR previous_vliw_pc;
extern CGEN_ATTR_VALUE_TYPE frv_current_fm_slot;
/* Hardware status. */
#define GET_HSR0() GET_H_SPR (H_SPR_HSR0)
@ -174,6 +178,9 @@ extern IADDR previous_vliw_pc;
#define GET_IHSR8() GET_H_SPR (H_SPR_IHSR8)
#define GET_IHSR8_NBC(ihsr8) ((ihsr8) & 1)
#define GET_IHSR8_ICDM(ihsr8) (((ihsr8) >> 1) & 1)
#define GET_IHSR8_ICWE(ihsr8) (((ihsr8) >> 8) & 7)
#define GET_IHSR8_DCWE(ihsr8) (((ihsr8) >> 12) & 7)
void frvbf_insn_cache_preload (SIM_CPU *, SI, USI, int);
void frvbf_data_cache_preload (SIM_CPU *, SI, USI, int);
@ -645,6 +652,9 @@ enum frv_msr_mtt
#define GET_MSR_EMCI(msr) ( \
((msr) >> 24) & 0x1 \
)
#define GET_MSR_MPEM(msr) ( \
((msr) >> 27) & 0x1 \
)
#define GET_MSR_SRDAV(msr) ( \
((msr) >> 28) & 0x1 \
)
@ -676,6 +686,15 @@ frv_queue_external_interrupt (SIM_CPU *, enum frv_interrupt_kind);
struct frv_interrupt_queue_element *
frv_queue_illegal_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
struct frv_interrupt_queue_element *
frv_queue_privileged_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
struct frv_interrupt_queue_element *
frv_queue_float_disabled_interrupt (SIM_CPU *);
struct frv_interrupt_queue_element *
frv_queue_media_disabled_interrupt (SIM_CPU *);
struct frv_interrupt_queue_element *
frv_queue_non_implemented_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);

71
sim/frv/frv.c
View File

@ -113,6 +113,7 @@ check_register_alignment (SIM_CPU *current_cpu, UINT reg, int align_mask)
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
case bfd_mach_fr550:
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
break;
case bfd_mach_frvtomcat:
@ -140,6 +141,7 @@ check_fr_register_alignment (SIM_CPU *current_cpu, UINT reg, int align_mask)
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
case bfd_mach_fr550:
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
break;
case bfd_mach_frvtomcat:
@ -431,6 +433,9 @@ frvbf_h_spr_set_handler (SIM_CPU *current_cpu, UINT spr, USI newval)
case H_SPR_SR3:
spr_sr_set_handler (current_cpu, spr, newval);
break;
case H_SPR_IHSR8:
frv_cache_reconfigure (current_cpu, CPU_INSN_CACHE (current_cpu));
break;
default:
CPU (h_spr[spr]) = newval;
break;
@ -926,9 +931,13 @@ frvbf_clear_accumulators (SIM_CPU *current_cpu, SI acc_ix, int A)
SIM_DESC sd = CPU_STATE (current_cpu);
int acc_num =
(STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr500) ? 8 :
(STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) ? 8 :
(STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400) ? 4 :
63;
FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu);
ps->mclracc_acc = acc_ix;
ps->mclracc_A = A;
if (A == 0 || acc_ix != 0) /* Clear 1 accumuator? */
{
/* This instruction is a nop if the referenced accumulator is not
@ -1027,6 +1036,65 @@ frvbf_media_cut_ss (SIM_CPU *current_cpu, DI acc, SI cut_point)
return frvbf_media_cut (current_cpu, acc, cut_point);
}
/* Compute the result of int accumulator cut (SCUTSS). */
SI
frvbf_iacc_cut (SIM_CPU *current_cpu, DI acc, SI cut_point)
{
/* The cut point is the lower 6 bits (signed) of what we are passed. */
cut_point = cut_point << 25 >> 25;
if (cut_point <= -32)
cut_point = -31; /* Special case for full shiftout. */
/* Negative cuts (cannot saturate). */
if (cut_point < 0)
return acc >> (32 + -cut_point);
/* Positive cuts will saturate if significant bits are shifted out. */
if (acc != ((acc << cut_point) >> cut_point))
if (acc >= 0)
return 0x7fffffff;
else
return 0x80000000;
/* No saturate, just cut. */
return ((acc << cut_point) >> 32);
}
/* Compute the result of shift-left-arithmetic-with-saturation (SLASS). */
SI
frvbf_shift_left_arith_saturate (SIM_CPU *current_cpu, SI arg1, SI arg2)
{
int neg_arg1;
/* FIXME: what to do with negative shift amt? */
if (arg2 <= 0)
return arg1;
if (arg1 == 0)
return 0;
/* Signed shift by 31 or greater saturates by definition. */
if (arg2 >= 31)
if (arg1 > 0)
return (SI) 0x7fffffff;
else
return (SI) 0x80000000;
/* OK, arg2 is between 1 and 31. */
neg_arg1 = (arg1 < 0);
do {
arg1 <<= 1;
/* Check for sign bit change (saturation). */
if (neg_arg1 && (arg1 >= 0))
return (SI) 0x80000000;
else if (!neg_arg1 && (arg1 < 0))
return (SI) 0x7fffffff;
} while (--arg2 > 0);
return arg1;
}
/* Simulate the media custom insns. */
void
frvbf_media_cop (SIM_CPU *current_cpu, int cop_num)
@ -1051,12 +1119,13 @@ do_media_average (SIM_CPU *current_cpu, HI arg1, HI arg2)
HI result = sum >> 1;
int rounding_value;
/* On fr400, check the rounding mode. On other machines rounding is always
/* On fr400 and fr550, check the rounding mode. On other machines rounding is always
toward negative infinity and the result is already correctly rounded. */
switch (STATE_ARCHITECTURE (sd)->mach)
{
/* Need to check rounding mode. */
case bfd_mach_fr400:
case bfd_mach_fr550:
/* Check whether rounding will be required. Rounding will be required
if the sum is an odd number. */
rounding_value = sum & 1;

111
sim/frv/interrupts.c
View File

@ -235,10 +235,14 @@ frv_queue_illegal_instruction_interrupt (
SIM_CPU *current_cpu, const CGEN_INSN *insn
)
{
/* The fr400 does not have the fp_exception. */
SIM_DESC sd = CPU_STATE (current_cpu);
if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr400)
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
case bfd_mach_fr550:
break;
default:
/* Some machines generate fp_exception for this case. */
if (frv_is_float_insn (insn) || frv_is_media_insn (insn))
{
struct frv_fp_exception_info fp_info = {
@ -246,21 +250,59 @@ frv_queue_illegal_instruction_interrupt (
};
return frv_queue_fp_exception_interrupt (current_cpu, & fp_info);
}
break;
}
return frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
}
struct frv_interrupt_queue_element *
frv_queue_privileged_instruction_interrupt (SIM_CPU *current_cpu, const CGEN_INSN *insn)
{
/* The fr550 has no privileged instruction interrupt. It uses
illegal_instruction. */
SIM_DESC sd = CPU_STATE (current_cpu);
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
return frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
return frv_queue_program_interrupt (current_cpu, FRV_PRIVILEGED_INSTRUCTION);
}
struct frv_interrupt_queue_element *
frv_queue_float_disabled_interrupt (SIM_CPU *current_cpu)
{
/* The fr550 has no fp_disabled interrupt. It uses illegal_instruction. */
SIM_DESC sd = CPU_STATE (current_cpu);
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
return frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
return frv_queue_program_interrupt (current_cpu, FRV_FP_DISABLED);
}
struct frv_interrupt_queue_element *
frv_queue_media_disabled_interrupt (SIM_CPU *current_cpu)
{
/* The fr550 has no mp_disabled interrupt. It uses illegal_instruction. */
SIM_DESC sd = CPU_STATE (current_cpu);
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
return frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
return frv_queue_program_interrupt (current_cpu, FRV_MP_DISABLED);
}
struct frv_interrupt_queue_element *
frv_queue_non_implemented_instruction_interrupt (
SIM_CPU *current_cpu, const CGEN_INSN *insn
)
{
/* The fr400 does not have the fp_exception, nor does it generate mp_exception
for this case. */
SIM_DESC sd = CPU_STATE (current_cpu);
if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr400)
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
case bfd_mach_fr550:
break;
default:
/* Some machines generate fp_exception or mp_exception for this case. */
if (frv_is_float_insn (insn))
{
struct frv_fp_exception_info fp_info = {
@ -268,14 +310,13 @@ frv_queue_non_implemented_instruction_interrupt (
};
return frv_queue_fp_exception_interrupt (current_cpu, & fp_info);
}
if (frv_is_media_insn (insn))
{
frv_set_mp_exception_registers (current_cpu, MTT_UNIMPLEMENTED_MPOP,
0);
return NULL; /* no interrupt queued at this time. */
}
break;
}
return frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
@ -364,19 +405,19 @@ frv_detect_insn_access_interrupts (SIM_CPU *current_cpu, SCACHE *sc)
if (frv_is_float_insn (insn)
|| (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR_ACCESS)
&& ! GET_H_PSR_EM ()))
frv_queue_program_interrupt (current_cpu, FRV_FP_DISABLED);
frv_queue_float_disabled_interrupt (current_cpu);
}
/* Make sure media support is enabled. */
else if (! GET_H_PSR_EM ())
{
/* Generate mp_disabled if it is a media insn. */
if (frv_is_media_insn (insn) || CGEN_INSN_NUM (insn) == FRV_INSN_MTRAP)
frv_queue_program_interrupt (current_cpu, FRV_MP_DISABLED);
frv_queue_media_disabled_interrupt (current_cpu);
}
/* Check for privileged insns. */
else if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_PRIVILEGED) &&
! GET_H_PSR_S ())
frv_queue_program_interrupt (current_cpu, FRV_PRIVILEGED_INSTRUCTION);
frv_queue_privileged_instruction_interrupt (current_cpu, insn);
#if 0 /* disable for now until we find out how FSR0.QNE gets reset. */
else
{
@ -552,6 +593,10 @@ esr_for_data_access_exception (
SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item
)
{
SIM_DESC sd = CPU_STATE (current_cpu);
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
return 8; /* Use ESR8, EPCR8. */
if (item->slot == UNIT_I0)
return 8; /* Use ESR8, EPCR8, EAR8, EDR8. */
@ -593,7 +638,7 @@ clear_exception_status_registers (SIM_CPU *current_cpu)
CLEAR_ESR_VALID (esr);
SET_ESR (i, esr);
}
for (i = 8; i <= 13; ++i)
for (i = 8; i <= 15; ++i)
{
SI esr = GET_ESR (i);
CLEAR_ESR_VALID (esr);
@ -617,10 +662,11 @@ frv_set_mp_exception_registers (
{
FRV_VLIW *vliw = CPU_VLIW (current_cpu);
int slot = vliw->next_slot - 1;
SIM_DESC sd = CPU_STATE (current_cpu);
/* If this insn is in the M2 slot, then set MSR1.OVF and MSR1.SIE,
otherwise set MSR0.OVF and MSR0.SIE. */
if ((*vliw->current_vliw)[slot] == UNIT_FM1)
if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550 && (*vliw->current_vliw)[slot] == UNIT_FM1)
{
SI msr = GET_MSR (1);
OR_MSR_SIE (msr, sie);
@ -633,9 +679,15 @@ frv_set_mp_exception_registers (
SET_MSR_OVF (msr0);
}
/* Generate the interrupt now if MSR0.MPEM is set on fr550 */
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550 && GET_MSR_MPEM (msr0))
frv_queue_program_interrupt (current_cpu, FRV_MP_EXCEPTION);
else
{
/* Regardless of the slot, set MSR0.AOVF. */
SET_MSR_AOVF (msr0);
}
}
SET_MSR (0, msr0);
}
@ -689,6 +741,18 @@ set_fp_exception_registers (
SI fsr0;
IADDR pc;
struct frv_fp_exception_info *fp_info;
SIM_DESC sd = CPU_STATE (current_cpu);
/* No FQ registers on fr550 */
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
{
/* Update the fsr. */
fp_info = & item->u.fp_info;
fsr0 = GET_FSR (0);
SET_FSR_FTT (fsr0, fp_info->ftt);
SET_FSR (0, fsr0);
return;
}
/* Select an FQ and update it with the exception information. */
fq_index = fq_for_exception (current_cpu, item);
@ -755,6 +819,8 @@ set_exception_status_registers (
SET_ESR_REC (esr, item->u.rec);
else if (interrupt->kind == FRV_INSTRUCTION_ACCESS_EXCEPTION)
SET_ESR_IAEC (esr, item->u.iaec);
/* For fr550, don't set epcr for precise interrupts. */
if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550)
set_epcr = 1;
}
else
@ -765,14 +831,17 @@ set_exception_status_registers (
set_isr_exception_fields (current_cpu, item);
/* fall thru to set reg_index. */
case FRV_COMMIT_EXCEPTION:
if (item->slot == UNIT_I0)
/* For fr550, always use ESR0. */
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
reg_index = 0;
else if (item->slot == UNIT_I0)
reg_index = 0;
else if (item->slot == UNIT_I1)
reg_index = 1;
set_epcr = 1;
break;
case FRV_DATA_STORE_ERROR:
reg_index = 14; /* Use ESR15, EPCR15. */
reg_index = 14; /* Use ESR14. */
break;
case FRV_DATA_ACCESS_ERROR:
reg_index = 15; /* Use ESR15, EPCR15. */
@ -787,15 +856,29 @@ set_exception_status_registers (
/* Get the appropriate ESR, EPCR, EAR and EDR.
EAR will be set. EDR will not be set if this is a store insn. */
set_ear = 1;
/* For fr550, never use EDRx. */
if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550)
if (item->u.data_written.length != 0)
set_edr = 1;
reg_index = esr_for_data_access_exception (current_cpu, item);
set_epcr = 1;
break;
case FRV_MP_EXCEPTION:
/* For fr550, use EPCR2 and ESR2. */
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
{
reg_index = 2;
set_epcr = 1;
}
break; /* MSR0-1, FQ0-9 are already set. */
case FRV_FP_EXCEPTION:
set_fp_exception_registers (current_cpu, item);
/* For fr550, use EPCR2 and ESR2. */
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
{
reg_index = 2;
set_epcr = 1;
}
break;
default:
{

317
sim/frv/memory.c
View File

@ -1,6 +1,6 @@
/* frv memory model.
Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
Contributed by Red Hat.
Copyright (C) 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
Contributed by Red Hat
This file is part of the GNU simulators.
@ -55,6 +55,17 @@ fr500_check_data_read_address (SIM_CPU *current_cpu, SI address, int align_mask)
return address;
}
static SI
fr550_check_data_read_address (SIM_CPU *current_cpu, SI address, int align_mask)
{
if ((USI)address >= 0xfe800000 && (USI)address <= 0xfefeffff
|| (align_mask > 0x3
&& ((USI)address >= 0xfeff0000 && (USI)address <= 0xfeffffff)))
frv_queue_data_access_error_interrupt (current_cpu, address);
return address;
}
static SI
check_data_read_address (SIM_CPU *current_cpu, SI address, int align_mask)
{
@ -71,6 +82,10 @@ check_data_read_address (SIM_CPU *current_cpu, SI address, int align_mask)
address = fr500_check_data_read_address (current_cpu, address,
align_mask);
break;
case bfd_mach_fr550:
address = fr550_check_data_read_address (current_cpu, address,
align_mask);
break;
default:
break;
}
@ -108,6 +123,25 @@ fr500_check_readwrite_address (SIM_CPU *current_cpu, SI address, int align_mask)
return address;
}
static SI
fr550_check_readwrite_address (SIM_CPU *current_cpu, SI address, int align_mask)
{
/* No alignment restrictions on fr550 */
if ((USI)address >= 0xfe000000 && (USI)address <= 0xfe3fffff
|| (USI)address >= 0xfe408000 && (USI)address <= 0xfe7fffff)
frv_queue_data_access_exception_interrupt (current_cpu);
else
{
USI hsr0 = GET_HSR0 ();
if (! GET_HSR0_RME (hsr0)
&& (USI)address >= 0xfe400000 && (USI)address <= 0xfe407fff)
frv_queue_data_access_exception_interrupt (current_cpu);
}
return address;
}
static SI
check_readwrite_address (SIM_CPU *current_cpu, SI address, int align_mask)
{
@ -124,6 +158,10 @@ check_readwrite_address (SIM_CPU *current_cpu, SI address, int align_mask)
address = fr500_check_readwrite_address (current_cpu, address,
align_mask);
break;
case bfd_mach_fr550:
address = fr550_check_readwrite_address (current_cpu, address,
align_mask);
break;
default:
break;
}
@ -174,6 +212,27 @@ fr500_check_insn_read_address (SIM_CPU *current_cpu, PCADDR address,
return address;
}
static PCADDR
fr550_check_insn_read_address (SIM_CPU *current_cpu, PCADDR address,
int align_mask)
{
address &= ~align_mask;
if ((USI)address >= 0xfe800000 && (USI)address <= 0xfeffffff)
frv_queue_instruction_access_error_interrupt (current_cpu);
else if ((USI)address >= 0xfe008000 && (USI)address <= 0xfe7fffff)
frv_queue_instruction_access_exception_interrupt (current_cpu);
else
{
USI hsr0 = GET_HSR0 ();
if (! GET_HSR0_RME (hsr0)
&& (USI)address >= 0xfe000000 && (USI)address <= 0xfe007fff)
frv_queue_instruction_access_exception_interrupt (current_cpu);
}
return address;
}
static PCADDR
check_insn_read_address (SIM_CPU *current_cpu, PCADDR address, int align_mask)
{
@ -190,6 +249,10 @@ check_insn_read_address (SIM_CPU *current_cpu, PCADDR address, int align_mask)
address = fr500_check_insn_read_address (current_cpu, address,
align_mask);
break;
case bfd_mach_fr550:
address = fr550_check_insn_read_address (current_cpu, address,
align_mask);
break;
default:
break;
}
@ -262,6 +325,16 @@ frvbf_read_mem_UQI (SIM_CPU *current_cpu, IADDR pc, SI address)
return GETMEMUQI (current_cpu, pc, address);
}
/* Read a HI which spans two cache lines */
static HI
read_mem_unaligned_HI (SIM_CPU *current_cpu, IADDR pc, SI address)
{
HI value = frvbf_read_mem_QI (current_cpu, pc, address);
value <<= 8;
value |= frvbf_read_mem_UQI (current_cpu, pc, address + 1);
return T2H_2 (value);
}
HI
frvbf_read_mem_HI (SIM_CPU *current_cpu, IADDR pc, SI address)
{
@ -288,6 +361,13 @@ frvbf_read_mem_HI (SIM_CPU *current_cpu, IADDR pc, SI address)
if (GET_HSR0_DCE (hsr0))
{
int cycles;
/* Handle access which crosses cache line boundary */
SIM_DESC sd = CPU_STATE (current_cpu);
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
{
if (DATA_CROSSES_CACHE_LINE (cache, address, 2))
return read_mem_unaligned_HI (current_cpu, pc, address);
}
cycles = frv_cache_read (cache, 0, address);
if (cycles != 0)
return CACHE_RETURN_DATA (cache, 0, address, HI, 2);
@ -322,6 +402,13 @@ frvbf_read_mem_UHI (SIM_CPU *current_cpu, IADDR pc, SI address)
if (GET_HSR0_DCE (hsr0))
{
int cycles;
/* Handle access which crosses cache line boundary */
SIM_DESC sd = CPU_STATE (current_cpu);
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
{
if (DATA_CROSSES_CACHE_LINE (cache, address, 2))
return read_mem_unaligned_HI (current_cpu, pc, address);
}
cycles = frv_cache_read (cache, 0, address);
if (cycles != 0)
return CACHE_RETURN_DATA (cache, 0, address, UHI, 2);
@ -330,6 +417,44 @@ frvbf_read_mem_UHI (SIM_CPU *current_cpu, IADDR pc, SI address)
return GETMEMUHI (current_cpu, pc, address);
}
/* Read a SI which spans two cache lines */
static SI
read_mem_unaligned_SI (SIM_CPU *current_cpu, IADDR pc, SI address)
{
FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
unsigned hi_len = cache->line_size - (address & (cache->line_size - 1));
char valarray[4];
SI SIvalue;
HI HIvalue;
switch (hi_len)
{
case 1:
valarray[0] = frvbf_read_mem_QI (current_cpu, pc, address);
SIvalue = frvbf_read_mem_SI (current_cpu, pc, address + 1);
SIvalue = H2T_4 (SIvalue);
memcpy (valarray + 1, (char*)&SIvalue, 3);
break;
case 2:
HIvalue = frvbf_read_mem_HI (current_cpu, pc, address);
HIvalue = H2T_2 (HIvalue);
memcpy (valarray, (char*)&HIvalue, 2);
HIvalue = frvbf_read_mem_HI (current_cpu, pc, address + 2);
HIvalue = H2T_2 (HIvalue);
memcpy (valarray + 2, (char*)&HIvalue, 2);
break;
case 3:
SIvalue = frvbf_read_mem_SI (current_cpu, pc, address - 1);
SIvalue = H2T_4 (SIvalue);
memcpy (valarray, (char*)&SIvalue, 3);
valarray[3] = frvbf_read_mem_QI (current_cpu, pc, address + 3);
break;
default:
abort (); /* can't happen */
}
return T2H_4 (*(SI*)valarray);
}
SI
frvbf_read_mem_SI (SIM_CPU *current_cpu, IADDR pc, SI address)
{
@ -355,6 +480,13 @@ frvbf_read_mem_SI (SIM_CPU *current_cpu, IADDR pc, SI address)
if (GET_HSR0_DCE (hsr0))
{
int cycles;
/* Handle access which crosses cache line boundary */
SIM_DESC sd = CPU_STATE (current_cpu);
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
{
if (DATA_CROSSES_CACHE_LINE (cache, address, 4))
return read_mem_unaligned_SI (current_cpu, pc, address);
}
cycles = frv_cache_read (cache, 0, address);
if (cycles != 0)
return CACHE_RETURN_DATA (cache, 0, address, SI, 4);
@ -369,6 +501,79 @@ frvbf_read_mem_WI (SIM_CPU *current_cpu, IADDR pc, SI address)
return frvbf_read_mem_SI (current_cpu, pc, address);
}
/* Read a SI which spans two cache lines */
static DI
read_mem_unaligned_DI (SIM_CPU *current_cpu, IADDR pc, SI address)
{
FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
unsigned hi_len = cache->line_size - (address & (cache->line_size - 1));
DI value, value1;
switch (hi_len)
{
case 1:
value = frvbf_read_mem_QI (current_cpu, pc, address);
value <<= 56;
value1 = frvbf_read_mem_DI (current_cpu, pc, address + 1);
value1 = H2T_8 (value1);
value |= value1 & ((DI)0x00ffffff << 32);
value |= value1 & 0xffffffffu;
break;
case 2:
value = frvbf_read_mem_HI (current_cpu, pc, address);
value = H2T_2 (value);
value <<= 48;
value1 = frvbf_read_mem_DI (current_cpu, pc, address + 2);
value1 = H2T_8 (value1);
value |= value1 & ((DI)0x0000ffff << 32);
value |= value1 & 0xffffffffu;
break;
case 3:
value = frvbf_read_mem_SI (current_cpu, pc, address - 1);
value = H2T_4 (value);
value <<= 40;
value1 = frvbf_read_mem_DI (current_cpu, pc, address + 3);
value1 = H2T_8 (value1);
value |= value1 & ((DI)0x000000ff << 32);
value |= value1 & 0xffffffffu;
break;
case 4:
value = frvbf_read_mem_SI (current_cpu, pc, address);
value = H2T_4 (value);
value <<= 32;
value1 = frvbf_read_mem_SI (current_cpu, pc, address + 4);
value1 = H2T_4 (value1);
value |= value1 & 0xffffffffu;
break;
case 5:
value = frvbf_read_mem_DI (current_cpu, pc, address - 3);
value = H2T_8 (value);
value <<= 24;
value1 = frvbf_read_mem_SI (current_cpu, pc, address + 5);
value1 = H2T_4 (value1);
value |= value1 & 0x00ffffff;
break;
case 6:
value = frvbf_read_mem_DI (current_cpu, pc, address - 2);
value = H2T_8 (value);
value <<= 16;
value1 = frvbf_read_mem_HI (current_cpu, pc, address + 6);
value1 = H2T_2 (value1);
value |= value1 & 0x0000ffff;
break;
case 7:
value = frvbf_read_mem_DI (current_cpu, pc, address - 1);
value = H2T_8 (value);
value <<= 8;
value1 = frvbf_read_mem_QI (current_cpu, pc, address + 7);
value |= value1 & 0x000000ff;
break;
default:
abort (); /* can't happen */
}
return T2H_8 (value);
}
DI
frvbf_read_mem_DI (SIM_CPU *current_cpu, IADDR pc, SI address)
{
@ -394,6 +599,13 @@ frvbf_read_mem_DI (SIM_CPU *current_cpu, IADDR pc, SI address)
if (GET_HSR0_DCE (hsr0))
{
int cycles;
/* Handle access which crosses cache line boundary */
SIM_DESC sd = CPU_STATE (current_cpu);
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
{
if (DATA_CROSSES_CACHE_LINE (cache, address, 8))
return read_mem_unaligned_DI (current_cpu, pc, address);
}
cycles = frv_cache_read (cache, 0, address);
if (cycles != 0)
return CACHE_RETURN_DATA (cache, 0, address, DI, 8);
@ -427,6 +639,13 @@ frvbf_read_mem_DF (SIM_CPU *current_cpu, IADDR pc, SI address)
if (GET_HSR0_DCE (hsr0))
{
int cycles;
/* Handle access which crosses cache line boundary */
SIM_DESC sd = CPU_STATE (current_cpu);
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
{
if (DATA_CROSSES_CACHE_LINE (cache, address, 8))
return read_mem_unaligned_DI (current_cpu, pc, address);
}
cycles = frv_cache_read (cache, 0, address);
if (cycles != 0)
return CACHE_RETURN_DATA (cache, 0, address, DF, 8);
@ -498,6 +717,17 @@ fr500_check_write_address (SIM_CPU *current_cpu, SI address, int align_mask)
return address;
}
static SI
fr550_check_write_address (SIM_CPU *current_cpu, SI address, int align_mask)
{
if ((USI)address >= 0xfe800000 && (USI)address <= 0xfefeffff
|| (align_mask > 0x3
&& ((USI)address >= 0xfeff0000 && (USI)address <= 0xfeffffff)))
frv_queue_program_interrupt (current_cpu, FRV_DATA_STORE_ERROR);
return address;
}
static SI
check_write_address (SIM_CPU *current_cpu, SI address, int align_mask)
{
@ -512,6 +742,9 @@ check_write_address (SIM_CPU *current_cpu, SI address, int align_mask)
case bfd_mach_frv:
address = fr500_check_write_address (current_cpu, address, align_mask);
break;
case bfd_mach_fr550:
address = fr550_check_write_address (current_cpu, address, align_mask);
break;
default:
break;
}
@ -618,6 +851,16 @@ frvbf_mem_set_QI (SIM_CPU *current_cpu, IADDR pc, SI address, QI value)
frv_cache_write (cache, address, (char *)&value, sizeof (value));
}
/* Write a HI which spans two cache lines */
static void
mem_set_unaligned_HI (SIM_CPU *current_cpu, IADDR pc, SI address, HI value)
{
FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
/* value is already in target byte order */
frv_cache_write (cache, address, (char *)&value, 1);
frv_cache_write (cache, address + 1, ((char *)&value + 1), 1);
}
void
frvbf_mem_set_HI (SIM_CPU *current_cpu, IADDR pc, SI address, HI value)
{
@ -638,8 +881,31 @@ frvbf_mem_set_HI (SIM_CPU *current_cpu, IADDR pc, SI address, HI value)
(char *)&value, sizeof (value));
}
else
{
/* Handle access which crosses cache line boundary */
SIM_DESC sd = CPU_STATE (current_cpu);
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
{
if (DATA_CROSSES_CACHE_LINE (cache, address, 2))
{
mem_set_unaligned_HI (current_cpu, pc, address, value);
return;
}
}
frv_cache_write (cache, address, (char *)&value, sizeof (value));
}
}
/* Write a SI which spans two cache lines */
static void
mem_set_unaligned_SI (SIM_CPU *current_cpu, IADDR pc, SI address, SI value)
{
FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
unsigned hi_len = cache->line_size - (address & (cache->line_size - 1));
/* value is already in target byte order */
frv_cache_write (cache, address, (char *)&value, hi_len);
frv_cache_write (cache, address + hi_len, (char *)&value + hi_len, 4 - hi_len);
}
void
frvbf_mem_set_SI (SIM_CPU *current_cpu, IADDR pc, SI address, SI value)
@ -661,8 +927,31 @@ frvbf_mem_set_SI (SIM_CPU *current_cpu, IADDR pc, SI address, SI value)
(char *)&value, sizeof (value));
}
else
{
/* Handle access which crosses cache line boundary */
SIM_DESC sd = CPU_STATE (current_cpu);
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
{
if (DATA_CROSSES_CACHE_LINE (cache, address, 4))
{
mem_set_unaligned_SI (current_cpu, pc, address, value);
return;
}
}
frv_cache_write (cache, address, (char *)&value, sizeof (value));
}
}
/* Write a DI which spans two cache lines */
static void
mem_set_unaligned_DI (SIM_CPU *current_cpu, IADDR pc, SI address, DI value)
{
FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
unsigned hi_len = cache->line_size - (address & (cache->line_size - 1));
/* value is already in target byte order */
frv_cache_write (cache, address, (char *)&value, hi_len);
frv_cache_write (cache, address + hi_len, (char *)&value + hi_len, 8 - hi_len);
}
void
frvbf_mem_set_DI (SIM_CPU *current_cpu, IADDR pc, SI address, DI value)
@ -684,8 +973,20 @@ frvbf_mem_set_DI (SIM_CPU *current_cpu, IADDR pc, SI address, DI value)
(char *)&value, sizeof (value));
}
else
{
/* Handle access which crosses cache line boundary */
SIM_DESC sd = CPU_STATE (current_cpu);
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
{
if (DATA_CROSSES_CACHE_LINE (cache, address, 8))
{
mem_set_unaligned_DI (current_cpu, pc, address, value);
return;
}
}
frv_cache_write (cache, address, (char *)&value, sizeof (value));
}
}
void
frvbf_mem_set_DF (SIM_CPU *current_cpu, IADDR pc, SI address, DF value)
@ -707,8 +1008,20 @@ frvbf_mem_set_DF (SIM_CPU *current_cpu, IADDR pc, SI address, DF value)
(char *)&value, sizeof (value));
}
else
{
/* Handle access which crosses cache line boundary */
SIM_DESC sd = CPU_STATE (current_cpu);
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550)
{
if (DATA_CROSSES_CACHE_LINE (cache, address, 8))
{
mem_set_unaligned_DI (current_cpu, pc, address, value);
return;
}
}
frv_cache_write (cache, address, (char *)&value, sizeof (value));
}
}
void
frvbf_mem_set_XI (SIM_CPU *current_cpu, IADDR pc, SI address, SI *value)

8
sim/frv/mloop.in
View File

@ -1,5 +1,5 @@
# Simulator main loop for frv. -*- C -*-
# Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
# Copyright (C) 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
# Contributed by Red Hat.
#
# This file is part of the GNU Simulators.
@ -395,6 +395,7 @@ static void
break;
case bfd_mach_frvtomcat:
case bfd_mach_fr500:
case bfd_mach_fr550:
case bfd_mach_frv:
simulate_dual_insn_prefetch (current_cpu, vpc, 16);
break;
@ -454,6 +455,7 @@ cat <<EOF
int first_insn_p = 1;
int last_insn_p = 0;
int ninsns;
CGEN_ATTR_VALUE_TYPE slot;
/* If the timer is enabled, then enable model profiling. This is because
the timer needs accurate cycles counts to work properly. */
@ -465,6 +467,7 @@ cat <<EOF
vliw = CPU_VLIW (current_cpu);
frv_vliw_reset (vliw, STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach,
CPU_ELF_FLAGS (current_cpu));
frv_current_fm_slot = UNIT_NIL;
for (ninsns = 0; ! last_insn_p && ninsns < FRV_VLIW_SIZE; ++ninsns)
{
@ -484,6 +487,9 @@ cat <<EOF
if (! error)
frv_vliw_setup_insn (current_cpu, insn);
frv_detect_insn_access_interrupts (current_cpu, sc);
slot = (*vliw->current_vliw)[vliw->next_slot - 1];
if (slot >= UNIT_FM0 && slot <= UNIT_FM3)
frv_current_fm_slot = slot;
vpc = execute (current_cpu, sc, FAST_P);

18480
sim/frv/model.c
View File

File diff suppressed because it is too large Load Diff

2
sim/frv/pipeline.c
View File

@ -1,5 +1,5 @@
/* frv vliw model.
Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright (C) 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
Contributed by Red Hat.
This file is part of the GNU simulators.

2664
sim/frv/profile-fr550.c Normal file
View File

File diff suppressed because it is too large Load Diff

27
sim/frv/profile-fr550.h Normal file
View File

@ -0,0 +1,27 @@
/* Profiling definitions for the fr550 model of the FRV simulator
Copyright (C) 2003 Free Software Foundation, Inc.
Contributed by Red Hat.
This file is part of the GNU Simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#ifndef PROFILE_FR550_H
#define PROFILE_FR550_H
void fr550_model_insn_before (SIM_CPU *, int);
void fr550_model_insn_after (SIM_CPU *, int, int);
#endif /* PROFILE_FR550_H */

122
sim/frv/profile.c
View File

@ -31,6 +31,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#include "profile.h"
#include "profile-fr400.h"
#include "profile-fr500.h"
#include "profile-fr550.h"
static void
reset_gr_flags (SIM_CPU *cpu, INT gr)
@ -677,6 +678,8 @@ update_latencies (SIM_CPU *cpu, int cycles)
int *fdiv;
int *fsqrt;
int *idiv;
int *flt;
int *media;
int *ccr;
int *gr = ps->gr_busy;
int *fr = ps->fr_busy;
@ -758,6 +761,16 @@ update_latencies (SIM_CPU *cpu, int cycles)
++fdiv;
++fsqrt;
}
/* Float and media units can occur in 4 slots on some machines. */
flt = ps->float_busy;
media = ps->media_busy;
for (i = 0; i < 4; ++i)
{
*flt = (*flt <= cycles) ? 0 : (*flt - cycles);
*media = (*media <= cycles) ? 0 : (*media - cycles);
++flt;
++media;
}
}
/* Print information about the wait for the given number of cycles. */
@ -918,6 +931,9 @@ frvbf_model_insn_before (SIM_CPU *cpu, int first_p)
case bfd_mach_fr500:
fr500_model_insn_before (cpu, first_p);
break;
case bfd_mach_fr550:
fr550_model_insn_before (cpu, first_p);
break;
default:
break;
}
@ -981,6 +997,9 @@ frvbf_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
case bfd_mach_fr500:
fr500_model_insn_after (cpu, last_p, cycles);
break;
case bfd_mach_fr550:
fr550_model_insn_after (cpu, last_p, cycles);
break;
default:
break;
}
@ -1242,7 +1261,6 @@ decrease_ACC_busy (SIM_CPU *cpu, INT out_ACC, int cycles)
}
}
/* start-sanitize-frv */
void
increase_ACC_busy (SIM_CPU *cpu, INT out_ACC, int cycles)
{
@ -1261,7 +1279,6 @@ enforce_full_acc_latency (SIM_CPU *cpu, INT in_ACC)
ps->acc_busy_adjust [in_ACC] = -1;
}
/* end-sanitize-frv */
void
decrease_FR_busy (SIM_CPU *cpu, INT out_FR, int cycles)
{
@ -1360,6 +1377,27 @@ update_fsqrt_resource_latency (SIM_CPU *cpu, INT in_resource, int cycles)
r[in_resource] = cycles;
}
/* Set the latency of the given resource to the given number of cycles. */
void
update_float_resource_latency (SIM_CPU *cpu, INT in_resource, int cycles)
{
/* operate directly on the busy cycles since each resource can only
be used once in a VLIW insn. */
FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
int *r = ps->float_busy;
r[in_resource] = cycles;
}
void
update_media_resource_latency (SIM_CPU *cpu, INT in_resource, int cycles)
{
/* operate directly on the busy cycles since each resource can only
be used once in a VLIW insn. */
FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
int *r = ps->media_busy;
r[in_resource] = cycles;
}
/* Set the branch penalty to the given number of cycles. */
void
update_branch_penalty (SIM_CPU *cpu, int cycles)
@ -1572,6 +1610,46 @@ vliw_wait_for_fsqrt_resource (SIM_CPU *cpu, INT in_resource)
}
}
/* Check the availability of the given float unit resource and update
the number of cycles the current VLIW insn must wait until it is available.
*/
void
vliw_wait_for_float_resource (SIM_CPU *cpu, INT in_resource)
{
FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
int *r = ps->float_busy;
/* If the latency of the resource is greater than the current wait
then update the current wait. */
if (r[in_resource] > ps->vliw_wait)
{
if (TRACE_INSN_P (cpu))
{
sprintf (hazard_name, "Resource hazard for floating point unit in slot F%d:", in_resource);
}
ps->vliw_wait = r[in_resource];
}
}
/* Check the availability of the given media unit resource and update
the number of cycles the current VLIW insn must wait until it is available.
*/
void
vliw_wait_for_media_resource (SIM_CPU *cpu, INT in_resource)
{
FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
int *r = ps->media_busy;
/* If the latency of the resource is greater than the current wait
then update the current wait. */
if (r[in_resource] > ps->vliw_wait)
{
if (TRACE_INSN_P (cpu))
{
sprintf (hazard_name, "Resource hazard for media unit in slot M%d:", in_resource);
}
ps->vliw_wait = r[in_resource];
}
}
/* Run the caches until all requests for the given register(s) are satisfied. */
void
load_wait_for_GR (SIM_CPU *cpu, INT in_GR)
@ -1824,6 +1902,42 @@ post_wait_for_fsqrt (SIM_CPU *cpu, INT slot)
}
}
int
post_wait_for_float (SIM_CPU *cpu, INT slot)
{
FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
int *flt = ps->float_busy;
/* Multiple floating point square roots in the same slot need only wait 1
extra cycle. */
if (flt[slot] > ps->post_wait)
{
ps->post_wait = flt[slot];
if (TRACE_INSN_P (cpu))
{
sprintf (hazard_name, "Resource hazard for floating point unit in slot F%d:", slot);
}
}
}
int
post_wait_for_media (SIM_CPU *cpu, INT slot)
{
FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
int *media = ps->media_busy;
/* Multiple floating point square roots in the same slot need only wait 1
extra cycle. */
if (media[slot] > ps->post_wait)
{
ps->post_wait = media[slot];
if (TRACE_INSN_P (cpu))
{
sprintf (hazard_name, "Resource hazard for media unit in slot M%d:", slot);
}
}
}
/* Print cpu-specific profile information. */
#define COMMAS(n) sim_add_commas (comma_buf, sizeof (comma_buf), (n))
@ -1863,8 +1977,8 @@ static char *
slot_names[] =
{
"none",
"I0", "I1", "I01", "IALL",
"FM0", "FM1", "FM01", "FMALL", "FMLOW",
"I0", "I1", "I01", "I2", "I3", "IALL",
"FM0", "FM1", "FM01", "FM2", "FM3", "FMALL", "FMLOW",
"B0", "B1", "B01",
"C"
};

12
sim/frv/profile.h
View File

@ -45,6 +45,8 @@ typedef struct
int idiv_busy[2]; /* Cycles until integer division unit is available. */
int fdiv_busy[2]; /* Cycles until float division unit is available. */
int fsqrt_busy[2]; /* Cycles until square root unit is available. */
int float_busy[4]; /* Cycles until floating point unit is available. */
int media_busy[4]; /* Cycles until media unit is available. */
int branch_penalty; /* Cycles until branch is complete. */
int gr_latency[64]; /* Cycles until target GR is available. */
@ -72,6 +74,8 @@ typedef struct
int branch_hint; /* hint field from branch insn. */
USI branch_address; /* Address of predicted branch. */
USI insn_fetch_address;/* Address of sequential insns fetched. */
int mclracc_acc; /* ACC number of register cleared by mclracc. */
int mclracc_A; /* A field of mclracc. */
/* We need to know when the first branch of a vliw insn is taken, so that
we don't consider the remaining branches in the vliw insn. */
@ -117,12 +121,15 @@ void decrease_ACC_busy (SIM_CPU *, INT, int);
void decrease_FR_busy (SIM_CPU *, INT, int);
void decrease_GR_busy (SIM_CPU *, INT, int);
void increase_FR_busy (SIM_CPU *, INT, int);
void increase_ACC_busy (SIM_CPU *, INT, int);
void update_ACC_latency (SIM_CPU *, INT, int);
void update_CCR_latency (SIM_CPU *, INT, int);
void update_SPR_latency (SIM_CPU *, INT, int);
void update_idiv_resource_latency (SIM_CPU *, INT, int);
void update_fdiv_resource_latency (SIM_CPU *, INT, int);
void update_fsqrt_resource_latency (SIM_CPU *, INT, int);
void update_float_resource_latency (SIM_CPU *, INT, int);
void update_media_resource_latency (SIM_CPU *, INT, int);
void update_branch_penalty (SIM_CPU *, int);
void update_ACC_ptime (SIM_CPU *, INT, int);
void update_SPR_ptime (SIM_CPU *, INT, int);
@ -136,11 +143,14 @@ void vliw_wait_for_SPR (SIM_CPU *, INT);
void vliw_wait_for_idiv_resource (SIM_CPU *, INT);
void vliw_wait_for_fdiv_resource (SIM_CPU *, INT);
void vliw_wait_for_fsqrt_resource (SIM_CPU *, INT);
void vliw_wait_for_float_resource (SIM_CPU *, INT);
void vliw_wait_for_media_resource (SIM_CPU *, INT);
void load_wait_for_GR (SIM_CPU *, INT);
void load_wait_for_FR (SIM_CPU *, INT);
void load_wait_for_GRdouble (SIM_CPU *, INT);
void load_wait_for_FRdouble (SIM_CPU *, INT);
void enforce_full_fr_latency (SIM_CPU *, INT);
void enforce_full_acc_latency (SIM_CPU *, INT);
int post_wait_for_FR (SIM_CPU *, INT);
int post_wait_for_FRdouble (SIM_CPU *, INT);
int post_wait_for_ACC (SIM_CPU *, INT);
@ -148,6 +158,8 @@ int post_wait_for_CCR (SIM_CPU *, INT);
int post_wait_for_SPR (SIM_CPU *, INT);
int post_wait_for_fdiv (SIM_CPU *, INT);
int post_wait_for_fsqrt (SIM_CPU *, INT);
int post_wait_for_float (SIM_CPU *, INT);
int post_wait_for_media (SIM_CPU *, INT);
void trace_vliw_wait_cycles (SIM_CPU *);
void handle_resource_wait (SIM_CPU *);

1212
sim/frv/registers.c
View File

File diff suppressed because it is too large Load Diff

335
sim/frv/sem.c
View File

File diff suppressed because it is too large Load Diff

88
sim/frv/traps.c
View File

@ -1,5 +1,5 @@
/* frv trap support
Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
Copyright (C) 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
Contributed by Red Hat.
This file is part of the GNU simulators.
@ -30,6 +30,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#include "bfd.h"
#include "libiberty.h"
CGEN_ATTR_VALUE_TYPE frv_current_fm_slot;
/* The semantic code invokes this for invalid (unrecognized) instructions. */
SEM_PC
@ -276,9 +278,11 @@ frv_itrap (SIM_CPU *current_cpu, PCADDR pc, USI base, SI offset)
void
frv_mtrap (SIM_CPU *current_cpu)
{
SIM_DESC sd = CPU_STATE (current_cpu);
/* Check the status of media exceptions in MSR0. */
SI msr = GET_MSR (0);
if (GET_MSR_AOVF (msr) || GET_MSR_MTT (msr))
if (GET_MSR_AOVF (msr) || GET_MSR_MTT (msr) && STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550)
frv_queue_program_interrupt (current_cpu, FRV_MP_EXCEPTION);
}
@ -584,11 +588,17 @@ frvbf_media_cr_not_aligned (SIM_CPU *current_cpu)
{
SIM_DESC sd = CPU_STATE (current_cpu);
/* On the fr400 this generates an illegal_instruction interrupt. */
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
/* On some machines this generates an illegal_instruction interrupt. */
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
case bfd_mach_fr550:
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
else
break;
default:
frv_set_mp_exception_registers (current_cpu, MTT_CR_NOT_ALIGNED, 0);
break;
}
}
/* Record state for media exception: media_acc_not_aligned. */
@ -597,11 +607,17 @@ frvbf_media_acc_not_aligned (SIM_CPU *current_cpu)
{
SIM_DESC sd = CPU_STATE (current_cpu);
/* On the fr400 this generates an illegal_instruction interrupt. */
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
/* On some machines this generates an illegal_instruction interrupt. */
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
case bfd_mach_fr550:
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
else
break;
default:
frv_set_mp_exception_registers (current_cpu, MTT_ACC_NOT_ALIGNED, 0);
break;
}
}
/* Record state for media exception: media_register_not_aligned. */
@ -610,11 +626,17 @@ frvbf_media_register_not_aligned (SIM_CPU *current_cpu)
{
SIM_DESC sd = CPU_STATE (current_cpu);
/* On the fr400 this generates an illegal_instruction interrupt. */
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
/* On some machines this generates an illegal_instruction interrupt. */
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
case bfd_mach_fr550:
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
else
break;
default:
frv_set_mp_exception_registers (current_cpu, MTT_INVALID_FR, 0);
break;
}
}
/* Record state for media exception: media_overflow. */
@ -725,6 +747,50 @@ frvbf_check_recovering_store (
} /* loop over active neear registers. */
}
SI
frvbf_check_acc_range (SIM_CPU *current_cpu, SI regno)
{
/* Only applicable to fr550 */
SIM_DESC sd = CPU_STATE (current_cpu);
if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550)
return;
/* On the fr550, media insns in slots 0 and 2 can only access
accumulators acc0-acc3. Insns in slots 1 and 3 can only access
accumulators acc4-acc7 */
switch (frv_current_fm_slot)
{
case UNIT_FM0:
case UNIT_FM2:
if (regno <= 3)
return 1; /* all is ok */
break;
case UNIT_FM1:
case UNIT_FM3:
if (regno >= 4)
return 1; /* all is ok */
break;
}
/* The specified accumulator is out of range. Queue an illegal_instruction
interrupt. */
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
return 0;
}
void
frvbf_check_swap_address (SIM_CPU *current_cpu, SI address)
{
/* Only applicable to fr550 */
SIM_DESC sd = CPU_STATE (current_cpu);
if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr550)
return;
/* Adress must be aligned on a word boundary. */
if (address & 0x3)
frv_queue_data_access_exception_interrupt (current_cpu);
}
static void
clear_nesr_neear (SIM_CPU *current_cpu, SI target_index, BI is_float)
{