x86: fold RegEip/RegRip and RegEiz/RegRiz
This allows to simplify the code in a number of places.
This commit is contained in:
Jan Beulich
Jan Beulich
parent
b01474366f
commit
e968fc9b63
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@ -1,3 +1,14 @@
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2018-08-06 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (build_modrm_byte): Use RegIP and RegIZ.
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(output_disp): Use RegIP.
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(i386_addressing_mode): Drop uses of RegEip and RegEiz.
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(i386_index_check): Replace uses of RegEip/RegEiz.
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(parse_real_register): Use RegIZ.
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* config/tc-i386-intel.c (i386_intel_simplify_register): Use
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RegIZ.
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* testsuite/gas/i386/x86-64-mpx-inval-2.l: Adjust expectations.
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2018-08-05 H.J. Lu <hongjiu.lu@intel.com>
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* testsuite/gas/i386/i386.exp: Run evex-no-scale-32 and
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@ -289,8 +289,7 @@ i386_intel_simplify_register (expressionS *e)
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&& (i386_regtab[reg_num].reg_type.bitfield.xmmword
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|| i386_regtab[reg_num].reg_type.bitfield.ymmword
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|| i386_regtab[reg_num].reg_type.bitfield.zmmword
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|| i386_regtab[reg_num].reg_num == RegRiz
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|| i386_regtab[reg_num].reg_num == RegEiz))
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|| i386_regtab[reg_num].reg_num == RegIZ))
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intel_state.index = i386_regtab + reg_num;
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else if (!intel_state.base && !intel_state.in_scale)
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intel_state.base = i386_regtab + reg_num;
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@ -7094,8 +7094,7 @@ build_modrm_byte (void)
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if (i.tm.opcode_modifier.vecsib)
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{
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if (i.index_reg->reg_num == RegEiz
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|| i.index_reg->reg_num == RegRiz)
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if (i.index_reg->reg_num == RegIZ)
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abort ();
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i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
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@ -7166,8 +7165,7 @@ build_modrm_byte (void)
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else if (!i.tm.opcode_modifier.vecsib)
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{
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/* !i.base_reg && i.index_reg */
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if (i.index_reg->reg_num == RegEiz
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|| i.index_reg->reg_num == RegRiz)
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if (i.index_reg->reg_num == RegIZ)
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i.sib.index = NO_INDEX_REGISTER;
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else
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i.sib.index = i.index_reg->reg_num;
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@ -7193,8 +7191,7 @@ build_modrm_byte (void)
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}
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}
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/* RIP addressing for 64bit mode. */
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else if (i.base_reg->reg_num == RegRip ||
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i.base_reg->reg_num == RegEip)
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else if (i.base_reg->reg_num == RegIP)
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{
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gas_assert (!i.tm.opcode_modifier.vecsib);
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i.rm.regmem = NO_BASE_REGISTER;
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@ -7286,8 +7283,7 @@ build_modrm_byte (void)
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}
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else if (!i.tm.opcode_modifier.vecsib)
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{
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if (i.index_reg->reg_num == RegEiz
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|| i.index_reg->reg_num == RegRiz)
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if (i.index_reg->reg_num == RegIZ)
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i.sib.index = NO_INDEX_REGISTER;
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else
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i.sib.index = i.index_reg->reg_num;
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@ -8133,8 +8129,7 @@ output_disp (fragS *insn_start_frag, offsetT insn_start_off)
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{
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fixP->fx_tcbit = i.rex != 0;
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if (i.base_reg
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&& (i.base_reg->reg_num == RegRip
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|| i.base_reg->reg_num == RegEip))
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&& (i.base_reg->reg_num == RegIP))
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fixP->fx_tcbit2 = 1;
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}
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else
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@ -9235,9 +9230,7 @@ i386_addressing_mode (void)
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if (addr_reg)
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{
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if (addr_reg->reg_num == RegEip
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|| addr_reg->reg_num == RegEiz
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|| addr_reg->reg_type.bitfield.dword)
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if (addr_reg->reg_type.bitfield.dword)
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addr_mode = CODE_32BIT;
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else if (flag_code != CODE_64BIT
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&& addr_reg->reg_type.bitfield.word)
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@ -9347,21 +9340,18 @@ bad_address:
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{
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/* 32-bit/64-bit checks. */
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if ((i.base_reg
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&& (addr_mode == CODE_64BIT
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? !i.base_reg->reg_type.bitfield.qword
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: !i.base_reg->reg_type.bitfield.dword)
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&& (i.index_reg
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|| (i.base_reg->reg_num
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!= (addr_mode == CODE_64BIT ? RegRip : RegEip))))
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&& ((addr_mode == CODE_64BIT
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? !i.base_reg->reg_type.bitfield.qword
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: !i.base_reg->reg_type.bitfield.dword)
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|| (i.index_reg && i.base_reg->reg_num == RegIP)
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|| i.base_reg->reg_num == RegIZ))
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|| (i.index_reg
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&& !i.index_reg->reg_type.bitfield.xmmword
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&& !i.index_reg->reg_type.bitfield.ymmword
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&& !i.index_reg->reg_type.bitfield.zmmword
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&& ((addr_mode == CODE_64BIT
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? !(i.index_reg->reg_type.bitfield.qword
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|| i.index_reg->reg_num == RegRiz)
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: !(i.index_reg->reg_type.bitfield.dword
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|| i.index_reg->reg_num == RegEiz))
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? !i.index_reg->reg_type.bitfield.qword
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: !i.index_reg->reg_type.bitfield.dword)
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|| !i.index_reg->reg_type.bitfield.baseindex)))
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goto bad_address;
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@ -9370,7 +9360,7 @@ bad_address:
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|| (current_templates->start->base_opcode & ~1) == 0x0f1a)
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{
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/* They cannot use RIP-relative addressing. */
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if (i.base_reg && i.base_reg->reg_num == RegRip)
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if (i.base_reg && i.base_reg->reg_num == RegIP)
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{
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as_bad (_("`%s' cannot be used here"), operand_string);
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return 0;
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@ -10430,8 +10420,7 @@ parse_real_register (char *reg_string, char **end_op)
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return (const reg_entry *) NULL;
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/* Don't allow fake index register unless allow_index_reg isn't 0. */
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if (!allow_index_reg
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&& (r->reg_num == RegEiz || r->reg_num == RegRiz))
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if (!allow_index_reg && r->reg_num == RegIZ)
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return (const reg_entry *) NULL;
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/* Upper 16 vector registers are only available with VREX in 64bit
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@ -2,7 +2,7 @@
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.*:6: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
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.*:7: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
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.*:8: Error: `\(%rip\)' cannot be used here
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.*:9: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
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.*:9: Error: .*
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.*:12: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
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.*:13: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
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.*:15: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
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@ -23,16 +23,16 @@
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.*:38: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
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.*:39: Warning: register scaling is being ignored here
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.*:40: Error: `base\(%rip\)' cannot be used here
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.*:41: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
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.*:41: Error: .*
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.*:44: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
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.*:45: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
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.*:46: Warning: register scaling is being ignored here
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.*:47: Error: `base\(%rip\)' cannot be used here
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.*:48: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
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.*:48: Error: .*
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.*:51: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
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.*:52: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
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.*:53: Error: `\[rip\]' cannot be used here
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.*:54: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
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.*:54: Error: .*
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.*:55: Error: `\[rax\+rsp\]' is not a valid base/index expression
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.*:58: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
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.*:59: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
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@ -54,13 +54,13 @@
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.*:84: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
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.*:85: Warning: register scaling is being ignored here
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.*:86: Error: `\[rip\+base\]' cannot be used here
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.*:87: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
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.*:87: Error: .*
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.*:88: Error: `\[rax\+rsp\]' is not a valid base/index expression
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.*:91: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
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.*:92: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
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.*:93: Warning: register scaling is being ignored here
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.*:94: Error: `\[rip\+base\]' cannot be used here
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.*:95: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
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.*:95: Error: .*
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.*:96: Error: `\[rax\+rsp\]' is not a valid base/index expression
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GAS LISTING .*
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@ -77,10 +77,7 @@ GAS LISTING .*
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.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
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[ ]*[1-9][0-9]*[ ]+4C1903
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[ ]*[1-9][0-9]*[ ]+bndmk \(%rip\), %bnd3
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[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1B bndmk \(%eip\), %bnd2
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.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
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[ ]*[1-9][0-9]*[ ]+15000000
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[ ]*[1-9][0-9]*[ ]+00
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[ ]*[1-9][0-9]*[ ]+bndmk \(%eip\), %bnd2
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[ ]*[1-9][0-9]*[ ]+
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[ ]*[1-9][0-9]*[ ]+\#\#\# bndmov
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[ ]*[1-9][0-9]*[ ]+\?\?\?\? 6766410F bndmov \(%r8d\), %bnd1
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@ -122,12 +119,12 @@ GAS LISTING .*
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.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
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[ ]*[1-9][0-9]*[ ]+09
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[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F20F1B bndcn 0x3\(%ecx,%eax,1\), %bnd1
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GAS LISTING .*
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.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
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[ ]*[1-9][0-9]*[ ]+4C0103
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[ ]*[1-9][0-9]*[ ]+bndcn %ecx, %bnd1
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GAS LISTING .*
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[ ]*[1-9][0-9]*[ ]+bndcn %cx, %bnd1
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[ ]*[1-9][0-9]*[ ]+
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[ ]*[1-9][0-9]*[ ]+\#\#\# bndstx
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@ -141,9 +138,7 @@ GAS LISTING .*
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.* Warning: register scaling is being ignored here
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[ ]*[1-9][0-9]*[ ]+47
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[ ]*[1-9][0-9]*[ ]+bndstx %bnd3, base\(%rip\)
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[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1B0D bndstx %bnd1, base\(%eip\)
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.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
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[ ]*[1-9][0-9]*[ ]+[0-9A-F]+
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[ ]*[1-9][0-9]*[ ]+bndstx %bnd1, base\(%eip\)
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[ ]*[1-9][0-9]*[ ]+
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[ ]*[1-9][0-9]*[ ]+\#\#\# bndldx
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[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1A44 bndldx 0x3\(%eax,%ebx,1\), %bnd0
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@ -156,9 +151,7 @@ GAS LISTING .*
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.* Warning: register scaling is being ignored here
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[ ]*[1-9][0-9]*[ ]*B8
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[ ]*[1-9][0-9]*[ ]*bndldx base\(%rip\), %bnd1
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[ ]*[1-9][0-9]*[ ]*\?\?\?\? 670F1A1D bndldx base\(%eip\), %bnd3
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.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
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[ ]*[1-9][0-9]*[ ]+[0-9A-F]+
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[ ]*[1-9][0-9]*[ ]*bndldx base\(%eip\), %bnd3
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[ ]*[1-9][0-9]*[ ]+
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[ ]*[1-9][0-9]*[ ]+\.intel_syntax noprefix
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[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1B bndmk bnd1, \[eax\]
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@ -168,10 +161,7 @@ GAS LISTING .*
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.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
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[ ]*[1-9][0-9]*[ ]+4C0203
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[ ]*[1-9][0-9]*[ ]*bndmk bnd3, \[rip\]
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[ ]*[1-9][0-9]*[ ]*\?\?\?\? 67F30F1B bndmk bnd2, \[eip\]
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.* Error: 32-bit address isn't allowed in 64-bit MPX instructions.
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[ ]*[1-9][0-9]*[ ]*15000000
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[ ]*[1-9][0-9]*[ ]*00
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[ ]*[1-9][0-9]*[ ]*bndmk bnd2, \[eip\]
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[ ]*[1-9][0-9]*[ ]+bndmk bnd2, \[rax\+rsp\]
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[ ]*[1-9][0-9]*[ ]+
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[ ]*[1-9][0-9]*[ ]+\#\#\# bndmov
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@ -182,9 +172,6 @@ GAS LISTING .*
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.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
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[ ]*[1-9][0-9]*[ ]+4C0203
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[ ]*[1-9][0-9]*[ ]+
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GAS LISTING .*
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[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67660F1B bndmov \[eax\], bnd1
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.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
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[ ]*[1-9][0-9]*[ ]+08
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@ -195,6 +182,9 @@ GAS LISTING .*
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[ ]*[1-9][0-9]*[ ]+\#\#\# bndcl
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[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1A bndcl bnd1, \[eax\]
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.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
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GAS LISTING .*
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[ ]*[1-9][0-9]*[ ]+08
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[ ]*[1-9][0-9]*[ ]+\?\?\?\? 67F30F1A bndcl bnd1, \[edx\+1\*eax\+0x3\]
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.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
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@ -234,17 +224,12 @@ GAS LISTING .*
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.* Warning: register scaling is being ignored here
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[ ]*[1-9][0-9]*[ ]+B8
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[ ]*[1-9][0-9]*[ ]+bndstx \[rip\+base\], bnd1
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[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1B1D bndstx \[eip\+base\], bnd3
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.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
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[ ]*[1-9][0-9]*[ ]+[0-9A-F]+
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[ ]*[1-9][0-9]*[ ]+bndstx \[eip\+base\], bnd3
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[ ]*[1-9][0-9]*[ ]+bndstx \[rax\+rsp\], bnd3
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[ ]*[1-9][0-9]*[ ]+
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[ ]*[1-9][0-9]*[ ]+\#\#\# bndldx
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[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1A44 bndldx bnd0, \[eax\+ebx\*1\+0x3\]
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.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
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GAS LISTING .*
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[ ]*[1-9][0-9]*[ ]+1803
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[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1A14 bndldx bnd2, \[1\*ebx\+3\]
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.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
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@ -254,8 +239,6 @@ GAS LISTING .*
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.* Warning: register scaling is being ignored here
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[ ]*[1-9][0-9]*[ ]+C7
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[ ]*[1-9][0-9]*[ ]+bndldx bnd1, \[rip\+base\]
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[ ]*[1-9][0-9]*[ ]+\?\?\?\? 670F1A1D bndldx bnd3, \[eip\+base\]
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.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\.
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[ ]*[1-9][0-9]*[ ]+[0-9A-F]+
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[ ]*[1-9][0-9]*[ ]+bndldx bnd3, \[eip\+base\]
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[ ]*[1-9][0-9]*[ ]+bndldx bnd3, \[rax\+rsp\]
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#pass
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@ -1,3 +1,14 @@
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2018-08-06 Jan Beulich <jbeulich@suse.com>
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* i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
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(RegIP, RegIZ): Define.
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* i386-reg.tbl: Adjust comments.
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(rip): Use Qword instead of BaseIndex. Use RegIP.
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(eip): Use Dword instead of BaseIndex. Use RegIP.
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(riz): Add Qword. Use RegIZ.
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(eiz): Add Dword. Use RegIZ.
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* i386-tbl.h: Re-generate.
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2018-08-03 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
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@ -895,11 +895,9 @@ typedef struct
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#define RegRex64 0x2 /* Extended 8 bit register. */
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#define RegVRex 0x4 /* Extended vector register. */
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unsigned char reg_num;
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#define RegRip ((unsigned char ) ~0)
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#define RegEip (RegRip - 1)
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#define RegIP ((unsigned char ) ~0)
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/* EIZ and RIZ are fake index registers. */
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#define RegEiz (RegEip - 1)
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#define RegRiz (RegEiz - 1)
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#define RegIZ (RegIP - 1)
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/* FLAT is a fake segment register (Intel mode). */
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#define RegFlat ((unsigned char) ~0)
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signed char dw2_regnum[2];
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||||
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@ -283,14 +283,14 @@ bnd0, RegBND, 0, 0, Dw2Inval, Dw2Inval
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bnd1, RegBND, 0, 1, Dw2Inval, Dw2Inval
|
||||
bnd2, RegBND, 0, 2, Dw2Inval, Dw2Inval
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||||
bnd3, RegBND, 0, 3, Dw2Inval, Dw2Inval
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||||
// No type will make these registers rejected for all purposes except
|
||||
// No Reg will make these registers rejected for all purposes except
|
||||
// for addressing. This saves creating one extra type for RIP/EIP.
|
||||
rip, BaseIndex, RegRex64, RegRip, Dw2Inval, 16
|
||||
eip, BaseIndex, RegRex64, RegEip, 8, Dw2Inval
|
||||
// No type will make these registers rejected for all purposes except
|
||||
rip, Qword, RegRex64, RegIP, Dw2Inval, 16
|
||||
eip, Dword, RegRex64, RegIP, 8, Dw2Inval
|
||||
// No Reg will make these registers rejected for all purposes except
|
||||
// for addressing.
|
||||
riz, BaseIndex, RegRex64, RegRiz, Dw2Inval, Dw2Inval
|
||||
eiz, BaseIndex, 0, RegEiz, Dw2Inval, Dw2Inval
|
||||
riz, Qword|BaseIndex, RegRex64, RegIZ, Dw2Inval, Dw2Inval
|
||||
eiz, Dword|BaseIndex, 0, RegIZ, Dw2Inval, Dw2Inval
|
||||
// fp regs.
|
||||
st(0), FloatReg|Acc, 0, 0, 11, 33
|
||||
st(1), FloatReg, 0, 1, 12, 34
|
||||
|
|
|
|||
|
|
@ -73973,24 +73973,24 @@ const reg_entry i386_regtab[] =
|
|||
0, 3, { Dw2Inval, Dw2Inval } },
|
||||
{ "rip",
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 } },
|
||||
RegRex64, RegRip, { Dw2Inval, 16 } },
|
||||
RegRex64, RegIP, { Dw2Inval, 16 } },
|
||||
{ "eip",
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 } },
|
||||
RegRex64, RegEip, { 8, Dw2Inval } },
|
||||
RegRex64, RegIP, { 8, Dw2Inval } },
|
||||
{ "riz",
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 } },
|
||||
RegRex64, RegRiz, { Dw2Inval, Dw2Inval } },
|
||||
RegRex64, RegIZ, { Dw2Inval, Dw2Inval } },
|
||||
{ "eiz",
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 } },
|
||||
0, RegEiz, { Dw2Inval, Dw2Inval } },
|
||||
0, RegIZ, { Dw2Inval, Dw2Inval } },
|
||||
{ "st(0)",
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
|
||||
|
|
|
|||
Loading…
Reference in New Issue