From e9bffec9afc45cf7c49308f0b4b8cc6bf68f58f2 Mon Sep 17 00:00:00 2001 From: "Jose E. Marchesi" Date: Thu, 4 Jun 2020 16:15:53 +0200 Subject: [PATCH] opcodes: discriminate endianness and insn-endianness in CGEN ports The CGEN support code in opcodes accesses instruction contents using a couple of functions defined in cgen-opc.c: cgen_get_insn_value and cgen_put_insn_value. These functions use the "instruction endianness" in the CPU description to order the read/written bytes. The process of writing an instruction to the object file is: a) cgen_put_insn_value ;; Writes out the opcodes. b) ARCH_cgen_insert_operand insert_normal insert_1 cgen_put_insn_value ;; Writes out the bytes of the ;; operand. Likewise, the process of reading an instruction from the object file is: a) cgen_get_insn_value ;; Reads the opcodes. b) ARCH_cgen_extract_operand extract_normal extract_1 cgen_get_insn_value ;; Reads in the bytes of the ;; operand. As can be seen above, cgen_{get,put}_insn_value are used to both process the instruction opcodes (the constant fields conforming the base instruction) and also the values of the instruction operands, such as immediates. This is problematic for architectures in which the endianness of instructions is different to the endianness of data. An example is BPF, where instructions are always encoded big-endian but the data may be either big or little. This patch changes the cgen_{get,put}_insn_value functions in order to get an extra argument with the endianness to use, and adapts the existin callers to these functions in order to provide cd->endian or cd->insn_endian, whatever appropriate. Callers like extract_1 and insert_1 pass cd->endian (since they are reading/writing operand values) while callers reading/writing the base instruction pass cd->insn_endian instead. A few little adjustments have been needed in some existing CGEN based ports: * The BPF assembler uses cgen_put_insn_value. It has been adapted to pass the new endian argument. * The mep port has code in mep.opc that uses cgen_{get,put}_insn_value. It has been adapted to pass the new endianargument. Ditto for a call in the assembler. Tested with --enable-targets=all. Regested in all supported targets. No regressions. include/ChangeLog: 2020-06-04 Jose E. Marchesi * opcode/cgen.h: Get an `endian' argument in both cgen_get_insn_value and cgen_put_insn_value. opcodes/ChangeLog: 2020-06-04 Jose E. Marchesi * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument. (cgen_put_insn_value): Likewise. (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value. * cgen-dis.in (print_insn): Likewise. * cgen-ibld.in (insert_1): Likewise. (insert_1): Likewise. (insert_insn_normal): Likewise. (extract_1): Likewise. * bpf-dis.c: Regenerate. * bpf-ibld.c: Likewise. * bpf-ibld.c: Likewise. * cgen-dis.in: Likewise. * cgen-ibld.in: Likewise. * cgen-opc.c: Likewise. * epiphany-dis.c: Likewise. * epiphany-ibld.c: Likewise. * fr30-dis.c: Likewise. * fr30-ibld.c: Likewise. * frv-dis.c: Likewise. * frv-ibld.c: Likewise. * ip2k-dis.c: Likewise. * ip2k-ibld.c: Likewise. * iq2000-dis.c: Likewise. * iq2000-ibld.c: Likewise. * lm32-dis.c: Likewise. * lm32-ibld.c: Likewise. * m32c-dis.c: Likewise. * m32c-ibld.c: Likewise. * m32r-dis.c: Likewise. * m32r-ibld.c: Likewise. * mep-dis.c: Likewise. * mep-ibld.c: Likewise. * mt-dis.c: Likewise. * mt-ibld.c: Likewise. * or1k-dis.c: Likewise. * or1k-ibld.c: Likewise. * xc16x-dis.c: Likewise. * xc16x-ibld.c: Likewise. * xstormy16-dis.c: Likewise. * xstormy16-ibld.c: Likewise. gas/ChangeLog: 2020-06-04 Jose E. Marchesi * cgen.c (gas_cgen_finish_insn): Pass the endianness to cgen_put_insn_value. (gas_cgen_md_apply_fix): Likewise. (gas_cgen_md_apply_fix): Likewise. * config/tc-bpf.c (md_apply_fix): Pass data endianness to cgen_put_insn_value. * config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to cgen_put_insn_value. cpu/ChangeLog: 2020-06-02 Jose E. Marchesi * mep.opc (print_slot_insn): Pass the insn endianness to cgen_get_insn_value. --- cpu/ChangeLog | 5 +++++ cpu/mep.opc | 2 +- gas/ChangeLog | 11 ++++++++++ gas/cgen.c | 9 ++++++--- gas/config/tc-bpf.c | 3 ++- gas/config/tc-mep.c | 2 +- include/ChangeLog | 5 +++++ include/opcode/cgen.h | 4 ++-- opcodes/ChangeLog | 43 ++++++++++++++++++++++++++++++++++++++++ opcodes/bpf-dis.c | 2 +- opcodes/bpf-ibld.c | 10 +++++----- opcodes/cgen-dis.in | 2 +- opcodes/cgen-ibld.in | 10 +++++----- opcodes/cgen-opc.c | 18 ++++++++++------- opcodes/epiphany-dis.c | 2 +- opcodes/epiphany-ibld.c | 10 +++++----- opcodes/fr30-dis.c | 2 +- opcodes/fr30-ibld.c | 10 +++++----- opcodes/frv-dis.c | 2 +- opcodes/frv-ibld.c | 10 +++++----- opcodes/ip2k-dis.c | 2 +- opcodes/ip2k-ibld.c | 10 +++++----- opcodes/iq2000-dis.c | 2 +- opcodes/iq2000-ibld.c | 10 +++++----- opcodes/lm32-dis.c | 2 +- opcodes/lm32-ibld.c | 10 +++++----- opcodes/m32c-dis.c | 2 +- opcodes/m32c-ibld.c | 10 +++++----- opcodes/m32r-dis.c | 2 +- opcodes/m32r-ibld.c | 10 +++++----- opcodes/mep-dis.c | 4 ++-- opcodes/mep-ibld.c | 10 +++++----- opcodes/mt-dis.c | 2 +- opcodes/mt-ibld.c | 10 +++++----- opcodes/or1k-dis.c | 2 +- opcodes/or1k-ibld.c | 10 +++++----- opcodes/xc16x-dis.c | 2 +- opcodes/xc16x-ibld.c | 10 +++++----- opcodes/xstormy16-dis.c | 2 +- opcodes/xstormy16-ibld.c | 10 +++++----- 40 files changed, 178 insertions(+), 106 deletions(-) diff --git a/cpu/ChangeLog b/cpu/ChangeLog index 30b884c951..41ff181234 100644 --- a/cpu/ChangeLog +++ b/cpu/ChangeLog @@ -1,3 +1,8 @@ +2020-06-02 Jose E. Marchesi + + * mep.opc (print_slot_insn): Pass the insn endianness to + cgen_get_insn_value. + 2020-05-28 Jose E. Marchesi David Faust diff --git a/cpu/mep.opc b/cpu/mep.opc index 34e279d98e..5a4c93dc3a 100644 --- a/cpu/mep.opc +++ b/cpu/mep.opc @@ -1271,7 +1271,7 @@ print_slot_insn (CGEN_CPU_DESC cd, CGEN_INSN_INT insn_value; CGEN_EXTRACT_INFO ex_info; - insn_value = cgen_get_insn_value (cd, buf, 32); + insn_value = cgen_get_insn_value (cd, buf, 32, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call read_insn, since the incoming buffer is already read (and possibly diff --git a/gas/ChangeLog b/gas/ChangeLog index 6484c62d30..bb917ccc70 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,14 @@ +2020-06-04 Jose E. Marchesi + + * cgen.c (gas_cgen_finish_insn): Pass the endianness to + cgen_put_insn_value. + (gas_cgen_md_apply_fix): Likewise. + (gas_cgen_md_apply_fix): Likewise. + * config/tc-bpf.c (md_apply_fix): Pass data endianness to + cgen_put_insn_value. + * config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to + cgen_put_insn_value. + 2020-06-04 Alan Modra * testsuite/config/default.exp: Remove global directive outside diff --git a/gas/cgen.c b/gas/cgen.c index b94802ebc8..8d1867b731 100644 --- a/gas/cgen.c +++ b/gas/cgen.c @@ -621,7 +621,8 @@ gas_cgen_finish_insn (const CGEN_INSN *insn, CGEN_INSN_BYTES_PTR buf, /* If we're recording insns as numbers (rather than a string of bytes), target byte order handling is deferred until now. */ #if CGEN_INT_INSN_P - cgen_put_insn_value (gas_cgen_cpu_desc, (unsigned char *) f, length, *buf); + cgen_put_insn_value (gas_cgen_cpu_desc, (unsigned char *) f, length, *buf, + gas_cgen_cpu_desc->insn_endian); #else memcpy (f, buf, byte_len); #endif @@ -906,13 +907,15 @@ gas_cgen_md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) { CGEN_INSN_INT insn_value = cgen_get_insn_value (cd, (unsigned char *) where, - CGEN_INSN_BITSIZE (insn)); + CGEN_INSN_BITSIZE (insn), + cd->insn_endian); /* ??? 0 is passed for `pc'. */ errmsg = CGEN_CPU_INSERT_OPERAND (cd) (cd, opindex, fields, &insn_value, (bfd_vma) 0); cgen_put_insn_value (cd, (unsigned char *) where, - CGEN_INSN_BITSIZE (insn), insn_value); + CGEN_INSN_BITSIZE (insn), insn_value, + cd->insn_endian); } #else /* ??? 0 is passed for `pc'. */ diff --git a/gas/config/tc-bpf.c b/gas/config/tc-bpf.c index a379acbbed..7c7d22e477 100644 --- a/gas/config/tc-bpf.c +++ b/gas/config/tc-bpf.c @@ -324,7 +324,8 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg) this code is executed only once per instruction. */ where = fixP->fx_frag->fr_literal + fixP->fx_where; cgen_put_insn_value (gas_cgen_cpu_desc, (unsigned char *) where + 1, 8, - target_big_endian ? 0x01 : 0x10); + target_big_endian ? 0x01 : 0x10, + gas_cgen_cpu_desc->endian); /* Fallthrough. */ case BPF_OPERAND_DISP16: /* The PC-relative displacement fields in jump instructions diff --git a/gas/config/tc-mep.c b/gas/config/tc-mep.c index 26fb80ec8a..6b52841fa9 100644 --- a/gas/config/tc-mep.c +++ b/gas/config/tc-mep.c @@ -1111,7 +1111,7 @@ mep_check_ivc2_scheduling (void) #if CGEN_INT_INSN_P cgen_put_insn_value (gas_cgen_cpu_desc, (unsigned char *) temp, 32, - m->buffer[0]); + m->buffer[0], gas_cgen_cpu_desc->insn_endian); #else memcpy (temp, m->buffer, byte_len); #endif diff --git a/include/ChangeLog b/include/ChangeLog index df4208eda1..e0bef67438 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,8 @@ +2020-06-04 Jose E. Marchesi + + * opcode/cgen.h: Get an `endian' argument in both + cgen_get_insn_value and cgen_put_insn_value. + 2020-06-04 Jose E. Marchesi * opcode/cgen.h (enum cgen_cpu_open_arg): New value diff --git a/include/opcode/cgen.h b/include/opcode/cgen.h index 3f325447b9..cae279541f 100644 --- a/include/opcode/cgen.h +++ b/include/opcode/cgen.h @@ -1463,9 +1463,9 @@ extern const CGEN_INSN * cgen_lookup_get_insn_operands /* Cover fns to bfd_get/set. */ extern CGEN_INSN_INT cgen_get_insn_value - (CGEN_CPU_DESC, unsigned char *, int); + (CGEN_CPU_DESC, unsigned char *, int, int); extern void cgen_put_insn_value - (CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT); + (CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT, int); extern CGEN_INSN_INT cgen_get_base_insn_value (CGEN_CPU_DESC, unsigned char *, int); diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index dc4c285eb0..39df27efd7 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,46 @@ +2020-06-03 Jose E. Marchesi + + * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument. + (cgen_put_insn_value): Likewise. + (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value. + * cgen-dis.in (print_insn): Likewise. + * cgen-ibld.in (insert_1): Likewise. + (insert_1): Likewise. + (insert_insn_normal): Likewise. + (extract_1): Likewise. + * bpf-dis.c: Regenerate. + * bpf-ibld.c: Likewise. + * bpf-ibld.c: Likewise. + * cgen-dis.in: Likewise. + * cgen-ibld.in: Likewise. + * cgen-opc.c: Likewise. + * epiphany-dis.c: Likewise. + * epiphany-ibld.c: Likewise. + * fr30-dis.c: Likewise. + * fr30-ibld.c: Likewise. + * frv-dis.c: Likewise. + * frv-ibld.c: Likewise. + * ip2k-dis.c: Likewise. + * ip2k-ibld.c: Likewise. + * iq2000-dis.c: Likewise. + * iq2000-ibld.c: Likewise. + * lm32-dis.c: Likewise. + * lm32-ibld.c: Likewise. + * m32c-dis.c: Likewise. + * m32c-ibld.c: Likewise. + * m32r-dis.c: Likewise. + * m32r-ibld.c: Likewise. + * mep-dis.c: Likewise. + * mep-ibld.c: Likewise. + * mt-dis.c: Likewise. + * mt-ibld.c: Likewise. + * or1k-dis.c: Likewise. + * or1k-ibld.c: Likewise. + * xc16x-dis.c: Likewise. + * xc16x-ibld.c: Likewise. + * xstormy16-dis.c: Likewise. + * xstormy16-ibld.c: Likewise. + 2020-06-04 Jose E. Marchesi * cgen-dis.in (cpu_desc_list): New field `insn_endian'. diff --git a/opcodes/bpf-dis.c b/opcodes/bpf-dis.c index 21d9308be0..4d01112d25 100644 --- a/opcodes/bpf-dis.c +++ b/opcodes/bpf-dis.c @@ -376,7 +376,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/bpf-ibld.c b/opcodes/bpf-ibld.c index d5fa57a1c4..392dcebdd2 100644 --- a/opcodes/bpf-ibld.c +++ b/opcodes/bpf-ibld.c @@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; diff --git a/opcodes/cgen-dis.in b/opcodes/cgen-dis.in index 378b984551..2d5feebdb8 100644 --- a/opcodes/cgen-dis.in +++ b/opcodes/cgen-dis.in @@ -210,7 +210,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/cgen-ibld.in b/opcodes/cgen-ibld.in index 6a9b97fcb5..ae9d20d6f4 100644 --- a/opcodes/cgen-ibld.in +++ b/opcodes/cgen-ibld.in @@ -87,7 +87,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -97,7 +97,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -268,8 +268,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -386,7 +386,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; diff --git a/opcodes/cgen-opc.c b/opcodes/cgen-opc.c index f3cfa9d9c3..18f9aae971 100644 --- a/opcodes/cgen-opc.c +++ b/opcodes/cgen-opc.c @@ -357,9 +357,10 @@ cgen_macro_insn_count (CGEN_CPU_DESC cd) /* Cover function to read and properly byteswap an insn value. */ CGEN_INSN_INT -cgen_get_insn_value (CGEN_CPU_DESC cd, unsigned char *buf, int length) +cgen_get_insn_value (CGEN_CPU_DESC cd, unsigned char *buf, int length, + int endian) { - int big_p = (cd->insn_endian == CGEN_ENDIAN_BIG); + int big_p = (endian == CGEN_ENDIAN_BIG); int insn_chunk_bitsize = cd->insn_chunk_bitsize; CGEN_INSN_INT value = 0; @@ -385,7 +386,7 @@ cgen_get_insn_value (CGEN_CPU_DESC cd, unsigned char *buf, int length) } else { - value = bfd_get_bits (buf, length, cd->insn_endian == CGEN_ENDIAN_BIG); + value = bfd_get_bits (buf, length, endian == CGEN_ENDIAN_BIG); } return value; @@ -397,9 +398,10 @@ void cgen_put_insn_value (CGEN_CPU_DESC cd, unsigned char *buf, int length, - CGEN_INSN_INT value) + CGEN_INSN_INT value, + int endian) { - int big_p = (cd->insn_endian == CGEN_ENDIAN_BIG); + int big_p = (endian == CGEN_ENDIAN_BIG); int insn_chunk_bitsize = cd->insn_chunk_bitsize; if (insn_chunk_bitsize != 0 && insn_chunk_bitsize < length) @@ -459,7 +461,8 @@ cgen_lookup_insn (CGEN_CPU_DESC cd, { info = NULL; insn_bytes_value = (unsigned char *) xmalloc (cd->max_insn_bitsize / 8); - cgen_put_insn_value (cd, insn_bytes_value, length, insn_int_value); + cgen_put_insn_value (cd, insn_bytes_value, length, insn_int_value, + cd->insn_endian); } else { @@ -467,7 +470,8 @@ cgen_lookup_insn (CGEN_CPU_DESC cd, ex_info.dis_info = NULL; ex_info.insn_bytes = insn_bytes_value; ex_info.valid = -1; - insn_int_value = cgen_get_insn_value (cd, insn_bytes_value, length); + insn_int_value = cgen_get_insn_value (cd, insn_bytes_value, length, + cd->insn_endian); } if (!insn) diff --git a/opcodes/epiphany-dis.c b/opcodes/epiphany-dis.c index 966b39fe09..83f8d7969e 100644 --- a/opcodes/epiphany-dis.c +++ b/opcodes/epiphany-dis.c @@ -451,7 +451,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/epiphany-ibld.c b/opcodes/epiphany-ibld.c index c23a969294..4a974edccd 100644 --- a/opcodes/epiphany-ibld.c +++ b/opcodes/epiphany-ibld.c @@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; diff --git a/opcodes/fr30-dis.c b/opcodes/fr30-dis.c index b98ea94a1a..ed89926cef 100644 --- a/opcodes/fr30-dis.c +++ b/opcodes/fr30-dis.c @@ -472,7 +472,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/fr30-ibld.c b/opcodes/fr30-ibld.c index 5544d550f5..6816154ab2 100644 --- a/opcodes/fr30-ibld.c +++ b/opcodes/fr30-ibld.c @@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; diff --git a/opcodes/frv-dis.c b/opcodes/frv-dis.c index 60f1a6141e..48b33596d0 100644 --- a/opcodes/frv-dis.c +++ b/opcodes/frv-dis.c @@ -569,7 +569,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/frv-ibld.c b/opcodes/frv-ibld.c index 0421884908..43bccbac59 100644 --- a/opcodes/frv-ibld.c +++ b/opcodes/frv-ibld.c @@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; diff --git a/opcodes/ip2k-dis.c b/opcodes/ip2k-dis.c index 4a53a7c246..6cc08ba9d4 100644 --- a/opcodes/ip2k-dis.c +++ b/opcodes/ip2k-dis.c @@ -461,7 +461,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/ip2k-ibld.c b/opcodes/ip2k-ibld.c index 9258f7d3ad..605d0bde04 100644 --- a/opcodes/ip2k-ibld.c +++ b/opcodes/ip2k-ibld.c @@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; diff --git a/opcodes/iq2000-dis.c b/opcodes/iq2000-dis.c index 3aab139c51..fbe70c02b4 100644 --- a/opcodes/iq2000-dis.c +++ b/opcodes/iq2000-dis.c @@ -362,7 +362,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/iq2000-ibld.c b/opcodes/iq2000-ibld.c index 319e994d84..2a87c709af 100644 --- a/opcodes/iq2000-ibld.c +++ b/opcodes/iq2000-ibld.c @@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; diff --git a/opcodes/lm32-dis.c b/opcodes/lm32-dis.c index 7ba84b3a66..e66ad06ba4 100644 --- a/opcodes/lm32-dis.c +++ b/opcodes/lm32-dis.c @@ -320,7 +320,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/lm32-ibld.c b/opcodes/lm32-ibld.c index 9b594e8e0e..2b0efdaa3f 100644 --- a/opcodes/lm32-ibld.c +++ b/opcodes/lm32-ibld.c @@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; diff --git a/opcodes/m32c-dis.c b/opcodes/m32c-dis.c index 41afca3cc0..19135fa0b2 100644 --- a/opcodes/m32c-dis.c +++ b/opcodes/m32c-dis.c @@ -1064,7 +1064,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/m32c-ibld.c b/opcodes/m32c-ibld.c index c1fca2e169..6ad4da967d 100644 --- a/opcodes/m32c-ibld.c +++ b/opcodes/m32c-ibld.c @@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c index e666739801..e15d3c3b94 100644 --- a/opcodes/m32r-dis.c +++ b/opcodes/m32r-dis.c @@ -452,7 +452,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/m32r-ibld.c b/opcodes/m32r-ibld.c index ddebc32428..559f47135f 100644 --- a/opcodes/m32r-ibld.c +++ b/opcodes/m32r-ibld.c @@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; diff --git a/opcodes/mep-dis.c b/opcodes/mep-dis.c index d2df588303..1292d830cb 100644 --- a/opcodes/mep-dis.c +++ b/opcodes/mep-dis.c @@ -467,7 +467,7 @@ print_slot_insn (CGEN_CPU_DESC cd, CGEN_INSN_INT insn_value; CGEN_EXTRACT_INFO ex_info; - insn_value = cgen_get_insn_value (cd, buf, 32); + insn_value = cgen_get_insn_value (cd, buf, 32, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call read_insn, since the incoming buffer is already read (and possibly @@ -1360,7 +1360,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/mep-ibld.c b/opcodes/mep-ibld.c index 6a73f419c9..66a30e1b45 100644 --- a/opcodes/mep-ibld.c +++ b/opcodes/mep-ibld.c @@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; diff --git a/opcodes/mt-dis.c b/opcodes/mt-dis.c index 3d552e8acb..b0358e34e2 100644 --- a/opcodes/mt-dis.c +++ b/opcodes/mt-dis.c @@ -463,7 +463,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/mt-ibld.c b/opcodes/mt-ibld.c index 53a0775f7a..683b76b2b4 100644 --- a/opcodes/mt-ibld.c +++ b/opcodes/mt-ibld.c @@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; diff --git a/opcodes/or1k-dis.c b/opcodes/or1k-dis.c index d350d2bbae..87ff206488 100644 --- a/opcodes/or1k-dis.c +++ b/opcodes/or1k-dis.c @@ -347,7 +347,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/or1k-ibld.c b/opcodes/or1k-ibld.c index 2e476cb152..7b89260bf5 100644 --- a/opcodes/or1k-ibld.c +++ b/opcodes/or1k-ibld.c @@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; diff --git a/opcodes/xc16x-dis.c b/opcodes/xc16x-dis.c index 2cf926b68f..d4c24f033d 100644 --- a/opcodes/xc16x-dis.c +++ b/opcodes/xc16x-dis.c @@ -593,7 +593,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/xc16x-ibld.c b/opcodes/xc16x-ibld.c index 6b228bcdfc..b2802fecb6 100644 --- a/opcodes/xc16x-ibld.c +++ b/opcodes/xc16x-ibld.c @@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; diff --git a/opcodes/xstormy16-dis.c b/opcodes/xstormy16-dis.c index 8382c3da85..c2723167fa 100644 --- a/opcodes/xstormy16-dis.c +++ b/opcodes/xstormy16-dis.c @@ -341,7 +341,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/xstormy16-ibld.c b/opcodes/xstormy16-ibld.c index 70cf88d546..eaffbeef90 100644 --- a/opcodes/xstormy16-ibld.c +++ b/opcodes/xstormy16-ibld.c @@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length;