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Add assembler and disassembler support for the new Armv8.4-a instructions for AArch64. 

Some of these instructions have been back-ported as optional extensions to
Armv8.2-a and higher, but others are only available for Armv8.4-a.

opcodes/

	* aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
	(rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
	(sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
	(fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
	(ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
	(ldapur, ldapursw, stlur): New.
	* aarch64-dis-2.c: Regenerate.

gas/

	* testsuite/gas/aarch64/armv8_4-a-illegal.d: New.
	* testsuite/gas/aarch64/armv8_4-a-illegal.l: New.
	* testsuite/gas/aarch64/armv8_4-a-illegal.s: New.
	* testsuite/gas/aarch64/armv8_4-a.d: New.
	* testsuite/gas/aarch64/armv8_4-a.s: New.
	* testsuite/gas/aarch64/armv8_2-a-crypto-fp16.s: New.
	* testsuite/gas/aarch64/armv8_2-a-crypto-fp16.d: New.
	* testsuite/gas/aarch64/armv8_3-a-crypto-fp16.d: New.
	* testsuite/gas/aarch64/armv8_4-a-crypto-fp16.d: New.
	* testsuite/gas/aarch64/armv8_2-a-crypto-fp16-illegal.s: New.
	* testsuite/gas/aarch64/armv8_2-a-crypto-fp16-illegal.l: New.
	* testsuite/gas/aarch64/armv8_2-a-crypto-fp16-illegal.d: New.
This commit is contained in:
Tamar Christina 2017-11-16 16:07:07 +00:00
parent e849ea896b
commit e9dbdd80cb
16 changed files with 16902 additions and 3470 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
gas/ChangeLog
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2017-11-16 Tamar Christina <tamar.christina@arm.com>
* testsuite/gas/aarch64/armv8_4-a-illegal.d: New.
* testsuite/gas/aarch64/armv8_4-a-illegal.l: New.
* testsuite/gas/aarch64/armv8_4-a-illegal.s: New.
* testsuite/gas/aarch64/armv8_4-a.d: New.
* testsuite/gas/aarch64/armv8_4-a.s: New.
* testsuite/gas/aarch64/armv8_2-a-crypto-fp16.s: New.
* testsuite/gas/aarch64/armv8_2-a-crypto-fp16.d: New.
* testsuite/gas/aarch64/armv8_3-a-crypto-fp16.d: New.
* testsuite/gas/aarch64/armv8_4-a-crypto-fp16.d: New.
* testsuite/gas/aarch64/armv8_2-a-crypto-fp16-illegal.s: New.
* testsuite/gas/aarch64/armv8_2-a-crypto-fp16-illegal.l: New.
* testsuite/gas/aarch64/armv8_2-a-crypto-fp16-illegal.d: New.
2017-11-16 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/noextreg.s: Add tests with register index

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#as: -march=armv8.2-a+crypto+sm4+sha3
#source: armv8_2-a-illegal.s
#error-output: armv8_2-a-illegal.l

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[^:]+: Assembler messages:
[^:]+:[0-9]+: Error: operand 1 must be a floating-point register -- `sha512h X0,Q0,V1.2D'
[^:]+:[0-9]+: Error: operand mismatch -- `sha512h Q0,Q1,V2.16B'
[^:]+:[0-9]+: Info: did you mean this\?
[^:]+:[0-9]+: Info: sha512h q0, q1, v2.2d
[^:]+:[0-9]+: Error: operand 1 must be a floating-point register -- `sha512h2 X0,Q0,V1.2D'
[^:]+:[0-9]+: Error: operand mismatch -- `sha512h2 Q0,Q1,V2.16B'
[^:]+:[0-9]+: Info: did you mean this\?
[^:]+:[0-9]+: Info: sha512h2 q0, q1, v2.2d
[^:]+:[0-9]+: Error: operand mismatch -- `sha512su0 V1.2D,v2.16B'
[^:]+:[0-9]+: Info: did you mean this\?
[^:]+:[0-9]+: Info: sha512su0 v1.2d, v2.2d
[^:]+:[0-9]+: Error: invalid use of vector register at operand 1 -- `sha512su0 V0,V2.2D'
[^:]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sha512su1 X0,X1,X2'
[^:]+:[0-9]+: Error: operand mismatch -- `sha512su1 V1.2D,V2.16B,V2.2D'
[^:]+:[0-9]+: Info: did you mean this\?
[^:]+:[0-9]+: Info: sha512su1 v1.2d, v2.2d, v2.2d
[^:]+:[0-9]+: Error: operand mismatch -- `eor3 V1.2D,V2.2D,V3.2D,V4.2D'
[^:]+:[0-9]+: Info: did you mean this\?
[^:]+:[0-9]+: Info: eor3 v1.16b, v2.16b, v3.16b, v4.16b
[^:]+:[0-9]+: Error: operand mismatch -- `rax1 V0.4S,V2.4S,V3.4S'
[^:]+:[0-9]+: Info: did you mean this\?
[^:]+:[0-9]+: Info: rax1 v0.2d, v2.2d, v3.2d
[^:]+:[0-9]+: Error: immediate value out of range 0 to 63 at operand 4 -- `xar v0.2d,v1.2d,v3.2d,128'
[^:]+:[0-9]+: Error: immediate value out of range 0 to 63 at operand 4 -- `xar v0.2d,v1.2d,v3.2d,-128'

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# SHA2
sha512h X0, Q0, V1.2D
sha512h Q0, Q1, V2.16B
sha512h2 X0, Q0, V1.2D
sha512h2 Q0, Q1, V2.16B
sha512su0 V1.2D, v2.16B
sha512su0 V0, V2.2D
sha512su1 X0, X1, X2
sha512su1 V1.2D, V2.16B, V2.2D
eor3 V1.2D, V2.2D, V3.2D, V4.2D
rax1 V0.4S, V2.4S, V3.4S
xar v0.2d, v1.2d, v3.2d, 128
xar v0.2d, v1.2d, v3.2d, -128

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# Print a 4 operand instruction
.macro print_gen4reg op, d, pd1=, pd2=, n, pn1=, pn2=, m, pm1=, pm2=, w , pw1=, pw2=
.ifnb \d
\op \pd1\d\()\pd2, \pn1\n\()\pn2, \pm1\m\()\pm2, \pw1\w\()\pw2
.else
.ifnb \n
\op \pn1\n\()\pn2, \pm1\m\()\pm2, \pw1\w\()\pw2
.else
\op \pm1\m\()\pm2, \pw1\w\()\pw2
.endif
.endif
.endm
.macro gen4reg_iter_d_offset op, d, pd1=, pd2=, r
.irp m, 03, 82, 13
\op \pd1\d\()\pd2, [\r, \m]
.endr
.endm
.macro gen4reg_iter_d_n_w op, d, pd1=, pd2=, n, pn1=, pn2=, m, pm1=, pm2=, pw1=, pw2=
.irp w, 3, 11, 15
print_gen4reg \op, \d, \pd1, \pd2, \n, \pn1, \pn2, \m, \pm1, \pm2, \w, \pw1, \pw2
.endr
.endm
.macro gen4reg_iter_d_n op, d, pd1=, pd2=, n, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=
.irp m, 0, 8, 12
gen4reg_iter_d_n_w \op, \d, \pd1, \pd2, \n, \pn1, \pn2, \m, \pm1, \pm2, \pw1, \pw2
.endr
.endm
.macro gen4reg_iter_d op, d, pd1=, pd2=, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=
.irp n, 2, 15, 30
gen4reg_iter_d_n \op, \d, \pd1, \pd2, \n, \pn1, \pn2, \pm1, \pm2, \pw1, \pw2
.endr
.endm
.macro gen4reg_iter op, pd1=, pd2=, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=
.irp d, 0, 7, 16, 30
gen4reg_iter_d \op, \d, \pd1, \pd2, \pn1, \pn2, \pm1, \pm2, \pw1, \pw2
.endr
.endm
# Print a 3 operand instruction
.macro gen3reg_iter op, pd1=, pd2=, pn1=, pn2=, pm1=, pm2=
.irp d, 0, 7, 16, 30
gen4reg_iter_d \op,,, \d, \pd1, \pd2, \pn1, \pn2, \pm1, \pm2
.endr
.endm
.macro gen3reg_iter_lane op, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=, x:vararg
.irp l, \x
gen4reg_iter_d \op,,,, \pn1, \pn2, \pm1, \pm2, \pw1, \pw2[\l]
.endr
.endm
# Print a 2 operand instruction
.macro gen2reg_iter op, pd1=, pd2=, pn1=, pn2=
.irp d, 0, 7, 16, 30
gen4reg_iter_d_n \op,,,,,, \d, \pd1, \pd2, \pn1, \pn2
.endr
.endm
.macro gen2reg_iter_offset op, pd1=, pd2=, r
.irp d, 0, 7, 16, 30
gen4reg_iter_d_offset \op, \d, \pd1, \pd2, \r,
.endr
.endm
# Print a 1 operand instruction
.macro gen1reg_iter op, pd1=, pd2=
.irp d, 0, 7, 16, 30
\op \pd1\d\()\pd2
.endr
.endm
.text
func:
gen3reg_iter sha512h q,, q,, v,.2d
gen3reg_iter sha512h2 q,, q,, v,.2d
gen2reg_iter sha512su0 v,.2d, v,.2d
gen3reg_iter sha512su1 v,.2d, v,.2d, v,.2d
gen4reg_iter eor3 v,.16b, v,.16b, v,.16b, v,.16b
gen3reg_iter rax1 v,.2d, v,.2d, v,.2d
gen4reg_iter xar v,.2d, v,.2d, v,.2d,,
gen4reg_iter bcax v,.16b, v,.16b, v,.16b, v,.16b
gen4reg_iter sm3ss1 v,.4s, v,.4s, v,.4s, v,.4s
gen3reg_iter_lane sm3tt1a v,.4s, v,.4s, v,.s, 0, 1, 2, 3
gen3reg_iter_lane sm3tt1b v,.4s, v,.4s, v,.s, 0, 1, 2, 3
gen3reg_iter_lane sm3tt2a v,.4s, v,.4s, v,.s, 0, 1, 2, 3
gen3reg_iter_lane sm3tt2b v,.4s, v,.4s, v,.s, 0, 1, 2, 3
gen3reg_iter sm3partw1 v,.4s, v,.4s, v,.4s
gen3reg_iter sm3partw2 v,.4s, v,.4s, v,.4s
gen2reg_iter sm4e v,.4s, v,.4s
gen3reg_iter sm4ekey v,.4s, v,.4s, v,.4s
gen3reg_iter fmlal v,.2s, v,.2h, v,.2h
gen3reg_iter fmlal v,.4s, v,.4h, v,.4h
gen3reg_iter fmlsl v,.2s, v,.2h, v,.2h
gen3reg_iter fmlsl v,.4s, v,.4h, v,.4h
gen3reg_iter fmlal2 v,.2s, v,.2h, v,.2h
gen3reg_iter fmlal2 v,.4s, v,.4h, v,.4h
gen3reg_iter fmlsl2 v,.2s, v,.2h, v,.2h
gen3reg_iter fmlsl2 v,.4s, v,.4h, v,.4h
gen3reg_iter_lane fmlal v,.2s, v,.2h, v,.h, 0, 1, 5, 7
gen3reg_iter_lane fmlal v,.4s, v,.4h, v,.h, 0, 1, 5, 7
gen3reg_iter_lane fmlsl v,.2s, v,.2h, v,.h, 0, 1, 5, 7
gen3reg_iter_lane fmlsl v,.4s, v,.4h, v,.h, 0, 1, 5, 7
gen3reg_iter_lane fmlal2 v,.2s, v,.2h, v,.h, 0, 1, 5, 7
gen3reg_iter_lane fmlal2 v,.4s, v,.4h, v,.h, 0, 1, 5, 7
gen3reg_iter_lane fmlsl2 v,.2s, v,.2h, v,.h, 0, 1, 5, 7
gen3reg_iter_lane fmlsl2 v,.4s, v,.4h, v,.h, 0, 1, 5, 7

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#as: -march=armv8.4-a
#source: armv8_4-a-illegal.s
#error-output: armv8_4-a-illegal.l

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[^:]+: Assembler messages:
[^:]+:[0-9]+: Error: immediate value out of range 0 to 63 at operand 2 -- `rmif X0,65,2'
[^:]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 3 -- `rmif X1,60,20'
[^:]+:[0-9]+: Error: immediate offset out of range -256 to 255 at operand 2 -- `ldapurb W0,\[X0,256\]'

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RMIF X0, 65, 2
RMIF X1, 60, 20
# These all use the same modifier, so it's sufficient to just test one.
LDAPURB W0, [X0, 256]

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# Print a 4 operand instruction
.macro print_gen4reg op, d, pd1=, pd2=, n, pn1=, pn2=, m, pm1=, pm2=, w , pw1=, pw2=
.ifnb \d
\op \pd1\d\()\pd2, \pn1\n\()\pn2, \pm1\m\()\pm2, \pw1\w\()\pw2
.else
.ifnb \n
\op \pn1\n\()\pn2, \pm1\m\()\pm2, \pw1\w\()\pw2
.else
\op \pm1\m\()\pm2, \pw1\w\()\pw2
.endif
.endif
.endm
.macro gen4reg_iter_d_offset op, d, pd1=, pd2=, r
.irp m, 03, 82, 13
\op \pd1\d\()\pd2, [\r, \m]
.endr
.endm
.macro gen4reg_iter_d_n_w op, d, pd1=, pd2=, n, pn1=, pn2=, m, pm1=, pm2=, pw1=, pw2=
.irp w, 3, 11, 15
print_gen4reg \op, \d, \pd1, \pd2, \n, \pn1, \pn2, \m, \pm1, \pm2, \w, \pw1, \pw2
.endr
.endm
.macro gen4reg_iter_d_n op, d, pd1=, pd2=, n, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=
.irp m, 0, 8, 12
gen4reg_iter_d_n_w \op, \d, \pd1, \pd2, \n, \pn1, \pn2, \m, \pm1, \pm2, \pw1, \pw2
.endr
.endm
.macro gen4reg_iter_d op, d, pd1=, pd2=, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=
.irp n, 2, 15, 30
gen4reg_iter_d_n \op, \d, \pd1, \pd2, \n, \pn1, \pn2, \pm1, \pm2, \pw1, \pw2
.endr
.endm
.macro gen4reg_iter op, pd1=, pd2=, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=
.irp d, 0, 7, 16, 30
gen4reg_iter_d \op, \d, \pd1, \pd2, \pn1, \pn2, \pm1, \pm2, \pw1, \pw2
.endr
.endm
# Print a 3 operand instruction
.macro gen3reg_iter op, pd1=, pd2=, pn1=, pn2=, pm1=, pm2=
.irp d, 0, 7, 16, 30
gen4reg_iter_d \op,,, \d, \pd1, \pd2, \pn1, \pn2, \pm1, \pm2
.endr
.endm
.macro gen3reg_iter_lane op, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=, x:vararg
.irp l, \x
gen4reg_iter_d \op,,,, \pn1, \pn2, \pm1, \pm2, \pw1, \pw2[\l]
.endr
.endm
# Print a 2 operand instruction
.macro gen2reg_iter op, pd1=, pd2=, pn1=, pn2=
.irp d, 0, 7, 16, 30
gen4reg_iter_d_n \op,,,,,, \d, \pd1, \pd2, \pn1, \pn2
.endr
.endm
.macro gen2reg_iter_offset op, pd1=, pd2=, r
.irp d, 0, 7, 16, 30
gen4reg_iter_d_offset \op, \d, \pd1, \pd2, \r,
.endr
.endm
# Print a 1 operand instruction
.macro gen1reg_iter op, pd1=, pd2=
.irp d, 0, 7, 16, 30
\op \pd1\d\()\pd2
.endr
.endm
.text
func:
gen3reg_iter rmif x,,,,,,
gen1reg_iter setf8 w,,
gen1reg_iter setf16 w,,
gen2reg_iter stlurb w,,[x,]
gen1reg_iter stlurb w,", [sp]"
gen3reg_iter stlurb w,, [x,,,]
gen2reg_iter_offset stlurb w,,sp
gen2reg_iter ldapurb w,,[x,]
gen1reg_iter ldapurb w,", [sp]"
gen3reg_iter ldapurb w,, [x,,,]
gen2reg_iter_offset ldapurb w,,sp
gen2reg_iter ldapursb w,,[x,]
gen1reg_iter ldapursb w,", [sp]"
gen3reg_iter ldapursb w,, [x,,,]
gen2reg_iter_offset ldapursb w,,sp
gen2reg_iter ldapursb x,,[x,]
gen1reg_iter ldapursb x,", [sp]"
gen3reg_iter ldapursb x,, [x,,,]
gen2reg_iter_offset ldapursb x,,sp
gen2reg_iter stlurh w,,[x,]
gen1reg_iter stlurh w,", [sp]"
gen3reg_iter stlurh w,, [x,,,]
gen2reg_iter_offset stlurh w,,sp
gen2reg_iter ldapurh w,,[x,]
gen1reg_iter ldapurh w,", [sp]"
gen3reg_iter ldapurh w,, [x,,,]
gen2reg_iter_offset ldapurh w,,sp
gen2reg_iter ldapursh w,,[x,]
gen1reg_iter ldapursh w,", [sp]"
gen3reg_iter ldapursh w,, [x,,,]
gen2reg_iter_offset ldapursh w,,sp
gen2reg_iter ldapursh x,,[x,]
gen1reg_iter ldapursh x,", [sp]"
gen3reg_iter ldapursh x,, [x,,,]
gen2reg_iter_offset ldapursh x,,sp
gen2reg_iter stlur w,,[x,]
gen1reg_iter stlur w,", [sp]"
gen3reg_iter stlur w,, [x,,,]
gen2reg_iter_offset stlur w,,sp
gen2reg_iter stlur x,,[x,]
gen1reg_iter stlur x,", [sp]"
gen3reg_iter stlur x,, [x,,,]
gen2reg_iter_offset stlur x,,sp
gen2reg_iter ldapur w,,[x,]
gen1reg_iter ldapur w,", [sp]"
gen3reg_iter ldapur w,, [x,,,]
gen2reg_iter_offset ldapur w,,sp
gen2reg_iter ldapur x,,[x,]
gen1reg_iter ldapur x,", [sp]"
gen3reg_iter ldapur x,, [x,,,]
gen2reg_iter_offset ldapur x,,sp
gen2reg_iter ldapursw x,,[x,]
gen1reg_iter ldapursw x,", [sp]"
gen3reg_iter ldapursw x,, [x,,,]
gen2reg_iter_offset ldapursw x,,sp

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opcodes/ChangeLog
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2017-11-16 Tamar Christina <tamar.christina@arm.com>
* aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
(rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
(sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
(fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
(ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
(ldapur, ldapursw, stlur): New.
* aarch64-dis-2.c: Regenerate.
2017-11-16 Jan Beulich <jbeulich@suse.com>
(get_valid_dis386): Never flag bad opcode when

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@ -4288,7 +4288,66 @@ struct aarch64_opcode aarch64_opcode_table[] =
DOT_INSN ("sdot", 0xe009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
DOT_INSN ("udot", 0x2f00e000, 0xbf00f000, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ),
DOT_INSN ("sdot", 0xf00e000, 0xbf00f000, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ),
/* Crypto SHA2 (optional in ARMv8.2-a). */
SHA2_INSN ("sha512h", 0xce608000, 0xffe0fc00, cryptosha2, OP3 (Fd, Fn, Vm), QL_SHA512UPT, 0),
SHA2_INSN ("sha512h2", 0xce608400, 0xffe0fc00, cryptosha2, OP3 (Fd, Fn, Vm), QL_SHA512UPT, 0),
SHA2_INSN ("sha512su0", 0xcec08000, 0xfffffc00, cryptosha2, OP2 (Vd, Vn), QL_V2SAME2D, 0),
SHA2_INSN ("sha512su1", 0xce608800, 0xffe0fc00, cryptosha2, OP3 (Vd, Vn, Vm), QL_V3SAME2D, 0),
/* Crypto SHA3 (optional in ARMv8.2-a). */
SHA3_INSN ("eor3", 0xce000000, 0xffe08000, cryptosha3, OP4 (Vd, Vn, Vm, Va), QL_V4SAME16B, 0),
SHA3_INSN ("rax1", 0xce608c00, 0xffe0fc00, cryptosha3, OP3 (Vd, Vn, Vm), QL_V3SAME2D, 0),
SHA3_INSN ("xar", 0xce800000, 0xffe00000, cryptosha3, OP4 (Vd, Vn, Vm, IMM), QL_XAR, 0),
SHA3_INSN ("bcax", 0xce200000, 0xffe08000, cryptosha3, OP4 (Vd, Vn, Vm, Va), QL_V4SAME16B, 0),
/* Crypto SM3 (optional in ARMv8.2-a). */
SM4_INSN ("sm3ss1", 0xce400000, 0xffe08000, cryptosm3, OP4 (Vd, Vn, Vm, Va), QL_V4SAME4S, 0),
SM4_INSN ("sm3tt1a", 0xce408000, 0xffe0cc00, cryptosm3, OP3 (Vd, Vn, Em), QL_SM3TT, 0),
SM4_INSN ("sm3tt1b", 0xce408400, 0xffe0cc00, cryptosm3, OP3 (Vd, Vn, Em), QL_SM3TT, 0),
SM4_INSN ("sm3tt2a", 0xce408800, 0xffe0cc00, cryptosm3, OP3 (Vd, Vn, Em), QL_SM3TT, 0),
SM4_INSN ("sm3tt2b", 0xce408c00, 0xffe0cc00, cryptosm3, OP3 (Vd, Vn, Em), QL_SM3TT, 0),
SM4_INSN ("sm3partw1", 0xce60c000, 0xffe0fc00, cryptosm3, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0),
SM4_INSN ("sm3partw2", 0xce60c400, 0xffe0fc00, cryptosm3, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0),
/* Crypto SM4 (optional in ARMv8.2-a). */
SM4_INSN ("sm4e", 0xcec08400, 0xfffffc00, cryptosm4, OP2 (Vd, Vn), QL_V2SAME4S, 0),
SM4_INSN ("sm4ekey", 0xce60c800, 0xffe0fc00, cryptosm4, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0),
/* Crypto FP16 (optional in ARMv8.2-a). */
FP16_V8_2_INSN ("fmlal", 0xe20ec00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML2S, 0),
FP16_V8_2_INSN ("fmlsl", 0xea0ec00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML2S, 0),
FP16_V8_2_INSN ("fmlal2", 0x2e20cc00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML2S, 0),
FP16_V8_2_INSN ("fmlsl2", 0x2ea0cc00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML2S, 0),
FP16_V8_2_INSN ("fmlal", 0x4e20ec00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML4S, 0),
FP16_V8_2_INSN ("fmlsl", 0x4ea0ec00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML4S, 0),
FP16_V8_2_INSN ("fmlal2", 0x6e20cc00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML4S, 0),
FP16_V8_2_INSN ("fmlsl2", 0x6ea0cc00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML4S, 0),
FP16_V8_2_INSN ("fmlal", 0xf800000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_V2FML2S, 0),
FP16_V8_2_INSN ("fmlsl", 0xf804000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_V2FML2S, 0),
FP16_V8_2_INSN ("fmlal2", 0x2f808000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_V2FML2S, 0),
FP16_V8_2_INSN ("fmlsl2", 0x2f80c000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_V2FML2S, 0),
FP16_V8_2_INSN ("fmlal", 0x4f800000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_V2FML4S, 0),
FP16_V8_2_INSN ("fmlsl", 0x4f804000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_V2FML4S, 0),
FP16_V8_2_INSN ("fmlal2", 0x6f808000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_V2FML4S, 0),
FP16_V8_2_INSN ("fmlsl2", 0x6f80c000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_V2FML4S, 0),
/* System extensions ARMv8.4-a. */
V8_4_INSN ("cfinv", 0xd500401f, 0xffffffff, ic_system, OP0 (), {}, 0),
V8_4_INSN ("rmif", 0xba000400, 0xffe07c10, ic_system, OP3 (Rn, IMM_2, MASK), QL_RMIF, 0),
V8_4_INSN ("setf8", 0x3a00080d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0),
V8_4_INSN ("setf16", 0x3a00480d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0),
/* Memory access instructions ARMv8.4-a. */
V8_4_INSN ("stlurb" , 0x19000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
V8_4_INSN ("ldapurb", 0x19400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
V8_4_INSN ("ldapursb", 0x19c00000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
V8_4_INSN ("ldapursb", 0x19800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
V8_4_INSN ("stlurh", 0x59000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
V8_4_INSN ("ldapurh", 0x59400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
V8_4_INSN ("ldapursh", 0x59c00000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
V8_4_INSN ("ldapursh", 0x59800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
V8_4_INSN ("stlur", 0x99000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
V8_4_INSN ("ldapur", 0x99400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
V8_4_INSN ("ldapursw", 0x99800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
V8_4_INSN ("stlur", 0xd9000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
V8_4_INSN ("ldapur", 0xd9400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
{0, 0, 0, 0, 0, 0, {}, {}, 0, 0, NULL},
};