sim: mcore: convert to nrun
A lot of cpu state is stored in global variables, as is memory handling. The sim_size support needs unwinding at some point. But at least this is an improvement on the status quo.
This commit is contained in:
Mike Frysinger
parent
525887679c
commit
ea6b7543b4
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@ -1,3 +1,26 @@
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2015-03-29 Mike Frysinger <vapier@gentoo.org>
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* Makefile.in (SIM_RUN_OBJS, SIM_EXTRA_CFLAGS, SIM_EXTRA_LIBS): Delete.
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(SIM_OBJS): Change to $(SIM_NEW_COMMON_OBJS).
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* interp.c: Include sim-main.h, sim-base.h, and sim-options.h.
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(word, uword): Move to sim-main.h.
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(callback, sim_kind, myname): Delete.
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(struct mcore_regset): Move pc to sim_cpu.
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(memcycles, sim_size): Mark static.
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(set_initial_gprs): Take a sim_cpu arg. Set pc via CIA_SET.
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(handle_trap1): Take a SIM_DESC arg. Get callback from it.
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(process_stub): Take a SIM_DESC arg. Pass it to handle_trap1
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(util): Take a SIM_DESC arg. Pass it to process_stub.
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(sim_resume): Get/set pc via CIA_GET/CIA_SET. Pass sd to handle_trap1
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and util.
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(sim_trace, sim_stop, sim_load, sim_set_callbacks): Delete.
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(sim_info): Get callback from SIM_DESC.
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(free_state): New cleanup function.
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(sim_open): Rewrite to use new common logic.
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(sim_create_inferior): Get sim_cpu from sd. Pass to set_initial_gprs
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and set pc via CIA_SET.
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* sim-main.h: New file.
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2015-03-29 Mike Frysinger <vapier@gentoo.org>
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* configure.ac: Call SIM_AC_OPTION_ENDIAN, SIM_AC_OPTION_ALIGNMENT,
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@ -1,7 +1,7 @@
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# Makefile template for Configure for the MCore sim library.
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# Copyright (C) 1990-2015 Free Software Foundation, Inc.
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# Written by Cygnus Solutions.
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#
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 3 of the License, or
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@ -17,11 +17,12 @@
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## COMMON_PRE_CONFIG_FRAG
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# Use the deprecated run frontend until we migrate to nrun.o
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SIM_RUN_OBJS = run.o
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SIM_EXTRA_CFLAGS = -DSIM_USE_DEPRECATED_RUN_FRONTEND
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SIM_OBJS = interp.o sim-load.o
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SIM_EXTRA_LIBS = -lm
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SIM_OBJS = \
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interp.o \
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$(SIM_NEW_COMMON_OBJS) \
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sim-cpu.o \
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sim-engine.o \
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sim-hload.o \
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sim-stop.o
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## COMMON_POST_CONFIG_FRAG
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@ -29,16 +29,15 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "libiberty.h"
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#include "gdb/remote-sim.h"
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#include "sim-main.h"
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#include "sim-base.h"
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#include "sim-options.h"
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#ifndef NUM_ELEM
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#define NUM_ELEM(A) (sizeof (A) / sizeof (A)[0])
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#endif
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typedef long int word;
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typedef unsigned long int uword;
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static int target_big_endian = 0;
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host_callback * callback;
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#define target_big_endian (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
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static unsigned long
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@ -104,6 +103,7 @@ mcore_store_unsigned_integer (unsigned char *addr, int len, unsigned long val)
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read/write functions. Keeping this data in native order improves
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the performance of the simulator. Simulation speed is deemed more
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important. */
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/* TODO: Should be moved to sim-main.h:sim_cpu. */
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/* The ordering of the mcore_regset structure is matched in the
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gdb/config/mcore/tm-mcore.h file in the REGISTER_NAMES macro. */
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@ -112,7 +112,6 @@ struct mcore_regset
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word gregs [16]; /* primary registers */
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word alt_gregs [16]; /* alt register file */
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word cregs [32]; /* control registers */
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word pc; /* the pc */
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int ticks;
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int stalls;
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int cycles;
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@ -132,10 +131,7 @@ union
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#define LAST_VALID_CREG 32 /* only 0..12 implemented */
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#define NUM_MCORE_REGS (16 + 16 + LAST_VALID_CREG + 1)
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int memcycles = 1;
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static SIM_OPEN_KIND sim_kind;
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static char * myname;
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static int memcycles = 1;
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static int issue_messages = 0;
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@ -352,10 +348,11 @@ rhat (word x)
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/* Default to a 8 Mbyte (== 2^23) memory space. */
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/* TODO: Delete all this custom memory logic and move to common sim helpers. */
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static int sim_memory_size = 23;
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#define MEM_SIZE_FLOOR 64
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void
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static void
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sim_size (int power)
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{
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sim_memory_size = power;
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@ -391,7 +388,7 @@ init_pointers (void)
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}
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static void
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set_initial_gprs (void)
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set_initial_gprs (SIM_CPU *scpu)
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{
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int i;
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long space;
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@ -400,7 +397,7 @@ set_initial_gprs (void)
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init_pointers ();
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/* Set up machine just out of reset. */
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cpu.asregs.pc = 0;
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CIA_SET (scpu, 0);
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cpu.sr = 0;
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memsize = cpu.asregs.msize / (1024 * 1024);
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@ -468,9 +465,10 @@ is_opened (int fd)
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}
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static void
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handle_trap1 (void)
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handle_trap1 (SIM_DESC sd)
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{
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unsigned long a[3];
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host_callback *callback = STATE_CALLBACK (sd);
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switch ((unsigned long) (cpu.gr [TRAPCODE]))
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{
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@ -587,7 +585,7 @@ handle_trap1 (void)
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}
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static void
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process_stub (int what)
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process_stub (SIM_DESC sd, int what)
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{
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/* These values should match those in libgloss/mcore/syscalls.s. */
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switch (what)
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@ -600,7 +598,7 @@ process_stub (int what)
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case 19: /* _lseek */
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case 43: /* _times */
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cpu.gr [TRAPCODE] = what;
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handle_trap1 ();
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handle_trap1 (sd);
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break;
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default:
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@ -611,7 +609,7 @@ process_stub (int what)
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}
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static void
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util (unsigned what)
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util (SIM_DESC sd, unsigned what)
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{
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switch (what)
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{
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@ -653,7 +651,7 @@ util (unsigned what)
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break;
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case 0xFF:
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process_stub (cpu.gr[1]);
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process_stub (sd, cpu.gr[1]);
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break;
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default:
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@ -705,6 +703,7 @@ static int tracing = 0;
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void
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sim_resume (SIM_DESC sd, int step, int siggnal)
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{
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SIM_CPU *scpu = STATE_CPU (sd, 0);
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int needfetch;
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word ibuf;
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word pc;
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@ -717,7 +716,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
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word WLhash;
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cpu.asregs.exception = step ? SIGTRAP: 0;
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pc = cpu.asregs.pc;
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pc = CIA_GET (scpu);
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/* Fetch the initial instructions that we'll decode. */
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ibuf = rlat (pc & 0xFFFFFFFC);
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@ -895,7 +894,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
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break;
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case 0x9: /* trap 1 */
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handle_trap1 ();
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handle_trap1 (sd);
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break;
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}
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break;
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@ -1492,7 +1491,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
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cpu.asregs.exception = SIGILL;
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break;
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case 0x50:
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util (inst & 0xFF);
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util (sd, inst & 0xFF);
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break;
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case 0x51: case 0x52: case 0x53:
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case 0x54: case 0x55: case 0x56: case 0x57:
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@ -1649,7 +1648,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
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while (!cpu.asregs.exception);
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/* Hide away the things we've cached while executing. */
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cpu.asregs.pc = pc;
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CIA_SET (scpu, pc);
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cpu.asregs.insts += insts; /* instructions done ... */
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cpu.asregs.cycles += insts; /* and each takes a cycle */
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cpu.asregs.cycles += bonus_cycles; /* and extra cycles for branches */
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@ -1723,19 +1722,6 @@ sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
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return 0;
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}
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int
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sim_trace (SIM_DESC sd)
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{
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tracing = 1;
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sim_resume (sd, 0, 0);
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tracing = 0;
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return 1;
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}
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void
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sim_stop_reason (SIM_DESC sd, enum sim_stop *reason, int *sigrc)
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{
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@ -1751,15 +1737,6 @@ sim_stop_reason (SIM_DESC sd, enum sim_stop *reason, int *sigrc)
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}
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}
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int
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sim_stop (SIM_DESC sd)
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{
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cpu.asregs.exception = SIGINT;
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return 1;
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}
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void
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sim_info (SIM_DESC sd, int verbose)
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{
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@ -1767,6 +1744,7 @@ sim_info (SIM_DESC sd, int verbose)
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int w, wcyc;
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#endif
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double virttime = cpu.asregs.cycles / 36.0e6;
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host_callback *callback = STATE_CALLBACK (sd);
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callback->printf_filtered (callback, "\n\n# instructions executed %10d\n",
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cpu.asregs.insts);
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@ -1817,12 +1795,71 @@ struct aout
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#define LONG(x) (((x)[0]<<24)|((x)[1]<<16)|((x)[2]<<8)|(x)[3])
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#define SHORT(x) (((x)[0]<<8)|(x)[1])
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static void
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free_state (SIM_DESC sd)
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{
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if (STATE_MODULES (sd) != NULL)
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sim_module_uninstall (sd);
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sim_cpu_free_all (sd);
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sim_state_free (sd);
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}
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SIM_DESC
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sim_open (SIM_OPEN_KIND kind, host_callback *cb, struct bfd *abfd, char **argv)
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{
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int osize = sim_memory_size;
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myname = argv[0];
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callback = cb;
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SIM_DESC sd = sim_state_alloc (kind, cb);
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int i, osize;
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SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
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/* The cpu data is kept in a separately allocated chunk of memory. */
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if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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/* getopt will print the error message so we just have to exit if this fails.
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FIXME: Hmmm... in the case of gdb we need getopt to call
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print_filtered. */
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if (sim_parse_args (sd, argv) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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/* Check for/establish the a reference program image. */
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if (sim_analyze_program (sd,
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(STATE_PROG_ARGV (sd) != NULL
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? *STATE_PROG_ARGV (sd)
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: NULL), abfd) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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/* Configure/verify the target byte order and other runtime
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configuration options. */
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if (sim_config (sd) != SIM_RC_OK)
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{
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sim_module_uninstall (sd);
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return 0;
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}
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if (sim_post_argv_init (sd) != SIM_RC_OK)
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{
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/* Uninstall the modules to avoid memory leaks,
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file descriptor leaks, etc. */
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sim_module_uninstall (sd);
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return 0;
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}
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osize = sim_memory_size;
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if (kind == SIM_OPEN_STANDALONE)
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issue_messages = 1;
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@ -1831,10 +1868,14 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb, struct bfd *abfd, char **argv)
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sim_size (1); /* small */
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sim_size (osize); /* and back again */
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set_initial_gprs (); /* Reset the GPR registers. */
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/* CPU specific initialization. */
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for (i = 0; i < MAX_NR_PROCESSORS; ++i)
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{
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SIM_CPU *cpu = STATE_CPU (sd, i);
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set_initial_gprs (cpu); /* Reset the GPR registers. */
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}
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/* Fudge our descriptor for now. */
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return (SIM_DESC) 1;
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return sd;
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}
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void
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@ -1843,62 +1884,10 @@ sim_close (SIM_DESC sd, int quitting)
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/* nothing to do */
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}
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SIM_RC
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sim_load (SIM_DESC sd, const char *prog, bfd *abfd, int from_tty)
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{
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/* Do the right thing for ELF executables; this turns out to be
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just about the right thing for any object format that:
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- we crack using BFD routines
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- follows the traditional UNIX text/data/bss layout
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- calls the bss section ".bss". */
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extern bfd * sim_load_file (); /* ??? Don't know where this should live. */
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bfd * prog_bfd;
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{
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bfd * handle;
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handle = bfd_openr (prog, 0); /* could be "mcore" */
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if (!handle)
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{
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printf("``%s'' could not be opened.\n", prog);
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return SIM_RC_FAIL;
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}
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/* Makes sure that we have an object file, also cleans gets the
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section headers in place. */
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if (!bfd_check_format (handle, bfd_object))
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{
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/* wasn't an object file */
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bfd_close (handle);
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printf ("``%s'' is not appropriate object file.\n", prog);
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return SIM_RC_FAIL;
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}
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/* Clean up after ourselves. */
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bfd_close (handle);
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/* XXX: do we need to free the s_bss and handle structures? */
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}
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/* from sh -- dac */
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prog_bfd = sim_load_file (sd, myname, callback, prog, abfd,
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sim_kind == SIM_OPEN_DEBUG,
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0, sim_write);
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if (prog_bfd == NULL)
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return SIM_RC_FAIL;
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target_big_endian = bfd_big_endian (prog_bfd);
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if (abfd == NULL)
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bfd_close (prog_bfd);
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return SIM_RC_OK;
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}
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SIM_RC
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sim_create_inferior (SIM_DESC sd, struct bfd *prog_bfd, char **argv, char **env)
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{
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SIM_CPU *scpu = STATE_CPU (sd, 0);
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char ** avp;
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int nargs = 0;
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int nenv = 0;
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@ -1912,11 +1901,11 @@ sim_create_inferior (SIM_DESC sd, struct bfd *prog_bfd, char **argv, char **env)
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/* Set the initial register set. */
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l = issue_messages;
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issue_messages = 0;
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set_initial_gprs ();
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set_initial_gprs (scpu);
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issue_messages = l;
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hi_stack = cpu.asregs.msize - 4;
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cpu.asregs.pc = bfd_get_start_address (prog_bfd);
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CIA_SET (scpu, bfd_get_start_address (prog_bfd));
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/* Calculate the argument and environment strings. */
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s_length = 0;
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@ -2085,9 +2074,3 @@ sim_do_command (SIM_DESC sd, const char *cmd)
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fprintf (stderr, " verbose\n");
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}
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}
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void
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sim_set_callbacks (host_callback *ptr)
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{
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callback = ptr;
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}
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|
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@ -0,0 +1,56 @@
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/* Simulator for Motorola's MCore processor
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Copyright (C) 2009-2015 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GDB, the GNU debugger.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>. */
|
||||
|
||||
#ifndef SIM_MAIN_H
|
||||
#define SIM_MAIN_H
|
||||
|
||||
#include "sim-basics.h"
|
||||
|
||||
typedef address_word sim_cia;
|
||||
typedef long int word;
|
||||
typedef unsigned long int uword;
|
||||
|
||||
typedef struct _sim_cpu SIM_CPU;
|
||||
|
||||
#include "sim-base.h"
|
||||
#include "bfd.h"
|
||||
|
||||
#define CIA_GET(cpu) (cpu)->pc
|
||||
#define CIA_SET(cpu,val) (cpu)->pc = (val)
|
||||
|
||||
struct _sim_cpu {
|
||||
|
||||
word pc;
|
||||
|
||||
sim_cpu_base base;
|
||||
};
|
||||
|
||||
struct sim_state {
|
||||
|
||||
sim_cpu *cpu[MAX_NR_PROCESSORS];
|
||||
#if (WITH_SMP)
|
||||
#define STATE_CPU(sd,n) ((sd)->cpu[n])
|
||||
#else
|
||||
#define STATE_CPU(sd,n) ((sd)->cpu[0])
|
||||
#endif
|
||||
|
||||
sim_state_base base;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue