diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index e3cba76069..3092e22320 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
+
+	* aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
+	local variable to `index_regno'.
+
 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 
 	* arc-tbl.h: Removed any "inv.+" instructions from the table.
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index d8c5fa7aa5..188006eb33 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -1321,14 +1321,14 @@ aarch64_ext_sve_addr_rr_lsl (const aarch64_operand *self,
 			     aarch64_opnd_info *info, aarch64_insn code,
 			     const aarch64_inst *inst ATTRIBUTE_UNUSED)
 {
-  int index;
+  int index_regno;
 
-  index = extract_field (self->fields[1], code, 0);
-  if (index == 31 && (self->flags & OPD_F_NO_ZR) != 0)
+  index_regno = extract_field (self->fields[1], code, 0);
+  if (index_regno == 31 && (self->flags & OPD_F_NO_ZR) != 0)
     return 0;
 
   info->addr.base_regno = extract_field (self->fields[0], code, 0);
-  info->addr.offset.regno = index;
+  info->addr.offset.regno = index_regno;
   info->addr.offset.is_reg = TRUE;
   info->addr.writeback = FALSE;
   info->addr.preind = TRUE;