Wed Jun 3 18:21:56 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
* config/tc-i386.c (SCALE1_WHEN_NO_INDEX): Define. (ebp, esp): Remove static variables. (MATCH): Remove test for InOutPortReg. (i386_operand): Properly handle InOutPortReg here instead. Disallows `inb (%dx,2)', `inb %es:(%dx)' and `mov (%dx),%ax' (md_assemble): Simplify and correct modrm and sib generation. (i386_operand): Add warning for scale without index. Rewrite checks for valid base/index combinations.
This commit is contained in:
Ian Lance Taylor
parent
2edb8195a9
commit
ec1e6bb850
@ -1,3 +1,14 @@
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Wed Jun 3 18:21:56 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
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* config/tc-i386.c (SCALE1_WHEN_NO_INDEX): Define.
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(ebp, esp): Remove static variables.
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(MATCH): Remove test for InOutPortReg.
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(i386_operand): Properly handle InOutPortReg here instead.
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Disallows `inb (%dx,2)', `inb %es:(%dx)' and `mov (%dx),%ax'
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(md_assemble): Simplify and correct modrm and sib generation.
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(i386_operand): Add warning for scale without index.
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Rewrite checks for valid base/index combinations.
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Wed Jun 3 15:09:10 1998 Ian Lance Taylor <ian@cygnus.com>
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* configure.in: Recognize m5200 as a cpu_type of m68k.
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@ -38,6 +38,14 @@
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#define TC_RELOC(X,Y) (Y)
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#endif
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#ifndef SCALE1_WHEN_NO_INDEX
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/* Specifying a scale factor besides 1 when there is no index is
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futile. eg. `mov (%ebx,2),%al' does exactly the same as
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`mov (%ebx),%al'. To slavishly follow what the programmer
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specified, set SCALE1_WHEN_NO_INDEX to 0. */
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#define SCALE1_WHEN_NO_INDEX 1
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#endif
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static unsigned long mode_from_disp_size PARAMS ((unsigned long));
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static int fits_in_signed_byte PARAMS ((long));
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static int fits_in_unsigned_byte PARAMS ((long));
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@ -102,10 +110,9 @@ struct _i386_insn
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const seg_entry *seg[2]; /* segments for memory operands (if given) */
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/* PREFIX holds all the given prefix opcodes (usually null).
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PREFIXES is the size of PREFIX. */
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/* richfix: really unsigned? */
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unsigned char prefix[MAX_PREFIXES];
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PREFIXES is the number of prefix opcodes. */
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unsigned int prefixes;
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unsigned char prefix[MAX_PREFIXES];
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/* Wait prefix needs to come before any other prefixes, so handle
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it specially. wait_prefix will hold the opcode modifier flag
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@ -189,9 +196,6 @@ static templates *current_templates;
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/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
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static expressionS disp_expressions[2], im_expressions[2];
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/* Pointers to ebp & esp entries in reg_hash hash table. */
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static reg_entry *ebp, *esp;
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static int this_operand; /* current operand we are working on */
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static int flag_do_long_jump; /* FIXME what does this do? */
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@ -609,9 +613,6 @@ md_begin ()
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}
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}
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esp = (reg_entry *) hash_find (reg_hash, "esp");
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ebp = (reg_entry *) hash_find (reg_hash, "ebp");
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/* initialize reg_hash hash table */
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prefix_hash = hash_new ();
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{
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@ -967,7 +968,6 @@ md_assemble (line)
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else
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{
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/* This opcode's got a prefix. */
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unsigned int q;
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prefix_entry *prefix;
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if (l == token_start)
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@ -1143,11 +1143,9 @@ md_assemble (line)
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with the template operand types. */
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#define MATCH(overlap,given_type) \
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(overlap && \
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(((overlap & (JumpAbsolute|BaseIndex|Mem8)) \
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== (given_type & (JumpAbsolute|BaseIndex|Mem8))) \
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|| (overlap == InOutPortReg)))
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(overlap \
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&& ((overlap & (JumpAbsolute|BaseIndex|Mem8)) \
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== (given_type & (JumpAbsolute|BaseIndex|Mem8))))
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/* If m0 and m1 are register matches they must be consistent
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with the expected operand types t0 and t1.
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@ -1524,85 +1522,72 @@ md_assemble (line)
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? 0
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: (i.types[1] & Mem) ? 1 : 2);
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/* Encode memory operand into modrm byte and base index
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byte. */
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default_seg = &ds;
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if (i.base_reg == esp && !i.index_reg)
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if (! i.base_reg)
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{
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/* <disp>(%esp) becomes two byte modrm with no index
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register. */
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i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
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i.rm.mode = mode_from_disp_size (i.types[op]);
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i.bi.base = ESP_REG_NUM;
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i.bi.index = NO_INDEX_REGISTER;
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i.bi.scale = 0; /* Must be zero! */
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}
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else if (i.base_reg == ebp && !i.index_reg)
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{
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if (!(i.types[op] & Disp))
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i.rm.mode = 0;
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if (! i.disp_operands)
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fake_zero_displacement = 1;
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if (! i.index_reg)
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{
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/* Must fake a zero byte displacement. There is
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no direct way to code '(%ebp)' directly. */
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fake_zero_displacement = 1;
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/* fake_zero_displacement code does not set this. */
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i.types[op] |= Disp8;
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}
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i.rm.mode = mode_from_disp_size (i.types[op]);
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i.rm.regmem = EBP_REG_NUM;
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}
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else if (!i.base_reg && (i.types[op] & BaseIndex))
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{
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/* There are three cases here.
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Case 1: '<32bit disp>(,1)' -- indirect absolute.
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(Same as cases 2 & 3 with NO index register)
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Case 2: <32bit disp> (,<index>) -- no base register with disp
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Case 3: (, <index>) --- no base register;
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no disp (must add 32bit 0 disp). */
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i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
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i.rm.mode = 0; /* 32bit mode */
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i.bi.base = NO_BASE_REGISTER;
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i.types[op] &= ~Disp;
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i.types[op] |= Disp32; /* Must be 32bit! */
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if (i.index_reg)
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{ /* case 2 or case 3 */
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i.bi.index = i.index_reg->reg_num;
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i.bi.scale = i.log2_scale_factor;
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if (i.disp_operands == 0)
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fake_zero_displacement = 1; /* case 3 */
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/* Operand is just <disp> */
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i.rm.regmem = NO_BASE_REGISTER;
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i.types[op] &= ~Disp;
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i.types[op] |= Disp32;
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}
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else
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{
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i.bi.index = NO_INDEX_REGISTER;
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i.bi.scale = 0;
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i.bi.index = i.index_reg->reg_num;
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i.bi.base = NO_BASE_REGISTER;
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i.bi.scale = i.log2_scale_factor;
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i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
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i.types[op] &= ~Disp;
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i.types[op] |= Disp32; /* Must be 32 bit */
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}
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}
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else if (i.disp_operands && !i.base_reg && !i.index_reg)
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else /* i.base_reg */
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{
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/* Operand is just <32bit disp> */
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i.rm.regmem = EBP_REG_NUM;
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i.rm.mode = 0;
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i.types[op] &= ~Disp;
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i.types[op] |= Disp32;
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}
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else
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{
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/* It's not a special case; rev'em up. */
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i.rm.regmem = i.base_reg->reg_num;
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i.rm.mode = mode_from_disp_size (i.types[op]);
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if (i.index_reg)
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i.bi.base = i.base_reg->reg_num;
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if (i.base_reg->reg_num == EBP_REG_NUM)
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{
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i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
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i.bi.base = i.base_reg->reg_num;
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i.bi.index = i.index_reg->reg_num;
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i.bi.scale = i.log2_scale_factor;
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if (i.base_reg == ebp && i.disp_operands == 0)
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{ /* pace */
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default_seg = &ss;
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if (i.disp_operands == 0)
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{
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fake_zero_displacement = 1;
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i.types[op] |= Disp8;
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i.rm.mode = mode_from_disp_size (i.types[op]);
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}
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}
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else if (i.base_reg->reg_num == ESP_REG_NUM)
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{
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default_seg = &ss;
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}
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i.bi.scale = i.log2_scale_factor;
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if (! i.index_reg)
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{
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/* <disp>(%esp) becomes two byte modrm
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with no index register. We've already
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stored the code for esp in i.rm.regmem
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ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
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base register besides %esp will not use
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the extra modrm byte. */
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i.bi.index = NO_INDEX_REGISTER;
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#if ! SCALE1_WHEN_NO_INDEX
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/* Another case where we force the second
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modrm byte. */
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if (i.log2_scale_factor)
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i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
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#endif
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}
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else
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{
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i.bi.index = i.index_reg->reg_num;
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i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
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}
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i.rm.mode = mode_from_disp_size (i.types[op]);
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}
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if (fake_zero_displacement)
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{
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/* Fakes a zero displacement assuming that i.types[op]
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@ -1614,24 +1599,6 @@ md_assemble (line)
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exp->X_add_symbol = (symbolS *) 0;
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exp->X_op_symbol = (symbolS *) 0;
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}
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/* Find the default segment for the memory operand.
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Used to optimize out explicit segment specifications. */
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if (i.seg[0])
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{
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unsigned int seg_index;
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if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING)
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{
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seg_index = (i.rm.mode << 3) | i.bi.base;
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default_seg = two_byte_segment_defaults[seg_index];
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}
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else
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{
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seg_index = (i.rm.mode << 3) | i.rm.regmem;
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default_seg = one_byte_segment_defaults[seg_index];
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}
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}
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}
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/* Fill in i.rm.reg or i.rm.regmem field with register
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@ -1984,7 +1951,8 @@ md_assemble (line)
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1);
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/* If i.rm.regmem == ESP (4) && i.rm.mode != Mode 3 (Register mode)
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==> need second modrm byte. */
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if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING && i.rm.mode != 3)
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if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
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&& i.rm.mode != 3)
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{
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p = frag_more (1);
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insn_size += 1;
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@ -2202,7 +2170,7 @@ i386_operand (operand_string)
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}
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goto do_memory_reference;
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}
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i.types[this_operand] |= r->reg_type;
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i.types[this_operand] |= r->reg_type & ~BaseIndex;
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i.regs[this_operand] = r;
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i.reg_operands++;
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}
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@ -2292,7 +2260,7 @@ i386_operand (operand_string)
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{
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/* This is a memory reference of some sort. */
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register char *base_string;
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unsigned int found_base_index_form;
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int found_base_index_form;
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do_memory_reference:
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if ((i.mem_operands == 1
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@ -2303,7 +2271,6 @@ i386_operand (operand_string)
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current_templates->start->name);
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return 0;
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}
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i.mem_operands++;
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/* Determine type of memory operand from opcode_suffix;
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no opcode suffix implies general memory references. */
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@ -2453,6 +2420,14 @@ i386_operand (operand_string)
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as_bad (_("expecting scale factor of 1, 2, 4, 8; got %d"), num);
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return 0;
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}
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if (num != 1 && ! i.index_reg)
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{
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as_warn (_("scale factor of %d without an index register"),
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num);
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#if SCALE1_WHEN_NO_INDEX
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i.log2_scale_factor = 0;
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#endif
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}
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}
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else
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{
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@ -2588,35 +2563,28 @@ i386_operand (operand_string)
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}
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}
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/* Make sure the memory operand we've been dealt is valid. */
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if (i.base_reg && i.index_reg &&
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!(i.base_reg->reg_type & i.index_reg->reg_type & Reg))
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/* Special case for (%dx) while doing input/output op. */
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if (i.base_reg &&
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i.base_reg->reg_type == (Reg16 | InOutPortReg) &&
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i.index_reg == 0 &&
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i.log2_scale_factor == 0 &&
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i.seg[i.mem_operands] == 0)
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{
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as_bad (_("register size mismatch in (base,index,scale) expression"));
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return 0;
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}
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/*
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* special case for (%dx) while doing input/output op
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*/
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if ((i.base_reg &&
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(i.base_reg->reg_type == (Reg16 | InOutPortReg)) &&
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(i.index_reg == 0)))
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{
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i.types[this_operand] |= InOutPortReg;
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i.types[this_operand] = InOutPortReg;
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return 1;
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}
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if ((i.base_reg && (i.base_reg->reg_type & Reg32) == 0) ||
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(i.index_reg && (i.index_reg->reg_type & Reg32) == 0))
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/* Make sure the memory operand we've been dealt is valid. */
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if ((i.base_reg && (i.base_reg->reg_type & BaseIndex) == 0)
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|| (i.index_reg && ((i.index_reg->reg_type & BaseIndex) == 0
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|| i.index_reg->reg_num == ESP_REG_NUM))
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|| (i.base_reg && i.index_reg
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&& (i.base_reg->reg_type & i.index_reg->reg_type & Reg) == 0))
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{
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as_bad (_("base/index register must be 32 bit register"));
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return 0;
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}
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if (i.index_reg && i.index_reg == esp)
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{
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as_bad (_("`%%s' may not be used as an index register"),
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esp->reg_name);
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as_bad (_("`%s' is not a valid base/index expression"),
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operand_string);
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return 0;
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}
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i.mem_operands++;
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}
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else
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{ /* it's not a memory operand; argh! */
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@ -2867,7 +2835,11 @@ md_apply_fix3 (fixP, valp, seg)
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#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
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if (OUTPUT_FLAVOR == bfd_target_elf_flavour
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&& (S_GET_SEGMENT (fixP->fx_addsy) == seg
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|| (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0))
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|| (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
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&& ! S_IS_EXTERNAL (fixP->fx_addsy)
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&& ! S_IS_WEAK (fixP->fx_addsy)
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&& S_IS_DEFINED (fixP->fx_addsy)
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&& ! S_IS_COMMON (fixP->fx_addsy))
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{
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/* Yes, we add the values in twice. This is because
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bfd_perform_relocation subtracts them out again. I think
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