* arm-tdep.c (thumb_expand_immediate): New function.
(thumb_instruction_changes_pc): Likewise. (thumb2_instruction_changes_pc): Likewise. (thumb_analyze_prologue): Handle 32-bit Thumb instructions during prologue parsing. Improved support for optimized code. (thumb_scan_prologue): Do not reply on line-number information, use same heuristics as arm_scan_prologue insead. (skip_prologue_function): Accept functions "__tls_get_addr" and "__aeabi_read_tp".
This commit is contained in:
Ulrich Weigand
parent
4024ca9964
commit
ec3d575a7a
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@ -1,3 +1,15 @@
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2010-10-08 Ulrich Weigand <uweigand@de.ibm.com>
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* arm-tdep.c (thumb_expand_immediate): New function.
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(thumb_instruction_changes_pc): Likewise.
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(thumb2_instruction_changes_pc): Likewise.
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(thumb_analyze_prologue): Handle 32-bit Thumb instructions during
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prologue parsing. Improved support for optimized code.
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(thumb_scan_prologue): Do not reply on line-number information,
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use same heuristics as arm_scan_prologue insead.
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(skip_prologue_function): Accept functions
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"__tls_get_addr" and "__aeabi_read_tp".
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2010-10-08 Ulrich Weigand <uweigand@de.ibm.com>
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Daniel Jacobowitz <dan@codesourcery.com>
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440
gdb/arm-tdep.c
440
gdb/arm-tdep.c
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@ -476,6 +476,12 @@ skip_prologue_function (CORE_ADDR pc)
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if (strncmp (name, "__aeabi_d2f", strlen ("__aeabi_d2f")) == 0)
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return 1;
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/* Internal functions related to thread-local storage. */
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if (strncmp (name, "__tls_get_addr", strlen ("__tls_get_addr")) == 0)
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return 1;
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if (strncmp (name, "__aeabi_read_tp", strlen ("__aeabi_read_tp")) == 0)
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return 1;
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return 0;
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}
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@ -488,6 +494,149 @@ skip_prologue_function (CORE_ADDR pc)
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#define BranchDest(addr,instr) \
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((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
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/* Decode immediate value; implements ThumbExpandImmediate pseudo-op. */
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static unsigned int
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thumb_expand_immediate (unsigned int imm)
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{
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unsigned int count = imm >> 7;
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if (count < 8)
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switch (count / 2)
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{
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case 0:
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return imm & 0xff;
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case 1:
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return (imm & 0xff) | ((imm & 0xff) << 16);
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case 2:
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return ((imm & 0xff) << 8) | ((imm & 0xff) << 24);
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case 3:
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return (imm & 0xff) | ((imm & 0xff) << 8)
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| ((imm & 0xff) << 16) | ((imm & 0xff) << 24);
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}
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return (0x80 | (imm & 0x7f)) << (32 - count);
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}
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/* Return 1 if the 16-bit Thumb instruction INST might change
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control flow, 0 otherwise. */
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static int
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thumb_instruction_changes_pc (unsigned short inst)
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{
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if ((inst & 0xff00) == 0xbd00) /* pop {rlist, pc} */
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return 1;
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if ((inst & 0xf000) == 0xd000) /* conditional branch */
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return 1;
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if ((inst & 0xf800) == 0xe000) /* unconditional branch */
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return 1;
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if ((inst & 0xff00) == 0x4700) /* bx REG, blx REG */
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return 1;
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if ((inst & 0xf500) == 0xb100) /* CBNZ or CBZ. */
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return 1;
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return 0;
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}
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/* Return 1 if the 32-bit Thumb instruction in INST1 and INST2
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might change control flow, 0 otherwise. */
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static int
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thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2)
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{
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if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
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{
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/* Branches and miscellaneous control instructions. */
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if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
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{
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/* B, BL, BLX. */
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return 1;
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}
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else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
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{
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/* SUBS PC, LR, #imm8. */
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return 1;
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}
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else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
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{
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/* Conditional branch. */
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return 1;
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}
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return 0;
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}
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if ((inst1 & 0xfe50) == 0xe810)
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{
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/* Load multiple or RFE. */
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if (bit (inst1, 7) && !bit (inst1, 8))
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{
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/* LDMIA or POP */
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if (bit (inst2, 15))
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return 1;
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}
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else if (!bit (inst1, 7) && bit (inst1, 8))
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{
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/* LDMDB */
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if (bit (inst2, 15))
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return 1;
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}
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else if (bit (inst1, 7) && bit (inst1, 8))
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{
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/* RFEIA */
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return 1;
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}
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else if (!bit (inst1, 7) && !bit (inst1, 8))
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{
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/* RFEDB */
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return 1;
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}
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return 0;
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}
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if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
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{
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/* MOV PC or MOVS PC. */
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return 1;
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}
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if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
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{
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/* LDR PC. */
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if (bits (inst1, 0, 3) == 15)
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return 1;
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if (bit (inst1, 7))
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return 1;
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if (bit (inst2, 11))
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return 1;
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if ((inst2 & 0x0fc0) == 0x0000)
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return 1;
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return 0;
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}
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if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
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{
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/* TBB. */
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return 1;
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}
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if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
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{
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/* TBH. */
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return 1;
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}
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return 0;
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}
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/* Analyze a Thumb prologue, looking for a recognizable stack frame
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and frame pointer. Scan until we encounter a store that could
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clobber the stack frame unexpectedly, or an unknown instruction.
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@ -506,6 +655,7 @@ thumb_analyze_prologue (struct gdbarch *gdbarch,
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struct pv_area *stack;
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struct cleanup *back_to;
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CORE_ADDR offset;
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CORE_ADDR unrecognized_pc = 0;
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for (i = 0; i < 16; i++)
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regs[i] = pv_register (i, 0);
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@ -643,9 +793,8 @@ thumb_analyze_prologue (struct gdbarch *gdbarch,
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constant = read_memory_unsigned_integer (loc, 4, byte_order);
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regs[bits (insn, 8, 10)] = pv_constant (constant);
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}
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else if ((insn & 0xe000) == 0xe000 && cache == NULL)
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else if ((insn & 0xe000) == 0xe000)
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{
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/* Only recognize 32-bit instructions for prologue skipping. */
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unsigned short inst2;
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inst2 = read_memory_unsigned_integer (start + 2, 2,
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@ -675,58 +824,256 @@ thumb_analyze_prologue (struct gdbarch *gdbarch,
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if (!skip_prologue_function (nextpc))
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break;
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}
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else if ((insn & 0xfe50) == 0xe800 /* stm{db,ia} Rn[!], { registers } */
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else if ((insn & 0xffd0) == 0xe900 /* stmdb Rn{!}, { registers } */
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&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
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;
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else if ((insn & 0xfe50) == 0xe840 /* strd Rt, Rt2, [Rn, #imm] */
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{
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pv_t addr = regs[bits (insn, 0, 3)];
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int regno;
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if (pv_area_store_would_trash (stack, addr))
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break;
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/* Calculate offsets of saved registers. */
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for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
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if (inst2 & (1 << regno))
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{
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addr = pv_add_constant (addr, -4);
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pv_area_store (stack, addr, 4, regs[regno]);
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}
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if (insn & 0x0020)
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regs[bits (insn, 0, 3)] = addr;
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}
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else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2, [Rn, #+/-imm]{!} */
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&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
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{
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int regno1 = bits (inst2, 12, 15);
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int regno2 = bits (inst2, 8, 11);
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pv_t addr = regs[bits (insn, 0, 3)];
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offset = inst2 & 0xff;
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if (insn & 0x0080)
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addr = pv_add_constant (addr, offset);
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else
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addr = pv_add_constant (addr, -offset);
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if (pv_area_store_would_trash (stack, addr))
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break;
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pv_area_store (stack, addr, 4, regs[regno1]);
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pv_area_store (stack, pv_add_constant (addr, 4),
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4, regs[regno2]);
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if (insn & 0x0020)
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regs[bits (insn, 0, 3)] = addr;
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}
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else if ((insn & 0xfff0) == 0xf8c0 /* str Rt,[Rn,+/-#imm]{!} */
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&& (inst2 & 0x0c00) == 0x0c00
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&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
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{
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int regno = bits (inst2, 12, 15);
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pv_t addr = regs[bits (insn, 0, 3)];
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offset = inst2 & 0xff;
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if (inst2 & 0x0200)
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addr = pv_add_constant (addr, offset);
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else
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addr = pv_add_constant (addr, -offset);
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if (pv_area_store_would_trash (stack, addr))
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break;
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pv_area_store (stack, addr, 4, regs[regno]);
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if (inst2 & 0x0100)
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regs[bits (insn, 0, 3)] = addr;
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}
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else if ((insn & 0xfff0) == 0xf8c0 /* str.w Rt,[Rn,#imm] */
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&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
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{
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int regno = bits (inst2, 12, 15);
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pv_t addr;
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offset = inst2 & 0xfff;
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addr = pv_add_constant (regs[bits (insn, 0, 3)], offset);
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if (pv_area_store_would_trash (stack, addr))
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break;
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pv_area_store (stack, addr, 4, regs[regno]);
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}
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else if ((insn & 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
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&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
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/* Ignore stores of argument registers to the stack. */
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;
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else if ((insn & 0xffd0) == 0xf800 /* str{bh} Rt,[Rn,#+/-imm] */
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&& (inst2 & 0x0d00) == 0x0c00
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&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
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/* Ignore stores of argument registers to the stack. */
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;
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else if ((insn & 0xffd0) == 0xe890 /* ldmia Rn[!], { registers } */
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&& (inst2 & 0x8000) == 0x0000
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&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
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&& (inst2 & 0x8000) == 0x0000
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&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
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/* Ignore block loads from the stack, potentially copying
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parameters from memory. */
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;
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else if ((insn & 0xffb0) == 0xe950 /* ldrd Rt, Rt2, [Rn, #+/-imm] */
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&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
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/* Similarly ignore dual loads from the stack. */
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;
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else if ((insn & 0xfff0) == 0xf850 /* ldr Rt,[Rn,#+/-imm] */
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&& (inst2 & 0x0d00) == 0x0c00
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&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
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/* Similarly ignore single loads from the stack. */
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;
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else if ((insn & 0xfff0) == 0xf8d0 /* ldr.w Rt,[Rn,#imm] */
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&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
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/* Similarly ignore single loads from the stack. */
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;
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else if ((insn & 0xfbf0) == 0xf100 /* add.w Rd, Rn, #imm */
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&& (inst2 & 0x8000) == 0x0000)
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/* Since we only recognize this for prologue skipping, do not bother
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to compute the constant. */
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regs[bits (inst2, 8, 11)] = regs[bits (insn, 0, 3)];
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else if ((insn & 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm12 */
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{
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unsigned int imm = ((bits (insn, 10, 10) << 11)
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| (bits (inst2, 12, 14) << 8)
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| bits (inst2, 0, 7));
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regs[bits (inst2, 8, 11)]
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= pv_add_constant (regs[bits (insn, 0, 3)],
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thumb_expand_immediate (imm));
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}
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else if ((insn & 0xfbf0) == 0xf200 /* addw Rd, Rn, #imm */
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&& (inst2 & 0x8000) == 0x0000)
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/* Since we only recognize this for prologue skipping, do not bother
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to compute the constant. */
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regs[bits (inst2, 8, 11)] = regs[bits (insn, 0, 3)];
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else if ((insn & 0xfbf0) == 0xf2a0 /* sub.w Rd, Rn, #imm8 */
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{
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unsigned int imm = ((bits (insn, 10, 10) << 11)
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| (bits (inst2, 12, 14) << 8)
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| bits (inst2, 0, 7));
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regs[bits (inst2, 8, 11)]
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= pv_add_constant (regs[bits (insn, 0, 3)], imm);
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}
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else if ((insn & 0xfbf0) == 0xf1a0 /* sub.w Rd, Rn, #imm */
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&& (inst2 & 0x8000) == 0x0000)
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/* Since we only recognize this for prologue skipping, do not bother
|
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to compute the constant. */
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regs[bits (inst2, 8, 11)] = regs[bits (insn, 0, 3)];
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else if ((insn & 0xff50) == 0xf850 /* ldr.w Rd, [Rn, #imm]{!} */
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&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
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;
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else if ((insn & 0xff50) == 0xe950 /* ldrd Rt, Rt2, [Rn, #imm]{!} */
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&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
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;
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else if ((insn & 0xff50) == 0xf800 /* strb.w or strh.w */
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&& pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
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;
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{
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unsigned int imm = ((bits (insn, 10, 10) << 11)
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| (bits (inst2, 12, 14) << 8)
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| bits (inst2, 0, 7));
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regs[bits (inst2, 8, 11)]
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= pv_add_constant (regs[bits (insn, 0, 3)],
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- (CORE_ADDR) thumb_expand_immediate (imm));
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}
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else if ((insn & 0xfbf0) == 0xf2a0 /* subw Rd, Rn, #imm */
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&& (inst2 & 0x8000) == 0x0000)
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{
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unsigned int imm = ((bits (insn, 10, 10) << 11)
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| (bits (inst2, 12, 14) << 8)
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| bits (inst2, 0, 7));
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regs[bits (inst2, 8, 11)]
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= pv_add_constant (regs[bits (insn, 0, 3)], - (CORE_ADDR) imm);
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}
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else if ((insn & 0xfbff) == 0xf04f) /* mov.w Rd, #const */
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{
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unsigned int imm = ((bits (insn, 10, 10) << 11)
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| (bits (inst2, 12, 14) << 8)
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| bits (inst2, 0, 7));
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regs[bits (inst2, 8, 11)]
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= pv_constant (thumb_expand_immediate (imm));
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}
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||||
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else if ((insn & 0xfbf0) == 0xf240) /* movw Rd, #const */
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{
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unsigned int imm = ((bits (insn, 0, 3) << 12)
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| (bits (insn, 10, 10) << 11)
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| (bits (inst2, 12, 14) << 8)
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| bits (inst2, 0, 7));
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regs[bits (inst2, 8, 11)] = pv_constant (imm);
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}
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else if (insn == 0xea5f /* mov.w Rd,Rm */
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&& (inst2 & 0xf0f0) == 0)
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||||
{
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||||
int dst_reg = (inst2 & 0x0f00) >> 8;
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int src_reg = inst2 & 0xf;
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regs[dst_reg] = regs[src_reg];
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||||
}
|
||||
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else if ((insn & 0xff7f) == 0xf85f) /* ldr.w Rt,<label> */
|
||||
{
|
||||
/* Constant pool loads. */
|
||||
unsigned int constant;
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||||
CORE_ADDR loc;
|
||||
|
||||
offset = bits (insn, 0, 11);
|
||||
if (insn & 0x0080)
|
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loc = start + 4 + offset;
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||||
else
|
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loc = start + 4 - offset;
|
||||
|
||||
constant = read_memory_unsigned_integer (loc, 4, byte_order);
|
||||
regs[bits (inst2, 12, 15)] = pv_constant (constant);
|
||||
}
|
||||
|
||||
else if ((insn & 0xff7f) == 0xe95f) /* ldrd Rt,Rt2,<label> */
|
||||
{
|
||||
/* Constant pool loads. */
|
||||
unsigned int constant;
|
||||
CORE_ADDR loc;
|
||||
|
||||
offset = bits (insn, 0, 7) << 2;
|
||||
if (insn & 0x0080)
|
||||
loc = start + 4 + offset;
|
||||
else
|
||||
loc = start + 4 - offset;
|
||||
|
||||
constant = read_memory_unsigned_integer (loc, 4, byte_order);
|
||||
regs[bits (inst2, 12, 15)] = pv_constant (constant);
|
||||
|
||||
constant = read_memory_unsigned_integer (loc + 4, 4, byte_order);
|
||||
regs[bits (inst2, 8, 11)] = pv_constant (constant);
|
||||
}
|
||||
|
||||
else if (thumb2_instruction_changes_pc (insn, inst2))
|
||||
{
|
||||
/* Don't scan past anything that might change control flow. */
|
||||
break;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* We don't know what this instruction is. We're finished
|
||||
scanning. NOTE: Recognizing more safe-to-ignore
|
||||
instructions here will improve support for optimized
|
||||
code. */
|
||||
break;
|
||||
/* The optimizer might shove anything into the prologue,
|
||||
so we just skip what we don't recognize. */
|
||||
unrecognized_pc = start;
|
||||
}
|
||||
|
||||
start += 2;
|
||||
}
|
||||
else if (thumb_instruction_changes_pc (insn))
|
||||
{
|
||||
/* Don't scan past anything that might change control flow. */
|
||||
break;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* We don't know what this instruction is. We're finished
|
||||
scanning. NOTE: Recognizing more safe-to-ignore
|
||||
instructions here will improve support for optimized
|
||||
code. */
|
||||
break;
|
||||
/* The optimizer might shove anything into the prologue,
|
||||
so we just skip what we don't recognize. */
|
||||
unrecognized_pc = start;
|
||||
}
|
||||
|
||||
start += 2;
|
||||
|
|
@ -736,10 +1083,13 @@ thumb_analyze_prologue (struct gdbarch *gdbarch,
|
|||
fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
|
||||
paddress (gdbarch, start));
|
||||
|
||||
if (unrecognized_pc == 0)
|
||||
unrecognized_pc = start;
|
||||
|
||||
if (cache == NULL)
|
||||
{
|
||||
do_cleanups (back_to);
|
||||
return start;
|
||||
return unrecognized_pc;
|
||||
}
|
||||
|
||||
if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
|
||||
|
|
@ -772,7 +1122,7 @@ thumb_analyze_prologue (struct gdbarch *gdbarch,
|
|||
cache->saved_regs[i].addr = offset;
|
||||
|
||||
do_cleanups (back_to);
|
||||
return start;
|
||||
return unrecognized_pc;
|
||||
}
|
||||
|
||||
/* Advance the PC across any function entry prologue instructions to
|
||||
|
|
@ -956,12 +1306,12 @@ thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc,
|
|||
if (find_pc_partial_function (block_addr, NULL, &prologue_start,
|
||||
&prologue_end))
|
||||
{
|
||||
struct symtab_and_line sal = find_pc_line (prologue_start, 0);
|
||||
|
||||
if (sal.line == 0) /* no line info, use current PC */
|
||||
prologue_end = prev_pc;
|
||||
else if (sal.end < prologue_end) /* next line begins after fn end */
|
||||
prologue_end = sal.end; /* (probably means no prologue) */
|
||||
/* See comment in arm_scan_prologue for an explanation of
|
||||
this heuristics. */
|
||||
if (prologue_end > prologue_start + 64)
|
||||
{
|
||||
prologue_end = prologue_start + 64;
|
||||
}
|
||||
}
|
||||
else
|
||||
/* We're in the boondocks: we have no idea where the start of the
|
||||
|
|
|
|||
Loading…
Reference in New Issue