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@ -2306,8 +2306,12 @@ const struct powerpc_operand powerpc_operands[] =
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#define UIM3 IMM32 + 1
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{ 0x7, 32, NULL, NULL, 0},
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/* The UIM field in a vector eval prefix instruction. */
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#define UIM8 UIM3 + 1
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{ 0xff, 32, NULL, NULL, 0},
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/* The IX field in xxsplti32dx. */
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#define IX UIM3 + 1
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#define IX UIM8 + 1
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{ 0x1, 17, NULL, NULL, 0 },
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/* The PMSK field in GER rank 8 prefix instructions. */
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@ -3107,6 +3111,7 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
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/* Mask for prefix vector permute insns. */
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#define P_XX4_MASK (PREFIX_MASK | XX4_MASK)
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#define P_UXX4_MASK (P_XX4_MASK & ~(7ULL << 32))
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#define P_U8XX4_MASK (P_XX4_MASK & ~(0xffULL << 32))
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/* MMIRR:XX3-form 8-byte outer product instructions. */
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#define P_GER_MASK ((-1ULL << 40) | XX3_MASK | (3 << 21) | 1)
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@ -4738,6 +4743,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}},
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{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}},
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{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}},
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{"vgnb", VX (4,1228), VX_MASK, POWER10, 0, {RT, VB, UIMM3}},
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{"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
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{"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
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{"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
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@ -4796,6 +4802,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"evmwlsmfaaw", VX (4,1355), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
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{"evmwhumiaa", VX (4,1356), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
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{"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
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{"vcfuged", VX (4,1357), VX_MASK, POWER10, 0, {VD, VA, VB}},
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{"evmwhsmiaa", VX (4,1357), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
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{"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
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{"evmwhsmfaa", VX (4,1359), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
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@ -4834,6 +4841,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
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{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
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{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
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{"vpextd", VX (4,1421), VX_MASK, POWER10, 0, {VD, VA, VB}},
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{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
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{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
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{"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
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@ -4862,6 +4870,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"evmwlsmfanw", VX (4,1483), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
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{"evmwhumian", VX (4,1484), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
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{"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
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{"vpdepd", VX (4,1485), VX_MASK, POWER10, 0, {VD, VA, VB}},
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{"evmwhsmian", VX (4,1485), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
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{"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
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{"evmwhsmfan", VX (4,1487), VX_MASK, PPCSPE, 0, {RD, RA, RB}},
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@ -4977,6 +4986,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
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{"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
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{"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
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{"vclzdm", VX (4,1924), VX_MASK, POWER10, 0, {VD, VA, VB}},
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{"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
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{"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
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{"vcmpgtsq.", VXR(4, 903,1), VXR_MASK, POWER10, 0, {VD, VA, VB}},
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@ -4989,6 +4999,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
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{"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
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{"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
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{"vctzdm", VX (4,1988), VX_MASK, POWER10, 0, {VD, VA, VB}},
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{"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
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{"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, 0, {URT, URA, URB}},
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{"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
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@ -6102,6 +6113,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, 0, {RA, RS}},
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{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, 0, {RA, RS}},
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{"cntlzdm", X(31,59), X_MASK, POWER10, 0, {RA, RS, RB}},
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{"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}},
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{"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}},
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@ -6236,6 +6249,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}},
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{"brw", X(31,155), XRB_MASK, POWER10, 0, {RA, RS}},
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{"pdepd", X(31,156), X_MASK, POWER10, 0, {RA, RS, RB}},
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{"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
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@ -6278,6 +6292,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}},
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{"brd", X(31,187), XRB_MASK, POWER10, 0, {RA, RS}},
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{"pextd", X(31,188), X_MASK, POWER10, 0, {RA, RS, RB}},
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{"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}},
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@ -6318,6 +6333,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}},
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{"brh", X(31,219), XRB_MASK, POWER10, 0, {RA, RS}},
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{"cfuged", X(31,220), X_MASK, POWER10, 0, {RA, RS, RB}},
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{"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
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@ -7170,6 +7186,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, 0, {RA, RS}},
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{"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, 0, {RA, RS}},
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{"cnttzdm", X(31,571), X_MASK, POWER10, 0, {RA, RS, RB}},
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{"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}},
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{"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}},
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@ -8408,6 +8426,7 @@ const struct powerpc_opcode prefix_opcodes[] = {
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{"xxblendvw", P8RR|XX4(33,2), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}},
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{"xxblendvd", P8RR|XX4(33,3), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}},
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{"xxpermx", P8RR|XX4(34,0), P_UXX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6, UIM3}},
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{"xxeval", P8RR|XX4(34,1), P_U8XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6, UIM8}},
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{"plbz", PMLS|OP(34), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}},
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{"pstw", PMLS|OP(36), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}},
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{"pstb", PMLS|OP(38), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}},
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