Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/ * sparc.h (struct sparc_opcode): New field 'hwcaps'. F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2, F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS, F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete. (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC, HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF, HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU, HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES, HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1, HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE, HWCAP_CBCOND, HWCAP_CRC32): New defines. opcodes/ * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values into new struct sparc_opcode 'hwcaps' field instead of 'flags'. gas/ * config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_* masks. (sparc_md_end): No longer need to translate hwcap_seen values into ELF hwcap bits, they now match exactly. (get_hwcap_name): Use HWCAP_* and handle new values. (sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
This commit is contained in:
David S. Miller
parent
4d29644716
commit
ec668d69b9
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@ -1,3 +1,12 @@
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2012-04-27 David S. Miller <davem@davemloft.net>
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* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
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masks.
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(sparc_md_end): No longer need to translate hwcap_seen values into
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ELF hwcap bits, they now match exactly.
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(get_hwcap_name): Use HWCAP_* and handle new values.
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(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
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2012-04-20 Tristan Gingold <gingold@adacore.com>
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* config/tc-ia64.c (obj_elf_vms_common): New function.
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@ -237,33 +237,33 @@ static struct sparc_arch {
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} sparc_arch_table[] = {
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{ "v6", "v6", v6, 0, 1, 0 },
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{ "v7", "v7", v7, 0, 1, 0 },
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{ "v8", "v8", v8, 32, 1, F_MUL32|F_DIV32|F_FSMULD },
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{ "v8a", "v8", v8, 32, 1, F_MUL32|F_DIV32|F_FSMULD },
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{ "sparc", "v9", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_V8PLUS },
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{ "sparcvis", "v9a", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS },
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{ "sparcvis2", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2 },
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{ "sparcfmaf", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_FMAF },
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{ "sparcima", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_FMAF|F_IMA },
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{ "sparcvis3", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_FMAF|F_VIS3|F_HPC },
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{ "sparcvis3r", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_FMAF|F_VIS3|F_HPC|F_RANDOM|F_TRANS|F_FJFMAU },
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{ "sparclet", "sparclet", sparclet, 32, 1, F_MUL32|F_DIV32|F_FSMULD },
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{ "sparclite", "sparclite", sparclite, 32, 1, F_MUL32|F_DIV32|F_FSMULD },
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{ "sparc86x", "sparclite", sparc86x, 32, 1, F_MUL32|F_DIV32|F_FSMULD },
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{ "v8plus", "v9", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_V8PLUS },
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{ "v8plusa", "v9a", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_V8PLUS|F_VIS },
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{ "v8plusb", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_V8PLUS|F_VIS|F_VIS2 },
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{ "v8plusc", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_V8PLUS|F_VIS|F_VIS2|F_ASI_BLK_INIT },
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{ "v8plusd", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_V8PLUS|F_VIS|F_VIS2|F_ASI_BLK_INIT|F_FMAF|F_VIS3|F_HPC },
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{ "v8plusv", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_V8PLUS|F_VIS|F_VIS2|F_ASI_BLK_INIT|F_FMAF|F_VIS3|F_HPC|F_RANDOM|F_TRANS|F_FJFMAU|F_IMA|F_ASI_CACHE_SPARING },
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{ "v9", "v9", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC },
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{ "v9a", "v9a", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS },
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{ "v9b", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2 },
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{ "v9c", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_ASI_BLK_INIT },
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{ "v9d", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_ASI_BLK_INIT|F_FMAF|F_VIS3|F_HPC },
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{ "v9v", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_ASI_BLK_INIT|F_FMAF|F_VIS3|F_HPC|F_RANDOM|F_TRANS|F_FJFMAU|F_IMA|F_ASI_CACHE_SPARING },
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{ "v8", "v8", v8, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
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{ "v8a", "v8", v8, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
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{ "sparc", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS },
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{ "sparcvis", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS },
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{ "sparcvis2", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2 },
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{ "sparcfmaf", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF },
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{ "sparcima", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_IMA },
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{ "sparcvis3", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
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{ "sparcvis3r", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU },
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{ "sparclet", "sparclet", sparclet, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
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{ "sparclite", "sparclite", sparclite, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
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{ "sparc86x", "sparclite", sparc86x, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
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{ "v8plus", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS },
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{ "v8plusa", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS },
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{ "v8plusb", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2 },
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{ "v8plusc", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT },
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{ "v8plusd", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
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{ "v8plusv", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING },
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{ "v9", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC },
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{ "v9a", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS },
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{ "v9b", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2 },
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{ "v9c", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT },
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{ "v9d", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
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{ "v9v", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING },
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/* This exists to allow configure.in/Makefile.in to pass one
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value to specify both the default machine and default word size. */
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{ "v9-64", "v9", v9, 64, 0, F_MUL32|F_DIV32|F_FSMULD|F_POPC },
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{ "v9-64", "v9", v9, 64, 0, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC },
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{ NULL, NULL, v8, 0, 0, 0 }
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};
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@ -945,44 +945,7 @@ sparc_md_end (void)
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#if defined(OBJ_ELF) && !defined(TE_SOLARIS)
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if (hwcap_seen)
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{
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int bits = 0;
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if (hwcap_seen & F_MUL32)
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bits |= ELF_SPARC_HWCAP_MUL32;
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if (hwcap_seen & F_DIV32)
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bits |= ELF_SPARC_HWCAP_DIV32;
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if (hwcap_seen & F_FSMULD)
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bits |= ELF_SPARC_HWCAP_FSMULD;
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if (hwcap_seen & F_V8PLUS)
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bits |= ELF_SPARC_HWCAP_V8PLUS;
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if (hwcap_seen & F_POPC)
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bits |= ELF_SPARC_HWCAP_POPC;
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if (hwcap_seen & F_VIS)
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bits |= ELF_SPARC_HWCAP_VIS;
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if (hwcap_seen & F_VIS2)
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bits |= ELF_SPARC_HWCAP_VIS2;
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if (hwcap_seen & F_ASI_BLK_INIT)
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bits |= ELF_SPARC_HWCAP_ASI_BLK_INIT;
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if (hwcap_seen & F_FMAF)
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bits |= ELF_SPARC_HWCAP_FMAF;
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if (hwcap_seen & F_VIS3)
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bits |= ELF_SPARC_HWCAP_VIS3;
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if (hwcap_seen & F_HPC)
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bits |= ELF_SPARC_HWCAP_HPC;
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if (hwcap_seen & F_RANDOM)
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bits |= ELF_SPARC_HWCAP_RANDOM;
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if (hwcap_seen & F_TRANS)
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bits |= ELF_SPARC_HWCAP_TRANS;
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if (hwcap_seen & F_FJFMAU)
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bits |= ELF_SPARC_HWCAP_FJFMAU;
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if (hwcap_seen & F_IMA)
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bits |= ELF_SPARC_HWCAP_IMA;
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if (hwcap_seen & F_ASI_CACHE_SPARING)
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bits |= ELF_SPARC_HWCAP_ASI_CACHE_SPARING;
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bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS, bits);
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}
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bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS, hwcap_seen);
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#endif
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}
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@ -1440,38 +1403,64 @@ md_assemble (char *str)
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static const char *
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get_hwcap_name (int mask)
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{
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if (mask & F_MUL32)
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if (mask & HWCAP_MUL32)
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return "mul32";
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if (mask & F_DIV32)
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if (mask & HWCAP_DIV32)
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return "div32";
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if (mask & F_FSMULD)
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if (mask & HWCAP_FSMULD)
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return "fsmuld";
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if (mask & F_V8PLUS)
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if (mask & HWCAP_V8PLUS)
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return "v8plus";
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if (mask & F_POPC)
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if (mask & HWCAP_POPC)
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return "popc";
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if (mask & F_VIS)
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if (mask & HWCAP_VIS)
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return "vis";
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if (mask & F_VIS2)
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if (mask & HWCAP_VIS2)
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return "vis2";
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if (mask & F_ASI_BLK_INIT)
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if (mask & HWCAP_ASI_BLK_INIT)
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return "ASIBlkInit";
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if (mask & F_FMAF)
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if (mask & HWCAP_FMAF)
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return "fmaf";
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if (mask & F_VIS3)
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if (mask & HWCAP_VIS3)
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return "vis3";
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if (mask & F_HPC)
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if (mask & HWCAP_HPC)
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return "hpc";
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if (mask & F_RANDOM)
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if (mask & HWCAP_RANDOM)
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return "random";
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if (mask & F_TRANS)
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if (mask & HWCAP_TRANS)
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return "trans";
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if (mask & F_FJFMAU)
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if (mask & HWCAP_FJFMAU)
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return "fjfmau";
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if (mask & F_IMA)
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if (mask & HWCAP_IMA)
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return "ima";
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if (mask & F_ASI_CACHE_SPARING)
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if (mask & HWCAP_ASI_CACHE_SPARING)
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return "cspare";
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if (mask & HWCAP_AES)
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return "aes";
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if (mask & HWCAP_DES)
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return "des";
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if (mask & HWCAP_KASUMI)
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return "kasumi";
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if (mask & HWCAP_CAMELLIA)
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return "camellia";
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if (mask & HWCAP_MD5)
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return "md5";
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if (mask & HWCAP_SHA1)
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return "sha1";
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if (mask & HWCAP_SHA256)
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return "sha256";
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if (mask & HWCAP_SHA512)
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return "sha512";
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if (mask & HWCAP_MPMUL)
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return "mpmul";
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if (mask & HWCAP_MONT)
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return "mont";
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if (mask & HWCAP_PAUSE)
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return "pause";
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if (mask & HWCAP_CBCOND)
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return "cbcond";
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if (mask & HWCAP_CRC32C)
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return "crc32c";
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return "UNKNOWN";
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}
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@ -2862,7 +2851,7 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
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{
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/* We have a match. Now see if the architecture is OK. */
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int needed_arch_mask = insn->architecture;
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int hwcaps = insn->flags & F_HWCAP_MASK;
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int hwcaps = insn->hwcaps;
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#if defined(OBJ_ELF) && !defined(TE_SOLARIS)
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if (hwcaps)
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@ -1,3 +1,17 @@
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2012-04-27 David S. Miller <davem@davemloft.net>
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* sparc.h (struct sparc_opcode): New field 'hwcaps'.
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F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
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F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
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F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
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(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
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HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
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HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
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HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
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HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
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HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
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HWCAP_CBCOND, HWCAP_CRC32): New defines.
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2012-03-10 Edmar Wienskoski <edmar@freescale.com>
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* ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
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@ -99,6 +99,7 @@ typedef struct sparc_opcode
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const char *args;
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/* This was called "delayed" in versions before the flags. */
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unsigned int flags;
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unsigned int hwcaps;
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short architecture; /* Bitmask of sparc_opcode_arch_val's. */
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} sparc_opcode;
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@ -110,25 +111,39 @@ typedef struct sparc_opcode
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#define F_JSR 0x00000010 /* Subroutine call. */
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#define F_FLOAT 0x00000020 /* Floating point instruction (not a branch). */
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#define F_FBR 0x00000040 /* Floating point branch. */
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#define F_MUL32 0x00000100 /* umul/umulcc/smul/smulcc insns */
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#define F_DIV32 0x00000200 /* udiv/udivcc/sdiv/sdivcc insns */
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#define F_FSMULD 0x00000400 /* 'fsmuld' insn */
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#define F_V8PLUS 0x00000800 /* v9 insns available to 32bit */
|
||||
#define F_POPC 0x00001000 /* 'popc' insn */
|
||||
#define F_VIS 0x00002000 /* VIS insns */
|
||||
#define F_VIS2 0x00004000 /* VIS2 insns */
|
||||
#define F_ASI_BLK_INIT 0x00008000 /* block init ASIs */
|
||||
#define F_FMAF 0x00010000 /* fused multiply-add */
|
||||
#define F_VIS3 0x00020000 /* VIS3 insns */
|
||||
#define F_HPC 0x00040000 /* HPC insns */
|
||||
#define F_RANDOM 0x00080000 /* 'random' insn */
|
||||
#define F_TRANS 0x00100000 /* transaction insns */
|
||||
#define F_FJFMAU 0x00200000 /* unfused multiply-add */
|
||||
#define F_IMA 0x00400000 /* integer multiply-add */
|
||||
#define F_ASI_CACHE_SPARING \
|
||||
0x00800000 /* cache sparing ASIs */
|
||||
|
||||
#define F_HWCAP_MASK 0x00ffff00
|
||||
/* These must match the HWCAP_* values precisely. */
|
||||
#define HWCAP_MUL32 0x00000001 /* umul/umulcc/smul/smulcc insns */
|
||||
#define HWCAP_DIV32 0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */
|
||||
#define HWCAP_FSMULD 0x00000004 /* 'fsmuld' insn */
|
||||
#define HWCAP_V8PLUS 0x00000008 /* v9 insns available to 32bit */
|
||||
#define HWCAP_POPC 0x00000010 /* 'popc' insn */
|
||||
#define HWCAP_VIS 0x00000020 /* VIS insns */
|
||||
#define HWCAP_VIS2 0x00000040 /* VIS2 insns */
|
||||
#define HWCAP_ASI_BLK_INIT \
|
||||
0x00000080 /* block init ASIs */
|
||||
#define HWCAP_FMAF 0x00000100 /* fused multiply-add */
|
||||
#define HWCAP_VIS3 0x00000400 /* VIS3 insns */
|
||||
#define HWCAP_HPC 0x00000800 /* HPC insns */
|
||||
#define HWCAP_RANDOM 0x00001000 /* 'random' insn */
|
||||
#define HWCAP_TRANS 0x00002000 /* transaction insns */
|
||||
#define HWCAP_FJFMAU 0x00004000 /* unfused multiply-add */
|
||||
#define HWCAP_IMA 0x00008000 /* integer multiply-add */
|
||||
#define HWCAP_ASI_CACHE_SPARING \
|
||||
0x00010000 /* cache sparing ASIs */
|
||||
#define HWCAP_AES 0x00020000 /* AES crypto insns */
|
||||
#define HWCAP_DES 0x00040000 /* DES crypto insns */
|
||||
#define HWCAP_KASUMI 0x00080000 /* KASUMI crypto insns */
|
||||
#define HWCAP_CAMELLIA 0x00100000 /* CAMELLIA crypto insns */
|
||||
#define HWCAP_MD5 0x00200000 /* MD5 hashing insns */
|
||||
#define HWCAP_SHA1 0x00400000 /* SHA1 hashing insns */
|
||||
#define HWCAP_SHA256 0x00800000 /* SHA256 hashing insns */
|
||||
#define HWCAP_SHA512 0x01000000 /* SHA512 hashing insns */
|
||||
#define HWCAP_MPMUL 0x02000000 /* Multiple Precision Multiply */
|
||||
#define HWCAP_MONT 0x04000000 /* Montgomery Mult/Sqrt */
|
||||
#define HWCAP_PAUSE 0x08000000 /* Pause insn */
|
||||
#define HWCAP_CBCOND 0x10000000 /* Compare and Branch insns */
|
||||
#define HWCAP_CRC32C 0x20000000 /* CRC32C insn */
|
||||
|
||||
/* All sparc opcodes are 32 bits, except for the `set' instruction (really a
|
||||
macro), which is 64 bits. It is handled as a special case.
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
2012-04-27 David S. Miller <davem@davemloft.net>
|
||||
|
||||
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
|
||||
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
|
||||
|
||||
2012-04-12 David S. Miller <davem@davemloft.net>
|
||||
|
||||
* sparc-dis.c (X_DISP10): Define.
|
||||
|
|
|
|||
2416
opcodes/sparc-opc.c
2416
opcodes/sparc-opc.c
File diff suppressed because it is too large
Load Diff
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Reference in New Issue