* arc-opc.c (MULTSHIFT operand): Delete.
(UNSIGNED, SATURATION): New operands. (mac, mul, mul64, mulu64): New insns. (ext. asl, asr, lsr, ror): Only available on host and graphics cpus. (padc, padd, pmov, pand, psbc, psub, swap): New insns. (host,graphics,audio extended and auxiliary regs): Define. (ss, sc, mh, ml): New suffixes. (arc_opcode_supported, arc_opval_supported): New functions. (insert_multshift, extract_multshift): Deleted.
This commit is contained in:
David Edelsohn
parent
98d42df90d
commit
ecec4df3e8
@ -1,5 +1,5 @@
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/* Opcode table for the ARC.
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Copyright 1994 Free Software Foundation, Inc.
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Copyright 1994, 1995 Free Software Foundation, Inc.
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Contributed by Doug Evans (dje@cygnus.com).
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This program is free software; you can redistribute it and/or modify
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@ -16,6 +16,9 @@
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* The ARC may eventually be bi-endian.
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Keep this file byte order independent. */
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#include "ansidecl.h"
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#include "opcode/arc.h"
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@ -43,6 +46,7 @@ INSERT_FN (insert_multshift);
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EXTRACT_FN (extract_reg);
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EXTRACT_FN (extract_flag);
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EXTRACT_FN (extract_cond);
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EXTRACT_FN (extract_reladdr);
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EXTRACT_FN (extract_unopmacro);
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EXTRACT_FN (extract_multshift);
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@ -69,14 +73,15 @@ EXTRACT_FN (extract_multshift);
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'y' SIZE22 size field in st c,[b,shimm]
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'x' SIGN0 sign extend field ld a,[b,c]
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'X' SIGN9 sign extend field ld a,[b,shimm]
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'u' ADDRESS3 update field in ld a,[b,c]
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'v' ADDRESS12 update field in ld a,[b,shimm]
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'w' ADDRESS24 update field in st c,[b,shimm]
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'w' ADDRESS3 write-back field in ld a,[b,c]
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'W' ADDRESS12 write-back field in ld a,[b,shimm]
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'v' ADDRESS24 write-back field in st c,[b,shimm]
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'D' CACHEBYPASS5 direct to memory enable (cache bypass) in ld a,[b,c]
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'e' CACHEBYPASS14 direct to memory enable (cache bypass) in ld a,[b,shimm]
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'E' CACHEBYPASS26 direct to memory enable (cache bypass) in st c,[b,shimm]
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'u' UNSIGNED unsigned multiply
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's' SATURATION saturation limit in audio arc mac insn
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'U' UNOPMACRO fake operand to copy REGB to REGC for unop macros
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'M' MULTSHIFT fake operand to check if target has multiply/shifter
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The following modifiers may appear between the % and char (eg: %.f):
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@ -149,7 +154,7 @@ const struct arc_operand arc_operands[] =
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/* branch address b, bl, and lp insns */
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#define BRANCH (FORCELIMM + 1)
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{ 'B', 20, 7, ARC_OPERAND_RELATIVE + ARC_OPERAND_SIGNED, insert_reladdr },
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{ 'B', 20, 7, ARC_OPERAND_RELATIVE + ARC_OPERAND_SIGNED, insert_reladdr, extract_reladdr },
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/* size field, stored in bit 1,2 */
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#define SIZE1 (BRANCH + 1)
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@ -173,39 +178,42 @@ const struct arc_operand arc_operands[] =
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/* address write back, stored in bit 3 */
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#define ADDRESS3 (SIGN9 + 1)
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{ 'u', 1, 3, ARC_OPERAND_SUFFIX },
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{ 'w', 1, 3, ARC_OPERAND_SUFFIX },
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/* address write back, stored in bit 12 */
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#define ADDRESS12 (ADDRESS3 + 1)
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{ 'v', 1, 12, ARC_OPERAND_SUFFIX },
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{ 'W', 1, 12, ARC_OPERAND_SUFFIX },
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/* address write back, stored in bit 24 */
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#define ADDRESS24 (ADDRESS12 + 1)
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{ 'w', 1, 24, ARC_OPERAND_SUFFIX },
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{ 'v', 1, 24, ARC_OPERAND_SUFFIX },
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/* address write back, stored in bit 3 */
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/* cache bypass, stored in bit 5 */
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#define CACHEBYPASS5 (ADDRESS24 + 1)
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{ 'D', 1, 5, ARC_OPERAND_SUFFIX },
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/* address write back, stored in bit 12 */
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/* cache bypass, stored in bit 14 */
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#define CACHEBYPASS14 (CACHEBYPASS5 + 1)
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{ 'e', 1, 14, ARC_OPERAND_SUFFIX },
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/* address write back, stored in bit 24 */
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/* cache bypass, stored in bit 26 */
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#define CACHEBYPASS26 (CACHEBYPASS14 + 1)
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{ 'E', 1, 26, ARC_OPERAND_SUFFIX },
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/* unsigned multiply */
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#define UNSIGNED (CACHEBYPASS26 + 1)
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{ 'u', 1, 27, ARC_OPERAND_SUFFIX },
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/* unsigned multiply */
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#define SATURATION (UNSIGNED + 1)
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{ 's', 1, 28, ARC_OPERAND_SUFFIX },
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/* unop macro, used to copy REGB to REGC */
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#define UNOPMACRO (CACHEBYPASS26 + 1)
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#define UNOPMACRO (SATURATION + 1)
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{ 'U', 6, ARC_SHIFT_REGC, ARC_OPERAND_FAKE, insert_unopmacro, extract_unopmacro },
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/* multiply/shifter detector */
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/* ??? Using ARC_OPERAND_FAKE this way is probably taking things too far. */
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#define MULTSHIFT (UNOPMACRO + 1)
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{ 'M', 0, 0, ARC_OPERAND_FAKE, insert_multshift, extract_multshift },
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/* '.' modifier ('.' required). */
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#define MODDOT (MULTSHIFT + 1)
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#define MODDOT (UNOPMACRO + 1)
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{ '.', 1, 0, ARC_MOD_DOT },
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/* Dummy 'r' modifier for the register table.
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@ -255,18 +263,22 @@ unsigned char arc_operand_map[256];
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together. */
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const struct arc_opcode arc_opcodes[] = {
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{ "mac%u%.s%.q%.f %a,%b,%c%F%S%L", I(-4), I(24), ARC_MACH_AUDIO },
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/* Note that "mov" is really an "and". */
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{ "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12) },
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{ "mul%M%.q%.f %a,%b,%c%F%S%L", I(-1), I(20) },
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{ "mulu%M%.q%.f %a,%b,%c%F%S%L", I(-1), I(21) },
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{ "mul%u%.q%.f %a,%b,%c%F%S%L", I(-2), I(28), ARC_MACH_AUDIO },
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/* ??? This insn allows an optional "0," preceding the args. */
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/* We can't use %u here because it's not a suffix (the "64" is in the way). */
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{ "mul64%.q%.f %b,%c%F%S%L", I(-1)+A(-1), I(20)+A(-1), ARC_MACH_HOST+ARC_MACH_GRAPHICS },
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{ "mulu64%.q%.f %b,%c%F%S%L", I(-1)+A(-1), I(21)+A(-1), ARC_MACH_HOST+ARC_MACH_GRAPHICS },
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{ "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9) },
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{ "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8) },
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{ "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12) },
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{ "asl%M%.q%.f %a,%b,%c%F%S%L", I(-1), I(16) },
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{ "asl%.q%.f %a,%b,%c%F%S%L", I(-1), I(16), ARC_MACH_HOST+ARC_MACH_GRAPHICS },
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/* Note that "asl" is really an "add". */
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{ "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) },
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{ "asr%M%.q%.f %a,%b,%c%F%S%L", I(-1), I(18) },
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{ "asr%.q%.f %a,%b,%c%F%S%L", I(-1), I(18), ARC_MACH_HOST+ARC_MACH_GRAPHICS },
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{ "asr%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(1) },
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{ "bic%.q%.f %a,%b,%c%F%S%L", I(-1), I(14) },
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{ "b%q%.n %B", I(-1), I(4) },
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@ -285,14 +297,22 @@ const struct arc_opcode arc_opcodes[] = {
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{ "lr %a,[%Ab]%S%L", I(-1)+C(-1), I(1)+C(0x10) },
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/* Note that "lsl" is really an "add". */
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{ "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) },
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{ "lsr%M%.q%.f %a,%b,%c%F%S%L", I(-1), I(17) },
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{ "lsr%.q%.f %a,%b,%c%F%S%L", I(-1), I(17), ARC_MACH_HOST+ARC_MACH_GRAPHICS },
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{ "lsr%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(2) },
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/* Note that "nop" is really an "xor". */
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{ "nop", 0xffffffff, 0x7fffffff },
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{ "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13) },
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/* ??? The %a here should be %p or something. */
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{ "padc%.q%.f %a,%b,%c%F%S%L", I(-1), I(25), ARC_MACH_GRAPHICS },
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{ "padd%.q%.f %a,%b,%c%F%S%L", I(-1), I(24), ARC_MACH_GRAPHICS },
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/* Note that "pmov" is really a "pand". */
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{ "pmov%.q%.f %a,%b%F%S%L%U", I(-1), I(28), ARC_MACH_GRAPHICS },
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{ "pand%.q%.f %a,%b,%c%F%S%L", I(-1), I(28), ARC_MACH_GRAPHICS },
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{ "psbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(27), ARC_MACH_GRAPHICS },
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{ "psub%.q%.f %a,%b,%c%F%S%L", I(-1), I(26), ARC_MACH_GRAPHICS },
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/* Note that "rlc" is really an "adc". */
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{ "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9) },
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{ "ror%M%.q%.f %a,%b,%c%F%S%L", I(-1), I(19) },
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{ "ror%.q%.f %a,%b,%c%F%S%L", I(-1), I(19), ARC_MACH_HOST+ARC_MACH_GRAPHICS },
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{ "ror%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(3) },
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{ "rrc%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(4) },
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{ "sbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(11) },
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@ -303,6 +323,7 @@ const struct arc_opcode arc_opcodes[] = {
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{ "st%y%.w%.E %0%c,[%b]%L", I(-1)+R(-1,25,3)+R(-1,21,1)+R(-1,0,511), I(2)+R(0,25,3)+R(0,21,1)+R(0,0,511) },
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{ "st%y%.w%.E %c,[%b,%d]%S%L", I(-1)+R(-1,25,3)+R(-1,21,1), I(2)+R(0,25,3)+R(0,21,1) },
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{ "sub%.q%.f %a,%b,%c%F%S%L", I(-1), I(10) },
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{ "swap%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(9), ARC_MACH_AUDIO },
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{ "xor%.q%.f %a,%b,%c%F%S%L", I(-1), I(15) }
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};
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int arc_opcodes_count = sizeof (arc_opcodes) / sizeof (arc_opcodes[0]);
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@ -340,6 +361,76 @@ const struct arc_operand_value arc_reg_names[] =
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{ "lp_end", 3, AUXREG },
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{ "identity", 4, AUXREG },
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{ "debug", 5, AUXREG },
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/* Host ARC Extensions. */
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{ "mlo", 57, REG, ARC_MACH_HOST },
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{ "mmid", 58, REG, ARC_MACH_HOST },
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{ "mhi", 59, REG, ARC_MACH_HOST },
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{ "ivic", 0x10, AUXREG, ARC_MACH_HOST },
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{ "ivdc", 0x11, AUXREG, ARC_MACH_HOST },
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{ "ivdcn", 0x12, AUXREG, ARC_MACH_HOST },
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{ "flushd", 0x13, AUXREG, ARC_MACH_HOST },
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{ "saha", 0x14, AUXREG, ARC_MACH_HOST },
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{ "gahd", 0x15, AUXREG, ARC_MACH_HOST },
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{ "aahd", 0x16, AUXREG, ARC_MACH_HOST },
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{ "rrcr", 0x17, AUXREG, ARC_MACH_HOST },
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{ "rpcr", 0x18, AUXREG, ARC_MACH_HOST },
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{ "flushdn", 0x19, AUXREG, ARC_MACH_HOST },
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{ "dbgad1", 0x1a, AUXREG, ARC_MACH_HOST },
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{ "dbgad2", 0x1b, AUXREG, ARC_MACH_HOST },
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{ "dbgmde", 0x1c, AUXREG, ARC_MACH_HOST },
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{ "dbgstat", 0x1d, AUXREG, ARC_MACH_HOST },
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{ "wag", 0x1e, AUXREG, ARC_MACH_HOST },
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{ "mulhi", 0x1f, AUXREG, ARC_MACH_HOST },
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{ "intwide", 0x20, AUXREG, ARC_MACH_HOST },
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{ "intgen", 0x21, AUXREG, ARC_MACH_HOST },
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{ "rfsh_n", 0x22, AUXREG, ARC_MACH_HOST },
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/* Graphics ARC Extensions. */
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{ "mlo", 57, REG, ARC_MACH_GRAPHICS },
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{ "mmid", 58, REG, ARC_MACH_GRAPHICS },
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{ "mhi", 59, REG, ARC_MACH_GRAPHICS },
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{ "ivic", 0x10, AUXREG, ARC_MACH_GRAPHICS },
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{ "wag", 0x1e, AUXREG, ARC_MACH_GRAPHICS },
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{ "mulhi", 0x1f, AUXREG, ARC_MACH_GRAPHICS },
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{ "intwide", 0x20, AUXREG, ARC_MACH_GRAPHICS },
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{ "intgen", 0x21, AUXREG, ARC_MACH_GRAPHICS },
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{ "pix", 0x100, AUXREG, ARC_MACH_GRAPHICS },
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{ "scratch", 0x120, AUXREG, ARC_MACH_GRAPHICS },
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/* Audio ARC Extensions. */
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{ "macmode", 39, REG, ARC_MACH_AUDIO },
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{ "rs1", 40, REG, ARC_MACH_AUDIO },
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{ "rs1n", 41, REG, ARC_MACH_AUDIO },
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{ "rs1start", 42, REG, ARC_MACH_AUDIO },
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{ "rs1size", 43, REG, ARC_MACH_AUDIO },
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{ "rs1delta", 44, REG, ARC_MACH_AUDIO },
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{ "rs1pos", 45, REG, ARC_MACH_AUDIO },
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{ "rd1", 46, REG, ARC_MACH_AUDIO },
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{ "rd1n", 47, REG, ARC_MACH_AUDIO },
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{ "rd1d", 48, REG, ARC_MACH_AUDIO },
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{ "rd1pos", 49, REG, ARC_MACH_AUDIO },
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{ "rs2", 50, REG, ARC_MACH_AUDIO },
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{ "rs2n", 51, REG, ARC_MACH_AUDIO },
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{ "rs2start", 52, REG, ARC_MACH_AUDIO },
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{ "rs2size", 53, REG, ARC_MACH_AUDIO },
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{ "rs2delta", 54, REG, ARC_MACH_AUDIO },
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{ "rs2pos", 55, REG, ARC_MACH_AUDIO },
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{ "rd2", 56, REG, ARC_MACH_AUDIO },
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{ "rd2n", 57, REG, ARC_MACH_AUDIO },
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{ "rd2d", 58, REG, ARC_MACH_AUDIO },
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{ "rd2pos", 59, REG, ARC_MACH_AUDIO },
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{ "ivic", 0x10, AUXREG, ARC_MACH_AUDIO },
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{ "wag", 0x1e, AUXREG, ARC_MACH_AUDIO },
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{ "intwide", 0x20, AUXREG, ARC_MACH_AUDIO },
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{ "intgen", 0x21, AUXREG, ARC_MACH_AUDIO },
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{ "bm_sstart", 0x30, AUXREG, ARC_MACH_AUDIO },
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{ "bm_length", 0x31, AUXREG, ARC_MACH_AUDIO },
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{ "bm_rstart", 0x32, AUXREG, ARC_MACH_AUDIO },
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{ "bm_go", 0x33, AUXREG, ARC_MACH_AUDIO },
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{ "xtp_newval", 0x40, AUXREG, ARC_MACH_AUDIO },
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{ "sram", 0x400, AUXREG, ARC_MACH_AUDIO },
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{ "reg_file", 0x800, AUXREG, ARC_MACH_AUDIO },
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};
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int arc_reg_names_count = sizeof (arc_reg_names) / sizeof (arc_reg_names[0]);
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@ -399,6 +490,13 @@ const struct arc_operand_value arc_suffixes[] =
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{ "di", 1, CACHEBYPASS5 },
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{ "di", 1, CACHEBYPASS14 },
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{ "di", 1, CACHEBYPASS26 },
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/* Audio ARC Extensions. */
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/* ??? The values here are guesses. */
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{ "ss", 16, COND, ARC_MACH_AUDIO },
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{ "sc", 17, COND, ARC_MACH_AUDIO },
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{ "mh", 18, COND, ARC_MACH_AUDIO },
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{ "ml", 19, COND, ARC_MACH_AUDIO },
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};
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int arc_suffixes_count = sizeof (arc_suffixes) / sizeof (arc_suffixes[0]);
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@ -410,20 +508,48 @@ static int cpu_type;
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/* Initialize any tables that need it.
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Must be called once at start up (or when first needed).
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CPU is a set of bits that say what version of the cpu we have. */
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FLAGS is a set of bits that say what version of the cpu we have. */
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void
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arc_opcode_init_tables (cpu)
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int cpu;
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arc_opcode_init_tables (flags)
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int flags;
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{
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register int i,n;
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cpu_type = flags;
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memset (arc_operand_map, 0, sizeof (arc_operand_map));
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n = sizeof (arc_operands) / sizeof (arc_operands[0]);
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for (i = 0; i < n; i++)
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arc_operand_map[arc_operands[i].fmt] = i;
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}
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cpu_type = cpu;
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/* Return non-zero if OPCODE is supported on the specified cpu.
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Cpu selection is made when calling `arc_opcode_init_tables'. */
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int
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arc_opcode_supported (opcode)
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const struct arc_opcode *opcode;
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{
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if (ARC_OPCODE_MACH (opcode->flags) == 0)
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return 1;
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if (ARC_OPCODE_MACH (opcode->flags) & ARC_HAVE_MACH (cpu_type))
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return 1;
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return 0;
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}
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/* Return non-zero if OPVAL is supported on the specified cpu.
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Cpu selection is made when calling `arc_opcode_init_tables'. */
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int
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arc_opval_supported (opval)
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const struct arc_operand_value *opval;
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{
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if (ARC_OPVAL_MACH (opval->flags) == 0)
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return 1;
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if (ARC_OPVAL_MACH (opval->flags) & ARC_HAVE_MACH (cpu_type))
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return 1;
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return 0;
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}
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/* Nonzero if we've seen an 'f' suffix (in certain insns). */
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@ -725,25 +851,9 @@ insert_reladdr (insn, operand, mods, reg, value, errmsg)
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long value;
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const char **errmsg;
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{
|
||||
/* FIXME: Addresses are stored * 4. Do we want to handle that here? */
|
||||
insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
|
||||
return insn;
|
||||
}
|
||||
|
||||
/* Fake operand to disallow the multiply and variable shift insns if the cpu
|
||||
doesn't have them. */
|
||||
|
||||
static arc_insn
|
||||
insert_multshift (insn, operand, mods, reg, value, errmsg)
|
||||
arc_insn insn;
|
||||
const struct arc_operand *operand;
|
||||
int mods;
|
||||
const struct arc_operand_value *reg;
|
||||
long value;
|
||||
const char **errmsg;
|
||||
{
|
||||
if (!(cpu_type & ARC_HAVE_MULT_SHIFT))
|
||||
*errmsg = "cpu doesn't support this insn";
|
||||
if (value & 3)
|
||||
*errmsg = "branch address not on 4 byte boundary";
|
||||
insn |= ((value >> 2) & ((1 << operand->bits) - 1)) << operand->shift;
|
||||
return insn;
|
||||
}
|
||||
|
||||
@ -897,6 +1007,27 @@ extract_cond (insn, operand, mods, opval, invalid)
|
||||
return cond;
|
||||
}
|
||||
|
||||
/* Extract a branch address.
|
||||
We return the value as a real address (not right shifted by 2). */
|
||||
|
||||
static long
|
||||
extract_reladdr (insn, operand, mods, opval, invalid)
|
||||
arc_insn *insn;
|
||||
const struct arc_operand *operand;
|
||||
int mods;
|
||||
const struct arc_operand_value **opval;
|
||||
int *invalid;
|
||||
{
|
||||
long addr;
|
||||
|
||||
addr = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
|
||||
if ((operand->flags & ARC_OPERAND_SIGNED)
|
||||
&& (addr & (1 << (operand->bits - 1))))
|
||||
addr -= 1 << operand->bits;
|
||||
|
||||
return addr << 2;
|
||||
}
|
||||
|
||||
/* The only thing this does is set the `invalid' flag if B != C.
|
||||
This is needed because the "mov" macro appears before it's real insn "and"
|
||||
and we don't want the disassembler to confuse them. */
|
||||
@ -920,22 +1051,6 @@ extract_unopmacro (insn, operand, mods, opval, invalid)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Don't recognize the multiply and variable shift insns if the cpu doesn't
|
||||
have them.
|
||||
|
||||
??? Actually, we probably should anyway. */
|
||||
|
||||
static long
|
||||
extract_multshift (insn, operand, mods, opval, invalid)
|
||||
arc_insn *insn;
|
||||
const struct arc_operand *operand;
|
||||
int mods;
|
||||
const struct arc_operand_value **opval;
|
||||
int *invalid;
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Utility for the extraction functions to return the index into
|
||||
`arc_suffixes'. */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user