Add support for moxie's mul.x and umul.x instructions
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@ -1,3 +1,7 @@
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2014-12-24 Anthony Green <green@moxielogic.com>
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* interp.c (sim_resume): Add mul.x and umul.x instructions.
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2014-12-12 Anthony Green <green@moxielogic.com>
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2014-12-12 Anthony Green <green@moxielogic.com>
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* interp.c (sim_resume): Add zex instructions.
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* interp.c (sim_resume): Add zex instructions.
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@ -622,8 +622,30 @@ sim_resume (sd, step, siggnal)
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cpu.asregs.regs[a] = (int) bv & 0xffff;
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cpu.asregs.regs[a] = (int) bv & 0xffff;
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}
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}
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break;
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break;
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case 0x14: /* bad */
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case 0x14: /* mul.x */
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case 0x15: /* bad */
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{
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int a = (inst >> 4) & 0xf;
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int b = inst & 0xf;
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unsigned av = cpu.asregs.regs[a];
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unsigned bv = cpu.asregs.regs[b];
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TRACE("mul.x");
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signed long long r =
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(signed long long) av * (signed long long) bv;
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cpu.asregs.regs[a] = r >> 32;
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}
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break;
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case 0x15: /* umul.x */
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{
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int a = (inst >> 4) & 0xf;
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int b = inst & 0xf;
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unsigned av = cpu.asregs.regs[a];
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unsigned bv = cpu.asregs.regs[b];
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TRACE("umul.x");
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unsigned long long r =
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(unsigned long long) av * (unsigned long long) bv;
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cpu.asregs.regs[a] = r >> 32;
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}
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break;
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case 0x16: /* bad */
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case 0x16: /* bad */
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case 0x17: /* bad */
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case 0x17: /* bad */
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case 0x18: /* bad */
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case 0x18: /* bad */
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