* gas/arm/copro.s: Avoid ldcl which encodes as a bad Neon instruction.
* gas/arm/copro.d: Update accordingly. * gas/arm/neon-cond.s: New test. Conditional Neon opcodes in ARM mode. * gas/arm/neon-cond.d: Expected results of above. * gas/arm/neon-cov.s: New test. Coverage of Neon instructions. * gas/arm/neon-cov.d: Expected results of above. * gas/arm/neon-ldst-es.s: New test. Element and structure loads and stores. * gas/arm/neon-ldst-es.d: Expected results of above. * gas/arm/neon-ldst-rm.s: New test. Single and multiple register loads and stores. * gas/arm/neon-ldst-rm.d: Expected results of above. * gas/arm/neon-omit.s: New test. Omission of optional operands. * gas/arm/neon-omit.d: Expected results of above. * gas/arm/vfp1.d: Expect Neon syntax for some VFP instructions. * gas/arm/vfp1_t2.d: Likewise. * gas/arm/vfp1xD.d: Likewise. * gas/arm/vfp1xD_t2.d: Likewise. * gas/arm/vfp2.d: Likewise. * gas/arm/vfp2_t2.d: Likewise. * gas/arm/vfp3-32drs.s: New test. Extended D register range for VFP instructions. * gas/arm/vfp3-32drs.d: Expected results of above. * gas/arm/vfp3-const-conv.s: New test. VFPv3 constant-load and conversion instructions. * gas/arm/vfp3-const-conv.d: Expected results of above.
This commit is contained in:
Julian Brown
parent
9e49821477
commit
edd40341c5
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@ -1,3 +1,32 @@
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2005-04-26 Julian Brown <julian@codesourcery.com>
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* gas/arm/copro.s: Avoid ldcl which encodes as a bad Neon instruction.
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* gas/arm/copro.d: Update accordingly.
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* gas/arm/neon-cond.s: New test. Conditional Neon opcodes in ARM mode.
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* gas/arm/neon-cond.d: Expected results of above.
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* gas/arm/neon-cov.s: New test. Coverage of Neon instructions.
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* gas/arm/neon-cov.d: Expected results of above.
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* gas/arm/neon-ldst-es.s: New test. Element and structure loads and
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stores.
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* gas/arm/neon-ldst-es.d: Expected results of above.
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* gas/arm/neon-ldst-rm.s: New test. Single and multiple register loads
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and stores.
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* gas/arm/neon-ldst-rm.d: Expected results of above.
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* gas/arm/neon-omit.s: New test. Omission of optional operands.
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* gas/arm/neon-omit.d: Expected results of above.
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* gas/arm/vfp1.d: Expect Neon syntax for some VFP instructions.
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* gas/arm/vfp1_t2.d: Likewise.
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* gas/arm/vfp1xD.d: Likewise.
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* gas/arm/vfp1xD_t2.d: Likewise.
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* gas/arm/vfp2.d: Likewise.
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* gas/arm/vfp2_t2.d: Likewise.
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* gas/arm/vfp3-32drs.s: New test. Extended D register range for VFP
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instructions.
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* gas/arm/vfp3-32drs.d: Expected results of above.
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* gas/arm/vfp3-const-conv.s: New test. VFPv3 constant-load and
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conversion instructions.
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* gas/arm/vfp3-const-conv.d: Expected results of above.
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2005-04-20 Paul Brook <paul@codesourcery.com>
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* gas/arm/arch7.d: Remove skip.
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@ -31,7 +31,7 @@ Disassembly of section .text:
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0+054 <[^>]*> ecc52805 stcl 8, cr2, \[r5\], \{5\}
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0+058 <[^>]*> fcd61906 ldc2l 9, cr1, \[r6\], \{6\}
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0+05c <[^>]*> fcc70a07 stc2l 10, cr0, \[r7\], \{7\}
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0+060 <[^>]*> ecd88bff ldcl 11, cr8, \[r8\], \{255\}
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0+060 <[^>]*> ecd88cff ldcl 12, cr8, \[r8\], \{255\}
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0+064 <[^>]*> ecc99cfe stcl 12, cr9, \[r9\], \{254\}
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0+068 <[^>]*> ec507d04 mrrc 13, 0, r7, r0, cr4
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0+06c <[^>]*> ec407e05 mcrr 14, 0, r7, r0, cr5
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@ -33,7 +33,8 @@ bar:
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stcl p8, c2, [r5], {5}
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ldc2l 9, c1, [r6], {6}
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stc2l p10, c0, [r7], {7}
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ldcl 11, c8, [r8], {255}
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@ using '11' below results in an (invalid) Neon vldmia instruction.
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ldcl 12, c8, [r8], {255}
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stcl p12, c9, [r9], {254}
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mrrc 13, 0, r7, r0, cr4
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mcrr p14, 0, r7, r0, cr5
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@ -0,0 +1,14 @@
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# name: Conditional Neon instructions
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# as: -mfpu=neon
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# objdump: -dr --prefix-addresses --show-raw-insn
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.*: +file format .*arm.*
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Disassembly of section \.text:
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0[0-9a-f]+ <[^>]+> 0d943b00 vldreq d3, \[r4\]
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0[0-9a-f]+ <[^>]+> be035b70 vmovlt\.16 d3\[1\], r5
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0[0-9a-f]+ <[^>]+> ac474b13 vmovge d3, r4, r7
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0[0-9a-f]+ <[^>]+> 3c543b3e vmovcc r3, r4, d30
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0[0-9a-f]+ <[^>]+> 1e223b10 vmovne\.32 d2\[1\], r3
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0[0-9a-f]+ <[^>]+> 2c521b13 vmovcs r1, r2, d3
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0[0-9a-f]+ <[^>]+> 3c421b14 vmovcc d4, r1, r2
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@ -0,0 +1,13 @@
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@ test conditional compilation
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.arm
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.text
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.syntax unified
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vldreq.32 d3,[r4]
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vmovlt.16 d3[1], r5
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vmovge d3, r4, r7
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vmovcc r3, r4, d30
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vmovne.32 d2[1],r3
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vmovcs r1,r2,d3
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vmovcc d4,r1,r2
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,595 @@
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@ Neon tests. Basic bitfield tests, using zero for as many registers/fields as
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@ possible, but without causing instructions to be badly-formed.
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.arm
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.syntax unified
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.text
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.macro regs3_1 op opq vtype
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\op\vtype q0,q0,q0
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\opq\vtype q0,q0,q0
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\op\vtype d0,d0,d0
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.endm
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.macro dregs3_1 op vtype
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\op\vtype d0,d0,d0
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.endm
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.macro regn3_1 op operand2 vtype
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\op\vtype d0,q0,\operand2
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.endm
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.macro regl3_1 op operand2 vtype
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\op\vtype q0,d0,\operand2
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.endm
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.macro regw3_1 op operand2 vtype
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\op\vtype q0,q0,\operand2
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.endm
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.macro regs2_1 op opq vtype
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\op\vtype q0,q0
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\opq\vtype q0,q0
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\op\vtype d0,d0
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.endm
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.macro regs3_su_32 op opq
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regs3_1 \op \opq .s8
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regs3_1 \op \opq .s16
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regs3_1 \op \opq .s32
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regs3_1 \op \opq .u8
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regs3_1 \op \opq .u16
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regs3_1 \op \opq .u32
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.endm
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regs3_su_32 vaba vabaq
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regs3_su_32 vhadd vhaddq
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regs3_su_32 vrhadd vrhaddq
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regs3_su_32 vhsub vhsubq
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.macro regs3_su_64 op opq
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regs3_1 \op \opq .s8
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regs3_1 \op \opq .s16
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regs3_1 \op \opq .s32
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regs3_1 \op \opq .s64
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regs3_1 \op \opq .u8
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regs3_1 \op \opq .u16
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regs3_1 \op \opq .u32
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regs3_1 \op \opq .u64
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.endm
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regs3_su_64 vqadd vqaddq
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regs3_su_64 vqsub vqsubq
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regs3_su_64 vrshl vrshlq
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regs3_su_64 vqrshl vqrshlq
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regs3_su_64 vshl vshlq
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regs3_su_64 vqshl vqshlq
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.macro regs2i_1 op opq imm vtype
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\op\vtype q0,q0,\imm
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\opq\vtype q0,q0,\imm
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\op\vtype d0,d0,\imm
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.endm
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.macro regs2i_su_64 op opq imm
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regs2i_1 \op \opq \imm .s8
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regs2i_1 \op \opq \imm .s16
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regs2i_1 \op \opq \imm .s32
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regs2i_1 \op \opq \imm .s64
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regs2i_1 \op \opq \imm .u8
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regs2i_1 \op \opq \imm .u16
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regs2i_1 \op \opq \imm .u32
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regs2i_1 \op \opq \imm .u64
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.endm
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.macro regs2i_i_64 op opq imm
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regs2i_1 \op \opq \imm .i8
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regs2i_1 \op \opq \imm .i16
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regs2i_1 \op \opq \imm .i32
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regs2i_1 \op \opq \imm .i64
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.endm
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regs2i_i_64 vshl vshlq 0
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regs2i_su_64 vqshl vqshlq 0
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.macro regs3_ntyp op opq
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regs3_1 \op \opq .8
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.endm
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regs3_ntyp vand vandq
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regs3_ntyp vbic vbicq
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regs3_ntyp vorr vorrq
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regs3_ntyp vorn vornq
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regs3_ntyp veor veorq
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.macro logic_imm_1 op opq imm vtype
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\op\vtype q0,\imm
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\opq\vtype q0,\imm
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\op\vtype d0,\imm
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.endm
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.macro logic_imm op opq
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logic_imm_1 \op \opq 0x000000ff .i32
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logic_imm_1 \op \opq 0x0000ff00 .i32
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logic_imm_1 \op \opq 0x00ff0000 .i32
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logic_imm_1 \op \opq 0xff000000 .i32
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logic_imm_1 \op \opq 0x00ff .i16
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logic_imm_1 \op \opq 0xff00 .i16
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.endm
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logic_imm vbic vbicq
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logic_imm vorr vorrq
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.macro logic_inv_imm op opq
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logic_imm_1 \op \opq 0xffffff00 .i32
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logic_imm_1 \op \opq 0xffff00ff .i32
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logic_imm_1 \op \opq 0xff00ffff .i32
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logic_imm_1 \op \opq 0x00ffffff .i32
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logic_imm_1 \op \opq 0xff00 .i16
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logic_imm_1 \op \opq 0x00ff .i16
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.endm
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logic_inv_imm vand vandq
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logic_inv_imm vorn vornq
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regs3_ntyp vbsl vbslq
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regs3_ntyp vbit vbitq
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regs3_ntyp vbif vbifq
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.macro regs3_suf_32 op opq
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regs3_1 \op \opq .s8
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regs3_1 \op \opq .s16
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regs3_1 \op \opq .s32
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regs3_1 \op \opq .u8
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regs3_1 \op \opq .u16
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regs3_1 \op \opq .u32
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regs3_1 \op \opq .f32
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.endm
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.macro regs3_if_32 op opq
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regs3_1 \op \opq .i8
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regs3_1 \op \opq .i16
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regs3_1 \op \opq .i32
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regs3_1 \op \opq .f32
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.endm
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regs3_suf_32 vabd vabdq
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regs3_suf_32 vmax vmaxq
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regs3_suf_32 vmin vminq
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regs3_suf_32 vcge vcgeq
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regs3_suf_32 vcgt vcgtq
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regs3_suf_32 vcle vcleq
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regs3_suf_32 vclt vcltq
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regs3_if_32 vceq vceqq
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.macro regs2i_sf_0 op opq
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regs2i_1 \op \opq 0 .s8
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regs2i_1 \op \opq 0 .s16
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regs2i_1 \op \opq 0 .s32
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regs2i_1 \op \opq 0 .f32
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.endm
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regs2i_sf_0 vcge vcgeq
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regs2i_sf_0 vcgt vcgtq
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regs2i_sf_0 vcle vcleq
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regs2i_sf_0 vclt vcltq
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.macro regs2i_if_0 op opq
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regs2i_1 \op \opq 0 .i8
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regs2i_1 \op \opq 0 .i16
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regs2i_1 \op \opq 0 .i32
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regs2i_1 \op \opq 0 .f32
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.endm
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regs2i_if_0 vceq vceqq
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.macro dregs3_suf_32 op
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dregs3_1 \op .s8
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dregs3_1 \op .s16
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dregs3_1 \op .s32
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dregs3_1 \op .u8
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dregs3_1 \op .u16
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dregs3_1 \op .u32
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dregs3_1 \op .f32
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.endm
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dregs3_suf_32 vpmax
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dregs3_suf_32 vpmin
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.macro sregs3_1 op opq vtype
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\op\vtype q0,q0,q0
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\opq\vtype q0,q0,q0
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\op\vtype d0,d0,d0
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.endm
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.macro sclr21_1 op opq vtype
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\op\vtype q0,q0,d0[0]
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\opq\vtype q0,q0,d0[0]
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\op\vtype d0,d0,d0[0]
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.endm
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.macro mul_incl_scalar op opq
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regs3_1 \op \opq .i8
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regs3_1 \op \opq .i16
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regs3_1 \op \opq .i32
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regs3_1 \op \opq .f32
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sclr21_1 \op \opq .i16
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sclr21_1 \op \opq .i32
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sclr21_1 \op \opq .f32
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.endm
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mul_incl_scalar vmla vmlaq
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mul_incl_scalar vmls vmlsq
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.macro dregs3_if_32 op
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dregs3_1 \op .i8
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dregs3_1 \op .i16
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dregs3_1 \op .i32
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dregs3_1 \op .f32
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.endm
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dregs3_if_32 vpadd
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.macro regs3_if_64 op opq
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regs3_1 \op \opq .i8
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regs3_1 \op \opq .i16
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regs3_1 \op \opq .i32
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regs3_1 \op \opq .i64
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regs3_1 \op \opq .f32
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.endm
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regs3_if_64 vadd vaddq
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regs3_if_64 vsub vsubq
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.macro regs3_sz_32 op opq
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regs3_1 \op \opq .8
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regs3_1 \op \opq .16
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regs3_1 \op \opq .32
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.endm
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regs3_sz_32 vtst vtstq
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.macro regs3_ifp_32 op opq
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regs3_1 \op \opq .i8
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regs3_1 \op \opq .i16
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regs3_1 \op \opq .i32
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regs3_1 \op \opq .f32
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regs3_1 \op \opq .p8
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.endm
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regs3_ifp_32 vmul vmulq
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.macro dqmulhs op opq
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regs3_1 \op \opq .s16
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regs3_1 \op \opq .s32
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sclr21_1 \op \opq .s16
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sclr21_1 \op \opq .s32
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.endm
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dqmulhs vqdmulh vqdmulhq
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dqmulhs vqrdmulh vqrdmulhq
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regs3_1 vacge vacgeq .f32
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regs3_1 vacgt vacgtq .f32
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regs3_1 vacle vacleq .f32
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regs3_1 vaclt vacltq .f32
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regs3_1 vrecps vrecpsq .f32
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regs3_1 vrsqrts vrsqrtsq .f32
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.macro regs2_sf_32 op opq
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regs2_1 \op \opq .s8
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regs2_1 \op \opq .s16
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regs2_1 \op \opq .s32
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regs2_1 \op \opq .f32
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.endm
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regs2_sf_32 vabs vabsq
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regs2_sf_32 vneg vnegq
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.macro rshift_imm op opq
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regs2i_1 \op \opq 7 .s8
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regs2i_1 \op \opq 15 .s16
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regs2i_1 \op \opq 31 .s32
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regs2i_1 \op \opq 63 .s64
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regs2i_1 \op \opq 7 .u8
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regs2i_1 \op \opq 15 .u16
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regs2i_1 \op \opq 31 .u32
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regs2i_1 \op \opq 63 .u64
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.endm
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rshift_imm vshr vshrq
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rshift_imm vrshr vrshrq
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rshift_imm vsra vsraq
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rshift_imm vrsra vrsraq
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regs2i_1 vsli vsliq 0 .8
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regs2i_1 vsli vsliq 0 .16
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regs2i_1 vsli vsliq 0 .32
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regs2i_1 vsli vsliq 0 .64
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|
||||
regs2i_1 vsri vsriq 7 .8
|
||||
regs2i_1 vsri vsriq 15 .16
|
||||
regs2i_1 vsri vsriq 31 .32
|
||||
regs2i_1 vsri vsriq 63 .64
|
||||
|
||||
regs2i_1 vqshlu vqshluq 0 .s8
|
||||
regs2i_1 vqshlu vqshluq 0 .s16
|
||||
regs2i_1 vqshlu vqshluq 0 .s32
|
||||
regs2i_1 vqshlu vqshluq 0 .s64
|
||||
|
||||
.macro qrshift_imm op
|
||||
regn3_1 \op 7 .s16
|
||||
regn3_1 \op 15 .s32
|
||||
regn3_1 \op 31 .s64
|
||||
regn3_1 \op 7 .u16
|
||||
regn3_1 \op 15 .u32
|
||||
regn3_1 \op 31 .u64
|
||||
.endm
|
||||
|
||||
.macro qrshiftu_imm op
|
||||
regn3_1 \op 7 .s16
|
||||
regn3_1 \op 15 .s32
|
||||
regn3_1 \op 31 .s64
|
||||
.endm
|
||||
|
||||
.macro qrshifti_imm op
|
||||
regn3_1 \op 7 .i16
|
||||
regn3_1 \op 15 .i32
|
||||
regn3_1 \op 31 .i64
|
||||
.endm
|
||||
|
||||
qrshift_imm vqshrn
|
||||
qrshift_imm vqrshrn
|
||||
qrshiftu_imm vqshrun
|
||||
qrshiftu_imm vqrshrun
|
||||
|
||||
qrshifti_imm vshrn
|
||||
qrshifti_imm vrshrn
|
||||
|
||||
regl3_1 vshll 1 .s8
|
||||
regl3_1 vshll 1 .s16
|
||||
regl3_1 vshll 1 .s32
|
||||
regl3_1 vshll 1 .u8
|
||||
regl3_1 vshll 1 .u16
|
||||
regl3_1 vshll 1 .u32
|
||||
|
||||
regl3_1 vshll 8 .i8
|
||||
regl3_1 vshll 16 .i16
|
||||
regl3_1 vshll 32 .i32
|
||||
|
||||
.macro convert op opr arg="" t1=".s32.f32" t2=".u32.f32" t3=".f32.s32" t4=".f32.u32"
|
||||
\op\t1 \opr,\opr\arg
|
||||
\op\t2 \opr,\opr\arg
|
||||
\op\t3 \opr,\opr\arg
|
||||
\op\t4 \opr,\opr\arg
|
||||
.endm
|
||||
|
||||
convert vcvt q0
|
||||
convert vcvtq q0
|
||||
convert vcvt d0
|
||||
convert vcvt q0 ",1"
|
||||
convert vcvtq q0 ",1"
|
||||
convert vcvt d0 ",1"
|
||||
|
||||
vmov q0,q0
|
||||
vmov d0,d0
|
||||
vmov.8 d0[0],r0
|
||||
vmov.16 d0[0],r0
|
||||
vmov.32 d0[0],r0
|
||||
vmov d0,r0,r0
|
||||
vmov.s8 r0,d0[0]
|
||||
vmov.s16 r0,d0[0]
|
||||
vmov.u8 r0,d0[0]
|
||||
vmov.u16 r0,d0[0]
|
||||
vmov.32 r0,d0[0]
|
||||
vmov r0,r1,d0
|
||||
|
||||
.macro mov_imm op imm vtype
|
||||
\op\vtype q0,\imm
|
||||
\op\vtype d0,\imm
|
||||
.endm
|
||||
|
||||
mov_imm vmov 0x00000077 .i32
|
||||
mov_imm vmvn 0x00000077 .i32
|
||||
mov_imm vmov 0x00007700 .i32
|
||||
mov_imm vmvn 0x00007700 .i32
|
||||
mov_imm vmov 0x00770000 .i32
|
||||
mov_imm vmvn 0x00770000 .i32
|
||||
mov_imm vmov 0x77000000 .i32
|
||||
mov_imm vmvn 0x77000000 .i32
|
||||
mov_imm vmov 0x0077 .i16
|
||||
mov_imm vmvn 0x0077 .i16
|
||||
mov_imm vmov 0x7700 .i16
|
||||
mov_imm vmvn 0x7700 .i16
|
||||
mov_imm vmov 0x000077ff .i32
|
||||
mov_imm vmvn 0x000077ff .i32
|
||||
mov_imm vmov 0x0077ffff .i32
|
||||
mov_imm vmvn 0x0077ffff .i32
|
||||
mov_imm vmov 0x77 .i8
|
||||
mov_imm vmov 0xff0000ff000000ff .i64
|
||||
mov_imm vmov 0x40880000 .f32
|
||||
|
||||
vmvn q0,q0
|
||||
vmvnq q0,q0
|
||||
vmvn d0,d0
|
||||
|
||||
.macro long_ops op
|
||||
regl3_1 \op d0 .s8
|
||||
regl3_1 \op d0 .s16
|
||||
regl3_1 \op d0 .s32
|
||||
regl3_1 \op d0 .u8
|
||||
regl3_1 \op d0 .u16
|
||||
regl3_1 \op d0 .u32
|
||||
.endm
|
||||
|
||||
long_ops vabal
|
||||
long_ops vabdl
|
||||
long_ops vaddl
|
||||
long_ops vsubl
|
||||
|
||||
.macro long_mac op
|
||||
regl3_1 \op d0 .s8
|
||||
regl3_1 \op d0 .s16
|
||||
regl3_1 \op d0 .s32
|
||||
regl3_1 \op d0 .u8
|
||||
regl3_1 \op d0 .u16
|
||||
regl3_1 \op d0 .u32
|
||||
regl3_1 \op "d0[0]" .s16
|
||||
regl3_1 \op "d0[0]" .s32
|
||||
regl3_1 \op "d0[0]" .u16
|
||||
regl3_1 \op "d0[0]" .u32
|
||||
.endm
|
||||
|
||||
long_mac vmlal
|
||||
long_mac vmlsl
|
||||
|
||||
.macro wide_ops op
|
||||
regw3_1 \op d0 .s8
|
||||
regw3_1 \op d0 .s16
|
||||
regw3_1 \op d0 .s32
|
||||
regw3_1 \op d0 .u8
|
||||
regw3_1 \op d0 .u16
|
||||
regw3_1 \op d0 .u32
|
||||
.endm
|
||||
|
||||
wide_ops vaddw
|
||||
wide_ops vsubw
|
||||
|
||||
.macro narr_ops op
|
||||
regn3_1 \op q0 .i16
|
||||
regn3_1 \op q0 .i32
|
||||
regn3_1 \op q0 .i64
|
||||
.endm
|
||||
|
||||
narr_ops vaddhn
|
||||
narr_ops vraddhn
|
||||
narr_ops vsubhn
|
||||
narr_ops vrsubhn
|
||||
|
||||
.macro long_dmac op
|
||||
regl3_1 \op d0 .s16
|
||||
regl3_1 \op d0 .s32
|
||||
regl3_1 \op "d0[0]" .s16
|
||||
regl3_1 \op "d0[0]" .s32
|
||||
.endm
|
||||
|
||||
long_dmac vqdmlal
|
||||
long_dmac vqdmlsl
|
||||
long_dmac vqdmull
|
||||
|
||||
regl3_1 vmull d0 .s8
|
||||
regl3_1 vmull d0 .s16
|
||||
regl3_1 vmull d0 .s32
|
||||
regl3_1 vmull d0 .u8
|
||||
regl3_1 vmull d0 .u16
|
||||
regl3_1 vmull d0 .u32
|
||||
regl3_1 vmull d0 .p8
|
||||
regl3_1 vmull "d0[0]" .s16
|
||||
regl3_1 vmull "d0[0]" .s32
|
||||
regl3_1 vmull "d0[0]" .u16
|
||||
regl3_1 vmull "d0[0]" .u32
|
||||
|
||||
vext.8 q0,q0,q0,0
|
||||
vextq.8 q0,q0,q0,0
|
||||
vext.8 d0,d0,d0,0
|
||||
|
||||
.macro revs op opq vtype
|
||||
\op\vtype q0,q0
|
||||
\opq\vtype q0,q0
|
||||
\op\vtype d0,d0
|
||||
.endm
|
||||
|
||||
revs vrev64 vrev64q .8
|
||||
revs vrev64 vrev64q .16
|
||||
revs vrev64 vrev64q .32
|
||||
revs vrev32 vrev32q .8
|
||||
revs vrev32 vrev32q .16
|
||||
revs vrev16 vrev16q .8
|
||||
|
||||
.macro dups op opq vtype
|
||||
\op\vtype q0,r0
|
||||
\opq\vtype q0,r0
|
||||
\op\vtype d0,r0
|
||||
\op\vtype q0,d0[0]
|
||||
\opq\vtype q0,d0[0]
|
||||
\op\vtype d0,d0[0]
|
||||
.endm
|
||||
|
||||
dups vdup vdupq .8
|
||||
dups vdup vdupq .16
|
||||
dups vdup vdupq .32
|
||||
|
||||
.macro binop_3typ op op1 op2 t1 t2 t3
|
||||
\op\t1 \op1,\op2
|
||||
\op\t2 \op1,\op2
|
||||
\op\t3 \op1,\op2
|
||||
.endm
|
||||
|
||||
binop_3typ vmovl q0 d0 .s8 .s16 .s32
|
||||
binop_3typ vmovl q0 d0 .u8 .u16 .u32
|
||||
binop_3typ vmovn d0 q0 .i16 .i32 .i64
|
||||
binop_3typ vqmovn d0 q0 .s16 .s32 .s64
|
||||
binop_3typ vqmovn d0 q0 .u16 .u32 .u64
|
||||
binop_3typ vqmovun d0 q0 .s16 .s32 .s64
|
||||
|
||||
.macro binops op opq vtype="" rhs="0"
|
||||
\op\vtype q0,q\rhs
|
||||
\opq\vtype q0,q\rhs
|
||||
\op\vtype d0,d\rhs
|
||||
.endm
|
||||
|
||||
.macro regs2_sz_32 op opq
|
||||
binops \op \opq .8 1
|
||||
binops \op \opq .16 1
|
||||
binops \op \opq .32 1
|
||||
.endm
|
||||
|
||||
regs2_sz_32 vzip vzipq
|
||||
regs2_sz_32 vuzp vuzpq
|
||||
|
||||
.macro regs2_s_32 op opq
|
||||
binops \op \opq .s8
|
||||
binops \op \opq .s16
|
||||
binops \op \opq .s32
|
||||
.endm
|
||||
|
||||
regs2_s_32 vqabs vqabsq
|
||||
regs2_s_32 vqneg vqnegq
|
||||
|
||||
.macro regs2_su_32 op opq
|
||||
regs2_s_32 \op \opq
|
||||
binops \op \opq .u8
|
||||
binops \op \opq .u16
|
||||
binops \op \opq .u32
|
||||
.endm
|
||||
|
||||
regs2_su_32 vpadal vpadalq
|
||||
regs2_su_32 vpaddl vpaddlq
|
||||
|
||||
binops vrecpe vrecpeq .u32
|
||||
binops vrecpe vrecpeq .f32
|
||||
binops vrsqrte vrsqrteq .u32
|
||||
binops vrsqrte vrsqrteq .f32
|
||||
|
||||
regs2_s_32 vcls vclsq
|
||||
|
||||
.macro regs2_i_32 op opq
|
||||
binops \op \opq .i8
|
||||
binops \op \opq .i16
|
||||
binops \op \opq .i32
|
||||
.endm
|
||||
|
||||
regs2_i_32 vclz vclzq
|
||||
|
||||
binops vcnt vcntq .8
|
||||
|
||||
binops vswp vswpq "" 1
|
||||
|
||||
regs2_sz_32 vtrn vtrnq
|
||||
|
||||
vtbl.8 d0,{d0},d0
|
||||
vtbx.8 d0,{d0},d0
|
||||
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
# name: Neon element and structure loads and stores
|
||||
# as: -mfpu=neon
|
||||
# objdump: -dr --prefix-addresses --show-raw-insn
|
||||
|
||||
.*: +file format .*arm.*
|
||||
|
||||
Disassembly of section \.text:
|
||||
0[0-9a-f]+ <[^>]+> f406282f vst2\.8 {d2-d3}, \[r6, :128\]
|
||||
0[0-9a-f]+ <[^>]+> f427140d vld3\.8 {d1-d3}, \[r7\]!
|
||||
0[0-9a-f]+ <[^>]+> f4091553 vst3\.16 {d1,d3,d5}, \[r9, :64\], r3
|
||||
0[0-9a-f]+ <[^>]+> f42a208f vld4\.32 {d2-d5}, \[sl\]
|
||||
0[0-9a-f]+ <[^>]+> f40a114f vst4\.16 {d1,d3,d5,d7}, \[sl\]
|
||||
0[0-9a-f]+ <[^>]+> f4aa1c6f vld1\.16 {d1\[\]-d2\[\]}, \[sl\]
|
||||
0[0-9a-f]+ <[^>]+> f4aa1c5f vld1\.16 {d1\[\]}, \[sl, :16\]
|
||||
0[0-9a-f]+ <[^>]+> f4aa1dbf vld2\.32 {d1\[\],d3\[\]}, \[sl, :64\]
|
||||
0[0-9a-f]+ <[^>]+> f4aa3e0c vld3\.8 {d3\[\]-d5\[\]}, \[sl\], ip
|
||||
0[0-9a-f]+ <[^>]+> f4a9af6d vld4\.16 {d10\[\],d12\[\],d14\[\],d16\[\]}, \[r9\]!
|
||||
0[0-9a-f]+ <[^>]+> f4a9af5f vld4\.16 {d10\[\]-d13\[\]}, \[r9, :64\]
|
||||
0[0-9a-f]+ <[^>]+> f4a9af9f vld4\.32 {d10\[\]-d13\[\]}, \[r9, :64\]
|
||||
0[0-9a-f]+ <[^>]+> f4a9afdf vld4\.32 {d10\[\]-d13\[\]}, \[r9, :128\]
|
||||
0[0-9a-f]+ <[^>]+> f4a530ed vld1\.8 {d3\[7\]}, \[r5\]!
|
||||
0[0-9a-f]+ <[^>]+> f48554df vst1\.16 {d5\[3\]}, \[r5, :16\]
|
||||
0[0-9a-f]+ <[^>]+> f4a535dd vld2\.16 {d3\[3\],d4\[3\]}, \[r5, :32\]!
|
||||
0[0-9a-f]+ <[^>]+> f4858a83 vst3\.32 {d8\[1\],d9\[1\],d10\[1\]}, \[r5\], r3
|
||||
0[0-9a-f]+ <[^>]+> f4a7804f vld1\.8 {d8\[2\]}, \[r7\]
|
||||
0[0-9a-f]+ <[^>]+> f4a7848f vld1\.16 {d8\[2\]}, \[r7\]
|
||||
0[0-9a-f]+ <[^>]+> f4a7849f vld1\.16 {d8\[2\]}, \[r7, :16\]
|
||||
0[0-9a-f]+ <[^>]+> f4a7888f vld1\.32 {d8\[1\]}, \[r7\]
|
||||
0[0-9a-f]+ <[^>]+> f4a788bf vld1\.32 {d8\[1\]}, \[r7, :32\]
|
||||
0[0-9a-f]+ <[^>]+> f4a7812f vld2\.8 {d8\[1\],d9\[1\]}, \[r7\]
|
||||
0[0-9a-f]+ <[^>]+> f4a7813f vld2\.8 {d8\[1\],d9\[1\]}, \[r7, :16\]
|
||||
0[0-9a-f]+ <[^>]+> f4a7854f vld2\.16 {d8\[1\],d9\[1\]}, \[r7\]
|
||||
0[0-9a-f]+ <[^>]+> f4a7855f vld2\.16 {d8\[1\],d9\[1\]}, \[r7, :32\]
|
||||
0[0-9a-f]+ <[^>]+> f4a7856f vld2\.16 {d8\[1\],d10\[1\]}, \[r7\]
|
||||
0[0-9a-f]+ <[^>]+> f4a7857f vld2\.16 {d8\[1\],d10\[1\]}, \[r7, :32\]
|
||||
0[0-9a-f]+ <[^>]+> f4a7898f vld2\.32 {d8\[1\],d9\[1\]}, \[r7\]
|
||||
0[0-9a-f]+ <[^>]+> f4a7899f vld2\.32 {d8\[1\],d9\[1\]}, \[r7, :64\]
|
||||
0[0-9a-f]+ <[^>]+> f4a789cf vld2\.32 {d8\[1\],d10\[1\]}, \[r7\]
|
||||
0[0-9a-f]+ <[^>]+> f4a789df vld2\.32 {d8\[1\],d10\[1\]}, \[r7, :64\]
|
||||
0[0-9a-f]+ <[^>]+> f4a7822f vld3\.8 {d8\[1\],d9\[1\],d10\[1\]}, \[r7\]
|
||||
0[0-9a-f]+ <[^>]+> f4a7864f vld3\.16 {d8\[1\],d9\[1\],d10\[1\]}, \[r7\]
|
||||
0[0-9a-f]+ <[^>]+> f4a7866f vld3\.16 {d8\[1\],d10\[1\],d12\[1\]}, \[r7\]
|
||||
0[0-9a-f]+ <[^>]+> f4a78a8f vld3\.32 {d8\[1\],d9\[1\],d10\[1\]}, \[r7\]
|
||||
0[0-9a-f]+ <[^>]+> f4a78acf vld3\.32 {d8\[1\],d10\[1\],d12\[1\]}, \[r7\]
|
||||
0[0-9a-f]+ <[^>]+> f4a7834f vld4\.8 {d8\[2\],d9\[2\],d10\[2\],d11\[2\]}, \[r7\]
|
||||
0[0-9a-f]+ <[^>]+> f4a7835f vld4\.8 {d8\[2\],d9\[2\],d10\[2\],d11\[2\]}, \[r7, :32\]
|
||||
0[0-9a-f]+ <[^>]+> f4a7876f vld4\.16 {d8\[1\],d10\[1\],d12\[1\],d14\[1\]}, \[r7\]
|
||||
0[0-9a-f]+ <[^>]+> f4a7875f vld4\.16 {d8\[1\],d9\[1\],d10\[1\],d11\[1\]}, \[r7, :64\]
|
||||
0[0-9a-f]+ <[^>]+> f4a78bcf vld4\.32 {d8\[1\],d10\[1\],d12\[1\],d14\[1\]}, \[r7\]
|
||||
0[0-9a-f]+ <[^>]+> f4a78bdf vld4\.32 {d8\[1\],d10\[1\],d12\[1\],d14\[1\]}, \[r7, :64\]
|
||||
0[0-9a-f]+ <[^>]+> f4a78bef vld4\.32 {d8\[1\],d10\[1\],d12\[1\],d14\[1\]}, \[r7, :128\]
|
||||
0[0-9a-f]+ <[^>]+> f3b43805 vtbl\.8 d3, {d4}, d5
|
||||
0[0-9a-f]+ <[^>]+> f3b23b05 vtbl\.8 d3, {d2-d5}, d5
|
||||
0[0-9a-f]+ <[^>]+> f3be3985 vtbl\.8 d3, {d30-d31}, d5
|
||||
0[0-9a-f]+ <[^>]+> f427288f vld2\.32 {d2-d3}, \[r7\]
|
||||
0[0-9a-f]+ <[^>]+> f427208f vld4\.32 {d2-d5}, \[r7\]
|
||||
0[0-9a-f]+ <[^>]+> f467c08f vld4\.32 {d28-d31}, \[r7\]
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
@ test element and structure loads and stores.
|
||||
|
||||
.text
|
||||
.arm
|
||||
.syntax unified
|
||||
|
||||
vst2.8 {d2,d3},[r6,:128]
|
||||
vld3.8 {d1,d2,d3},[r7]!
|
||||
vst3.16 {d1,d3,d5},[r9,:64],r3
|
||||
vld4.32 {d2,d3,d4,d5},[r10]
|
||||
vst4.16 {d1,d3,d5,d7},[r10]
|
||||
vld1.16 {d1[],d2[]},[r10]
|
||||
vld1.16 {d1[]},[r10,:16]
|
||||
vld2.32 {d1[],d3[]},[r10,:64]
|
||||
vld3.s8 {d3[],d4[],d5[]},[r10],r12
|
||||
vld4.16 {d10[],d12[],d14[],d16[]},[r9]!
|
||||
vld4.16 {d10[],d11[],d12[],d13[]},[r9,:64]
|
||||
vld4.32 {d10[],d11[],d12[],d13[]},[r9,:64]
|
||||
vld4.32 {d10[],d11[],d12[],d13[]},[r9,:128]
|
||||
vld1.8 {d3[7]},[r5]!
|
||||
vst1.16 {d5[3]},[r5,:16]
|
||||
vld2.16 {d3[3],d4[3]},[r5,:32]!
|
||||
vst3.32 {d8[1],d9[1],d10[1]},[r5],r3
|
||||
|
||||
vld1.8 {d8[2]},[r7]
|
||||
vld1.16 {d8[2]},[r7]
|
||||
vld1.16 {d8[2]},[r7,:16]
|
||||
vld1.32 {d8[1]},[r7]
|
||||
vld1.32 {d8[1]},[r7,:32]
|
||||
vld2.8 {d8[1],d9[1]},[r7]
|
||||
vld2.8 {d8[1],d9[1]},[r7,:16]
|
||||
vld2.16 {d8[1],d9[1]},[r7]
|
||||
vld2.16 {d8[1],d9[1]},[r7,:32]
|
||||
vld2.16 {d8[1],d10[1]},[r7]
|
||||
vld2.16 {d8[1],d10[1]},[r7,:32]
|
||||
vld2.32 {d8[1],d9[1]},[r7]
|
||||
vld2.32 {d8[1],d9[1]},[r7,:64]
|
||||
vld2.32 {d8[1],d10[1]},[r7]
|
||||
vld2.32 {d8[1],d10[1]},[r7,:64]
|
||||
vld3.8 {d8[1],d9[1],d10[1]},[r7]
|
||||
vld3.16 {d8[1],d9[1],d10[1]},[r7]
|
||||
vld3.16 {d8[1],d10[1],d12[1]},[r7]
|
||||
vld3.32 {d8[1],d9[1],d10[1]},[r7]
|
||||
vld3.32 {d8[1],d10[1],d12[1]},[r7]
|
||||
vld4.8 {d8[2],d9[2],d10[2],d11[2]},[r7]
|
||||
vld4.8 {d8[2],d9[2],d10[2],d11[2]},[r7,:32]
|
||||
vld4.16 {d8[1],d10[1],d12[1],d14[1]},[r7]
|
||||
vld4.16 {d8[1],d9[1],d10[1],d11[1]},[r7,:64]
|
||||
vld4.32 {d8[1],d10[1],d12[1],d14[1]},[r7]
|
||||
vld4.32 {d8[1],d10[1],d12[1],d14[1]},[r7,:64]
|
||||
vld4.32 {d8[1],d10[1],d12[1],d14[1]},[r7,:128]
|
||||
|
||||
vtbl.8 d3,{d4},d5
|
||||
vtbl.8 d3,{q1-q2},d5
|
||||
vtbl.8 d3,{q15},d5
|
||||
|
||||
vld2.32 {q1},[r7]
|
||||
vld4.32 {q1-q2},[r7]
|
||||
vld4.32 {q14-q15},[r7]
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
# name: Neon single and multiple register loads and stores
|
||||
# as: -mfpu=neon
|
||||
# objdump: -dr --prefix-addresses --show-raw-insn
|
||||
|
||||
.*: +file format .*arm.*
|
||||
|
||||
Disassembly of section \.text:
|
||||
0[0-9a-f]+ <[^>]+> ec922b02 vldmia r2, {d2}
|
||||
0[0-9a-f]+ <[^>]+> ec922b04 vldmia r2, {d2-d3}
|
||||
0[0-9a-f]+ <[^>]+> ec924b08 vldmia r2, {d4-d7}
|
||||
0[0-9a-f]+ <[^>]+> ecd28b10 vldmia r2, {d24-d31}
|
||||
0[0-9a-f]+ <[^>]+> ec923b20 vldmia r2, {d3-d18}
|
||||
0[0-9a-f]+ <[^>]+> ec922b02 vldmia r2, {d2}
|
||||
0[0-9a-f]+ <[^>]+> ec922b04 vldmia r2, {d2-d3}
|
||||
0[0-9a-f]+ <[^>]+> ec924b08 vldmia r2, {d4-d7}
|
||||
0[0-9a-f]+ <[^>]+> ecd28b10 vldmia r2, {d24-d31}
|
||||
0[0-9a-f]+ <[^>]+> ec923b20 vldmia r2, {d3-d18}
|
||||
0[0-9a-f]+ <[^>]+> ecb22b02 vldmia r2!, {d2}
|
||||
0[0-9a-f]+ <[^>]+> ecb22b04 vldmia r2!, {d2-d3}
|
||||
0[0-9a-f]+ <[^>]+> ecb24b08 vldmia r2!, {d4-d7}
|
||||
0[0-9a-f]+ <[^>]+> ecf28b10 vldmia r2!, {d24-d31}
|
||||
0[0-9a-f]+ <[^>]+> ecb23b20 vldmia r2!, {d3-d18}
|
||||
0[0-9a-f]+ <[^>]+> ed322b02 vldmdb r2!, {d2}
|
||||
0[0-9a-f]+ <[^>]+> ed322b04 vldmdb r2!, {d2-d3}
|
||||
0[0-9a-f]+ <[^>]+> ed324b08 vldmdb r2!, {d4-d7}
|
||||
0[0-9a-f]+ <[^>]+> ed728b10 vldmdb r2!, {d24-d31}
|
||||
0[0-9a-f]+ <[^>]+> ed323b20 vldmdb r2!, {d3-d18}
|
||||
0[0-9a-f]+ <[^>]+> ec822b02 vstmia r2, {d2}
|
||||
0[0-9a-f]+ <[^>]+> ec822b04 vstmia r2, {d2-d3}
|
||||
0[0-9a-f]+ <[^>]+> ec824b08 vstmia r2, {d4-d7}
|
||||
0[0-9a-f]+ <[^>]+> ecc28b10 vstmia r2, {d24-d31}
|
||||
0[0-9a-f]+ <[^>]+> ec823b20 vstmia r2, {d3-d18}
|
||||
0[0-9a-f]+ <[^>]+> ec822b02 vstmia r2, {d2}
|
||||
0[0-9a-f]+ <[^>]+> ec822b04 vstmia r2, {d2-d3}
|
||||
0[0-9a-f]+ <[^>]+> ec824b08 vstmia r2, {d4-d7}
|
||||
0[0-9a-f]+ <[^>]+> ecc28b10 vstmia r2, {d24-d31}
|
||||
0[0-9a-f]+ <[^>]+> ec823b20 vstmia r2, {d3-d18}
|
||||
0[0-9a-f]+ <[^>]+> eca22b02 vstmia r2!, {d2}
|
||||
0[0-9a-f]+ <[^>]+> eca22b04 vstmia r2!, {d2-d3}
|
||||
0[0-9a-f]+ <[^>]+> eca24b08 vstmia r2!, {d4-d7}
|
||||
0[0-9a-f]+ <[^>]+> ece28b10 vstmia r2!, {d24-d31}
|
||||
0[0-9a-f]+ <[^>]+> eca23b20 vstmia r2!, {d3-d18}
|
||||
0[0-9a-f]+ <[^>]+> ed222b02 vstmdb r2!, {d2}
|
||||
0[0-9a-f]+ <[^>]+> ed222b04 vstmdb r2!, {d2-d3}
|
||||
0[0-9a-f]+ <[^>]+> ed224b08 vstmdb r2!, {d4-d7}
|
||||
0[0-9a-f]+ <[^>]+> ed628b10 vstmdb r2!, {d24-d31}
|
||||
0[0-9a-f]+ <[^>]+> ed223b20 vstmdb r2!, {d3-d18}
|
||||
0[0-9a-f]+ <backward> 000001f4 streqd r0, \[r0\], -r4
|
||||
0[0-9a-f]+ <[^>]+> eddf6b0b vldr d22, \[pc, #44\] ; 0[0-9a-f]+ <forward>
|
||||
0[0-9a-f]+ <[^>]+> ed935b00 vldr d5, \[r3\]
|
||||
0[0-9a-f]+ <[^>]+> ed135b01 vldr d5, \[r3, #-4\]
|
||||
0[0-9a-f]+ <[^>]+> ed935b01 vldr d5, \[r3, #4\]
|
||||
0[0-9a-f]+ <[^>]+> ed835b00 vstr d5, \[r3\]
|
||||
0[0-9a-f]+ <[^>]+> ed035b01 vstr d5, \[r3, #-4\]
|
||||
0[0-9a-f]+ <[^>]+> ed835b01 vstr d5, \[r3, #4\]
|
||||
0[0-9a-f]+ <[^>]+> ed935b00 vldr d5, \[r3\]
|
||||
0[0-9a-f]+ <[^>]+> ed135b40 vldr d5, \[r3, #-256\]
|
||||
0[0-9a-f]+ <[^>]+> ed935b40 vldr d5, \[r3, #256\]
|
||||
0[0-9a-f]+ <[^>]+> ed835b00 vstr d5, \[r3\]
|
||||
0[0-9a-f]+ <[^>]+> ed035b40 vstr d5, \[r3, #-256\]
|
||||
0[0-9a-f]+ <[^>]+> ed835b40 vstr d5, \[r3, #256\]
|
||||
0[0-9a-f]+ <forward> 000002bc streqh r0, \[r0\], -ip
|
||||
0[0-9a-f]+ <[^>]+> ed1f7b11 vldr d7, \[pc, #-68\] ; 0[0-9a-f]+ <backward>
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
@ test register and multi-register loads and stores.
|
||||
|
||||
.text
|
||||
.arm
|
||||
.syntax unified
|
||||
|
||||
.macro multi op dir="" wb=""
|
||||
\op\dir r2\wb,{d2}
|
||||
\op\dir r2\wb,{d2-d3}
|
||||
\op\dir r2\wb,{q2-q3}
|
||||
\op\dir r2\wb,{q12-q14,q15}
|
||||
\op\dir r2\wb,{d3,d4,d5-d8,d9,d10,d11,d12-d16,d17-d18}
|
||||
.endm
|
||||
|
||||
multi vldm
|
||||
multi vldm ia
|
||||
multi vldm ia "!"
|
||||
multi vldm db "!"
|
||||
|
||||
multi vstm
|
||||
multi vstm ia
|
||||
multi vstm ia "!"
|
||||
multi vstm db "!"
|
||||
|
||||
backward:
|
||||
.word 500
|
||||
|
||||
.macro single op offset=""
|
||||
\op d5,[r3]
|
||||
\op d5,[r3,#-\offset]
|
||||
\op d5,[r3,#\offset]
|
||||
.endm
|
||||
|
||||
vldr d22, forward
|
||||
|
||||
single vldr 4
|
||||
single vstr 4
|
||||
single vldr 256
|
||||
single vstr 256
|
||||
|
||||
forward:
|
||||
.word 700
|
||||
|
||||
vldr d7, backward
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
# name: Neon optional register operands
|
||||
# as: -mfpu=neon
|
||||
# objdump: -dr --prefix-addresses --show-raw-insn
|
||||
|
||||
.*: +file format .*arm.*
|
||||
|
||||
Disassembly of section .text:
|
||||
0[0-9a-f]+ <[^>]+> f3022746 vabd\.u8 q1, q1, q3
|
||||
0[0-9a-f]+ <[^>]+> f26cc0c6 vhadd\.s32 q14, q14, q3
|
||||
0[0-9a-f]+ <[^>]+> f2222144 vrhadd\.s32 q1, q1, q2
|
||||
0[0-9a-f]+ <[^>]+> f22aa24e vhsub\.s32 q5, q5, q7
|
||||
0[0-9a-f]+ <[^>]+> f3166448 vshl\.u16 q3, q3, q4
|
||||
0[0-9a-f]+ <[^>]+> f32aa45c vqshl\.u32 q5, q5, q6
|
||||
0[0-9a-f]+ <[^>]+> f20ee170 vand q7, q7, q8
|
||||
0[0-9a-f]+ <[^>]+> f30ee170 veor q7, q7, q8
|
||||
0[0-9a-f]+ <[^>]+> f3b5a14a vceq\.i16 q5, q5, #0
|
||||
0[0-9a-f]+ <[^>]+> f31aa85a vceq\.i16 q5, q5, q5
|
||||
0[0-9a-f]+ <[^>]+> f3b5a24a vclt\.s16 q5, q5, #0
|
||||
0[0-9a-f]+ <[^>]+> f3b5a34c vabs\.s16 q5, q6
|
||||
0[0-9a-f]+ <[^>]+> f3b57388 vneg\.s16 d7, d8
|
||||
0[0-9a-f]+ <[^>]+> f3b97708 vabs\.f32 d7, d8
|
||||
0[0-9a-f]+ <[^>]+> f3f927e4 vneg\.f32 q9, q10
|
||||
0[0-9a-f]+ <[^>]+> f2211a03 vpmax\.s32 d1, d1, d3
|
||||
0[0-9a-f]+ <[^>]+> f2255a17 vpmin\.s32 d5, d5, d7
|
||||
0[0-9a-f]+ <[^>]+> f3011f03 vpmax\.f32 d1, d1, d3
|
||||
0[0-9a-f]+ <[^>]+> f3255f07 vpmin\.f32 d5, d5, d7
|
||||
0[0-9a-f]+ <[^>]+> f2122b46 vqdmulh\.s16 q1, q1, q3
|
||||
0[0-9a-f]+ <[^>]+> f3255b07 vqrdmulh\.s32 d5, d5, d7
|
||||
0[0-9a-f]+ <[^>]+> f3922c6d vqdmulh\.s16 q1, q1, d5\[3\]
|
||||
0[0-9a-f]+ <[^>]+> f2122056 vqadd\.s16 q1, q1, q3
|
||||
0[0-9a-f]+ <[^>]+> f2255017 vqadd\.s32 d5, d5, d7
|
||||
0[0-9a-f]+ <[^>]+> f2222944 vmla\.i32 q1, q1, q2
|
||||
0[0-9a-f]+ <[^>]+> f2133b14 vpadd\.i16 d3, d3, d4
|
||||
0[0-9a-f]+ <[^>]+> f3266948 vmls\.i32 q3, q3, q4
|
||||
0[0-9a-f]+ <[^>]+> f3022e54 vacge\.f32 q1, q1, q2
|
||||
0[0-9a-f]+ <[^>]+> f3266e58 vacgt\.f32 q3, q3, q4
|
||||
0[0-9a-f]+ <[^>]+> f30cae5a vacge\.f32 q5, q6, q5
|
||||
0[0-9a-f]+ <[^>]+> f320eede vacgt\.f32 q7, q8, q7
|
||||
0[0-9a-f]+ <[^>]+> f32ee370 vcge\.u32 q7, q7, q8
|
||||
0[0-9a-f]+ <[^>]+> f320e3de vcge\.u32 q7, q8, q7
|
||||
0[0-9a-f]+ <[^>]+> f3a22102 vaddw\.u32 q1, q1, d2
|
||||
0[0-9a-f]+ <[^>]+> f2a66304 vsubw\.s32 q3, q3, d4
|
||||
0[0-9a-f]+ <[^>]+> f2244856 vtst\.32 q2, q2, q3
|
||||
0[0-9a-f]+ <[^>]+> f2011f12 vrecps\.f32 d1, d1, d2
|
||||
0[0-9a-f]+ <[^>]+> f29c2052 vshr\.s16 q1, q1, #4
|
||||
0[0-9a-f]+ <[^>]+> f28b4254 vrshr\.s8 q2, q2, #5
|
||||
0[0-9a-f]+ <[^>]+> f39a6156 vsra\.u16 q3, q3, #6
|
||||
0[0-9a-f]+ <[^>]+> f39a8358 vrsra\.u16 q4, q4, #6
|
||||
0[0-9a-f]+ <[^>]+> f3954554 vsli\.16 q2, q2, #5
|
||||
0[0-9a-f]+ <[^>]+> f3bff69f vqshlu\.s64 d15, d15, #63
|
||||
0[0-9a-f]+ <[^>]+> f2b55306 vext\.8 d5, d5, d6, #3
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
@ test omitted optional arguments
|
||||
|
||||
.text
|
||||
.arm
|
||||
.syntax unified
|
||||
|
||||
vabd.u8 q1,q3
|
||||
vhadd.s32 q14, q3
|
||||
vrhadd.s32 q1,q2
|
||||
vhsub.s32 q5,q7
|
||||
vshl.u16 q3,q4
|
||||
vqshl.u32 q5,q6
|
||||
vand.64 q7,q8
|
||||
veor.64 q7,q8
|
||||
vceq.i16 q5,#0
|
||||
vceq.i16 q5,q5
|
||||
vclt.s16 q5,#0
|
||||
vabs.s16 q5,q6
|
||||
vneg.s16 d7,d8
|
||||
vabs.f d7,d8
|
||||
vneg.f q9,q10
|
||||
vpmax.s32 d1,d3
|
||||
vpmin.s32 d5,d7
|
||||
vpmax.f32 d1,d3
|
||||
vpmin.f32 d5,d7
|
||||
vqdmulh.s16 q1,q3
|
||||
vqrdmulh.s32 d5,d7
|
||||
vqdmulh.s16 q1,d5[3]
|
||||
vqadd.s16 q1,q3
|
||||
vqadd.s32 d5,d7
|
||||
vmla.i32 q1,q2
|
||||
vpadd.i16 d3,d4
|
||||
vmls.s32 q3,q4
|
||||
vacge.f q1,q2
|
||||
vacgt.f q3,q4
|
||||
vaclt.f q5,q6
|
||||
vacle.f q7,q8
|
||||
vcge.u32 q7,q8
|
||||
vclt.u32 q7,q8
|
||||
vaddw.u32 q1,d2
|
||||
vsubw.s32 q3,d4
|
||||
vtst.i32 q2,q3
|
||||
vrecps.f d1,d2
|
||||
vshr.s16 q1,#4
|
||||
vrshr.s8 q2,#5
|
||||
vsra.u16 q3,#6
|
||||
vrsra.u16 q4,#6
|
||||
vsli.16 q2,#5
|
||||
vqshlu.s64 d15,#63
|
||||
vext.8 d5,d6,#3
|
||||
|
|
@ -24,20 +24,20 @@ Disassembly of section .text:
|
|||
0+038 <[^>]*> ee100b40 fnmscd d0, d0, d0
|
||||
0+03c <[^>]*> ee200b40 fnmuld d0, d0, d0
|
||||
0+040 <[^>]*> ee300b40 fsubd d0, d0, d0
|
||||
0+044 <[^>]*> ed900b00 fldd d0, \[r0\]
|
||||
0+048 <[^>]*> ed800b00 fstd d0, \[r0\]
|
||||
0+04c <[^>]*> ec900b02 fldmiad r0, {d0}
|
||||
0+050 <[^>]*> ec900b02 fldmiad r0, {d0}
|
||||
0+054 <[^>]*> ecb00b02 fldmiad r0!, {d0}
|
||||
0+058 <[^>]*> ecb00b02 fldmiad r0!, {d0}
|
||||
0+05c <[^>]*> ed300b02 fldmdbd r0!, {d0}
|
||||
0+060 <[^>]*> ed300b02 fldmdbd r0!, {d0}
|
||||
0+064 <[^>]*> ec800b02 fstmiad r0, {d0}
|
||||
0+068 <[^>]*> ec800b02 fstmiad r0, {d0}
|
||||
0+06c <[^>]*> eca00b02 fstmiad r0!, {d0}
|
||||
0+070 <[^>]*> eca00b02 fstmiad r0!, {d0}
|
||||
0+074 <[^>]*> ed200b02 fstmdbd r0!, {d0}
|
||||
0+078 <[^>]*> ed200b02 fstmdbd r0!, {d0}
|
||||
0+044 <[^>]*> ed900b00 vldr d0, \[r0\]
|
||||
0+048 <[^>]*> ed800b00 vstr d0, \[r0\]
|
||||
0+04c <[^>]*> ec900b02 vldmia r0, {d0}
|
||||
0+050 <[^>]*> ec900b02 vldmia r0, {d0}
|
||||
0+054 <[^>]*> ecb00b02 vldmia r0!, {d0}
|
||||
0+058 <[^>]*> ecb00b02 vldmia r0!, {d0}
|
||||
0+05c <[^>]*> ed300b02 vldmdb r0!, {d0}
|
||||
0+060 <[^>]*> ed300b02 vldmdb r0!, {d0}
|
||||
0+064 <[^>]*> ec800b02 vstmia r0, {d0}
|
||||
0+068 <[^>]*> ec800b02 vstmia r0, {d0}
|
||||
0+06c <[^>]*> eca00b02 vstmia r0!, {d0}
|
||||
0+070 <[^>]*> eca00b02 vstmia r0!, {d0}
|
||||
0+074 <[^>]*> ed200b02 vstmdb r0!, {d0}
|
||||
0+078 <[^>]*> ed200b02 vstmdb r0!, {d0}
|
||||
0+07c <[^>]*> eeb80bc0 fsitod d0, s0
|
||||
0+080 <[^>]*> eeb80b40 fuitod d0, s0
|
||||
0+084 <[^>]*> eebd0b40 ftosid s0, d0
|
||||
|
|
@ -46,10 +46,10 @@ Disassembly of section .text:
|
|||
0+090 <[^>]*> eebc0bc0 ftouizd s0, d0
|
||||
0+094 <[^>]*> eeb70ac0 fcvtds d0, s0
|
||||
0+098 <[^>]*> eeb70bc0 fcvtsd s0, d0
|
||||
0+09c <[^>]*> ee300b10 fmrdh r0, d0
|
||||
0+0a0 <[^>]*> ee100b10 fmrdl r0, d0
|
||||
0+0a4 <[^>]*> ee200b10 fmdhr d0, r0
|
||||
0+0a8 <[^>]*> ee000b10 fmdlr d0, r0
|
||||
0+09c <[^>]*> ee300b10 vmov\.32 r0, d0\[1\]
|
||||
0+0a0 <[^>]*> ee100b10 vmov\.32 r0, d0\[0\]
|
||||
0+0a4 <[^>]*> ee200b10 vmov\.32 d0\[1\], r0
|
||||
0+0a8 <[^>]*> ee000b10 vmov\.32 d0\[0\], r0
|
||||
0+0ac <[^>]*> eeb51b40 fcmpzd d1
|
||||
0+0b0 <[^>]*> eeb52b40 fcmpzd d2
|
||||
0+0b4 <[^>]*> eeb5fb40 fcmpzd d15
|
||||
|
|
@ -89,46 +89,46 @@ Disassembly of section .text:
|
|||
0+13c <[^>]*> eeb70bc1 fcvtsd s0, d1
|
||||
0+140 <[^>]*> eeb70bc2 fcvtsd s0, d2
|
||||
0+144 <[^>]*> eeb70bcf fcvtsd s0, d15
|
||||
0+148 <[^>]*> ee301b10 fmrdh r1, d0
|
||||
0+14c <[^>]*> ee30eb10 fmrdh lr, d0
|
||||
0+150 <[^>]*> ee310b10 fmrdh r0, d1
|
||||
0+154 <[^>]*> ee320b10 fmrdh r0, d2
|
||||
0+158 <[^>]*> ee3f0b10 fmrdh r0, d15
|
||||
0+15c <[^>]*> ee101b10 fmrdl r1, d0
|
||||
0+160 <[^>]*> ee10eb10 fmrdl lr, d0
|
||||
0+164 <[^>]*> ee110b10 fmrdl r0, d1
|
||||
0+168 <[^>]*> ee120b10 fmrdl r0, d2
|
||||
0+16c <[^>]*> ee1f0b10 fmrdl r0, d15
|
||||
0+170 <[^>]*> ee201b10 fmdhr d0, r1
|
||||
0+174 <[^>]*> ee20eb10 fmdhr d0, lr
|
||||
0+178 <[^>]*> ee210b10 fmdhr d1, r0
|
||||
0+17c <[^>]*> ee220b10 fmdhr d2, r0
|
||||
0+180 <[^>]*> ee2f0b10 fmdhr d15, r0
|
||||
0+184 <[^>]*> ee001b10 fmdlr d0, r1
|
||||
0+188 <[^>]*> ee00eb10 fmdlr d0, lr
|
||||
0+18c <[^>]*> ee010b10 fmdlr d1, r0
|
||||
0+190 <[^>]*> ee020b10 fmdlr d2, r0
|
||||
0+194 <[^>]*> ee0f0b10 fmdlr d15, r0
|
||||
0+198 <[^>]*> ed910b00 fldd d0, \[r1\]
|
||||
0+19c <[^>]*> ed9e0b00 fldd d0, \[lr\]
|
||||
0+1a0 <[^>]*> ed900b00 fldd d0, \[r0\]
|
||||
0+1a4 <[^>]*> ed900bff fldd d0, \[r0, #1020\]
|
||||
0+1a8 <[^>]*> ed100bff fldd d0, \[r0, #-1020\]
|
||||
0+1ac <[^>]*> ed901b00 fldd d1, \[r0\]
|
||||
0+1b0 <[^>]*> ed902b00 fldd d2, \[r0\]
|
||||
0+1b4 <[^>]*> ed90fb00 fldd d15, \[r0\]
|
||||
0+1b8 <[^>]*> ed8ccbc9 fstd d12, \[ip, #804\]
|
||||
0+1bc <[^>]*> ec901b02 fldmiad r0, {d1}
|
||||
0+1c0 <[^>]*> ec902b02 fldmiad r0, {d2}
|
||||
0+1c4 <[^>]*> ec90fb02 fldmiad r0, {d15}
|
||||
0+1c8 <[^>]*> ec900b04 fldmiad r0, {d0-d1}
|
||||
0+1cc <[^>]*> ec900b06 fldmiad r0, {d0-d2}
|
||||
0+1d0 <[^>]*> ec900b20 fldmiad r0, {d0-d15}
|
||||
0+1d4 <[^>]*> ec901b1e fldmiad r0, {d1-d15}
|
||||
0+1d8 <[^>]*> ec902b1c fldmiad r0, {d2-d15}
|
||||
0+1dc <[^>]*> ec90eb04 fldmiad r0, {d14-d15}
|
||||
0+1e0 <[^>]*> ec910b02 fldmiad r1, {d0}
|
||||
0+1e4 <[^>]*> ec9e0b02 fldmiad lr, {d0}
|
||||
0+148 <[^>]*> ee301b10 vmov\.32 r1, d0\[1\]
|
||||
0+14c <[^>]*> ee30eb10 vmov\.32 lr, d0\[1\]
|
||||
0+150 <[^>]*> ee310b10 vmov\.32 r0, d1\[1\]
|
||||
0+154 <[^>]*> ee320b10 vmov\.32 r0, d2\[1\]
|
||||
0+158 <[^>]*> ee3f0b10 vmov\.32 r0, d15\[1\]
|
||||
0+15c <[^>]*> ee101b10 vmov\.32 r1, d0\[0\]
|
||||
0+160 <[^>]*> ee10eb10 vmov\.32 lr, d0\[0\]
|
||||
0+164 <[^>]*> ee110b10 vmov\.32 r0, d1\[0\]
|
||||
0+168 <[^>]*> ee120b10 vmov\.32 r0, d2\[0\]
|
||||
0+16c <[^>]*> ee1f0b10 vmov\.32 r0, d15\[0\]
|
||||
0+170 <[^>]*> ee201b10 vmov\.32 d0\[1\], r1
|
||||
0+174 <[^>]*> ee20eb10 vmov\.32 d0\[1\], lr
|
||||
0+178 <[^>]*> ee210b10 vmov\.32 d1\[1\], r0
|
||||
0+17c <[^>]*> ee220b10 vmov\.32 d2\[1\], r0
|
||||
0+180 <[^>]*> ee2f0b10 vmov\.32 d15\[1\], r0
|
||||
0+184 <[^>]*> ee001b10 vmov\.32 d0\[0\], r1
|
||||
0+188 <[^>]*> ee00eb10 vmov\.32 d0\[0\], lr
|
||||
0+18c <[^>]*> ee010b10 vmov\.32 d1\[0\], r0
|
||||
0+190 <[^>]*> ee020b10 vmov\.32 d2\[0\], r0
|
||||
0+194 <[^>]*> ee0f0b10 vmov\.32 d15\[0\], r0
|
||||
0+198 <[^>]*> ed910b00 vldr d0, \[r1\]
|
||||
0+19c <[^>]*> ed9e0b00 vldr d0, \[lr\]
|
||||
0+1a0 <[^>]*> ed900b00 vldr d0, \[r0\]
|
||||
0+1a4 <[^>]*> ed900bff vldr d0, \[r0, #1020\]
|
||||
0+1a8 <[^>]*> ed100bff vldr d0, \[r0, #-1020\]
|
||||
0+1ac <[^>]*> ed901b00 vldr d1, \[r0\]
|
||||
0+1b0 <[^>]*> ed902b00 vldr d2, \[r0\]
|
||||
0+1b4 <[^>]*> ed90fb00 vldr d15, \[r0\]
|
||||
0+1b8 <[^>]*> ed8ccbc9 vstr d12, \[ip, #804\]
|
||||
0+1bc <[^>]*> ec901b02 vldmia r0, {d1}
|
||||
0+1c0 <[^>]*> ec902b02 vldmia r0, {d2}
|
||||
0+1c4 <[^>]*> ec90fb02 vldmia r0, {d15}
|
||||
0+1c8 <[^>]*> ec900b04 vldmia r0, {d0-d1}
|
||||
0+1cc <[^>]*> ec900b06 vldmia r0, {d0-d2}
|
||||
0+1d0 <[^>]*> ec900b20 vldmia r0, {d0-d15}
|
||||
0+1d4 <[^>]*> ec901b1e vldmia r0, {d1-d15}
|
||||
0+1d8 <[^>]*> ec902b1c vldmia r0, {d2-d15}
|
||||
0+1dc <[^>]*> ec90eb04 vldmia r0, {d14-d15}
|
||||
0+1e0 <[^>]*> ec910b02 vldmia r1, {d0}
|
||||
0+1e4 <[^>]*> ec9e0b02 vldmia lr, {d0}
|
||||
0+1e8 <[^>]*> eeb50b40 fcmpzd d0
|
||||
0+1ec <[^>]*> eeb51b40 fcmpzd d1
|
||||
0+1f0 <[^>]*> eeb52b40 fcmpzd d2
|
||||
|
|
@ -162,20 +162,20 @@ Disassembly of section .text:
|
|||
0+260 <[^>]*> 0e167b4b fnmscdeq d7, d6, d11
|
||||
0+264 <[^>]*> 0e245b4c fnmuldeq d5, d4, d12
|
||||
0+268 <[^>]*> 0e3d3b4e fsubdeq d3, d13, d14
|
||||
0+26c <[^>]*> 0d952b00 flddeq d2, \[r5\]
|
||||
0+270 <[^>]*> 0d8c1b00 fstdeq d1, \[ip\]
|
||||
0+274 <[^>]*> 0c911b02 fldmiadeq r1, {d1}
|
||||
0+278 <[^>]*> 0c922b02 fldmiadeq r2, {d2}
|
||||
0+27c <[^>]*> 0cb33b02 fldmiadeq r3!, {d3}
|
||||
0+280 <[^>]*> 0cb44b02 fldmiadeq r4!, {d4}
|
||||
0+284 <[^>]*> 0d355b02 fldmdbdeq r5!, {d5}
|
||||
0+288 <[^>]*> 0d366b02 fldmdbdeq r6!, {d6}
|
||||
0+28c <[^>]*> 0c87fb02 fstmiadeq r7, {d15}
|
||||
0+290 <[^>]*> 0c88eb02 fstmiadeq r8, {d14}
|
||||
0+294 <[^>]*> 0ca9db02 fstmiadeq r9!, {d13}
|
||||
0+298 <[^>]*> 0caacb02 fstmiadeq sl!, {d12}
|
||||
0+29c <[^>]*> 0d2bbb02 fstmdbdeq fp!, {d11}
|
||||
0+2a0 <[^>]*> 0d2cab02 fstmdbdeq ip!, {d10}
|
||||
0+26c <[^>]*> 0d952b00 vldreq d2, \[r5\]
|
||||
0+270 <[^>]*> 0d8c1b00 vstreq d1, \[ip\]
|
||||
0+274 <[^>]*> 0c911b02 vldmiaeq r1, {d1}
|
||||
0+278 <[^>]*> 0c922b02 vldmiaeq r2, {d2}
|
||||
0+27c <[^>]*> 0cb33b02 vldmiaeq r3!, {d3}
|
||||
0+280 <[^>]*> 0cb44b02 vldmiaeq r4!, {d4}
|
||||
0+284 <[^>]*> 0d355b02 vldmdbeq r5!, {d5}
|
||||
0+288 <[^>]*> 0d366b02 vldmdbeq r6!, {d6}
|
||||
0+28c <[^>]*> 0c87fb02 vstmiaeq r7, {d15}
|
||||
0+290 <[^>]*> 0c88eb02 vstmiaeq r8, {d14}
|
||||
0+294 <[^>]*> 0ca9db02 vstmiaeq r9!, {d13}
|
||||
0+298 <[^>]*> 0caacb02 vstmiaeq sl!, {d12}
|
||||
0+29c <[^>]*> 0d2bbb02 vstmdbeq fp!, {d11}
|
||||
0+2a0 <[^>]*> 0d2cab02 vstmdbeq ip!, {d10}
|
||||
0+2a4 <[^>]*> 0eb8fbe0 fsitodeq d15, s1
|
||||
0+2a8 <[^>]*> 0eb81b6f fuitodeq d1, s31
|
||||
0+2ac <[^>]*> 0efd0b4f ftosideq s1, d15
|
||||
|
|
@ -184,10 +184,10 @@ Disassembly of section .text:
|
|||
0+2b8 <[^>]*> 0efc5bc3 ftouizdeq s11, d3
|
||||
0+2bc <[^>]*> 0eb71ac5 fcvtdseq d1, s10
|
||||
0+2c0 <[^>]*> 0ef75bc1 fcvtsdeq s11, d1
|
||||
0+2c4 <[^>]*> 0e318b10 fmrdheq r8, d1
|
||||
0+2c8 <[^>]*> 0e1f7b10 fmrdleq r7, d15
|
||||
0+2cc <[^>]*> 0e21fb10 fmdhreq d1, pc
|
||||
0+2d0 <[^>]*> 0e0f1b10 fmdlreq d15, r1
|
||||
0+2c4 <[^>]*> 0e318b10 vmoveq\.32 r8, d1\[1\]
|
||||
0+2c8 <[^>]*> 0e1f7b10 vmoveq\.32 r7, d15\[0\]
|
||||
0+2cc <[^>]*> 0e21fb10 vmoveq\.32 d1\[1\], pc
|
||||
0+2d0 <[^>]*> 0e0f1b10 vmoveq\.32 d15\[0\], r1
|
||||
0+2d4 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\)
|
||||
0+2d8 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\)
|
||||
0+2dc <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\)
|
||||
|
|
|
|||
|
|
@ -24,20 +24,20 @@ Disassembly of section .text:
|
|||
0+038 <[^>]*> ee10 0b40 fnmscd d0, d0, d0
|
||||
0+03c <[^>]*> ee20 0b40 fnmuld d0, d0, d0
|
||||
0+040 <[^>]*> ee30 0b40 fsubd d0, d0, d0
|
||||
0+044 <[^>]*> ed90 0b00 fldd d0, \[r0\]
|
||||
0+048 <[^>]*> ed80 0b00 fstd d0, \[r0\]
|
||||
0+04c <[^>]*> ec90 0b02 fldmiad r0, {d0}
|
||||
0+050 <[^>]*> ec90 0b02 fldmiad r0, {d0}
|
||||
0+054 <[^>]*> ecb0 0b02 fldmiad r0!, {d0}
|
||||
0+058 <[^>]*> ecb0 0b02 fldmiad r0!, {d0}
|
||||
0+05c <[^>]*> ed30 0b02 fldmdbd r0!, {d0}
|
||||
0+060 <[^>]*> ed30 0b02 fldmdbd r0!, {d0}
|
||||
0+064 <[^>]*> ec80 0b02 fstmiad r0, {d0}
|
||||
0+068 <[^>]*> ec80 0b02 fstmiad r0, {d0}
|
||||
0+06c <[^>]*> eca0 0b02 fstmiad r0!, {d0}
|
||||
0+070 <[^>]*> eca0 0b02 fstmiad r0!, {d0}
|
||||
0+074 <[^>]*> ed20 0b02 fstmdbd r0!, {d0}
|
||||
0+078 <[^>]*> ed20 0b02 fstmdbd r0!, {d0}
|
||||
0+044 <[^>]*> ed90 0b00 vldr d0, \[r0\]
|
||||
0+048 <[^>]*> ed80 0b00 vstr d0, \[r0\]
|
||||
0+04c <[^>]*> ec90 0b02 vldmia r0, {d0}
|
||||
0+050 <[^>]*> ec90 0b02 vldmia r0, {d0}
|
||||
0+054 <[^>]*> ecb0 0b02 vldmia r0!, {d0}
|
||||
0+058 <[^>]*> ecb0 0b02 vldmia r0!, {d0}
|
||||
0+05c <[^>]*> ed30 0b02 vldmdb r0!, {d0}
|
||||
0+060 <[^>]*> ed30 0b02 vldmdb r0!, {d0}
|
||||
0+064 <[^>]*> ec80 0b02 vstmia r0, {d0}
|
||||
0+068 <[^>]*> ec80 0b02 vstmia r0, {d0}
|
||||
0+06c <[^>]*> eca0 0b02 vstmia r0!, {d0}
|
||||
0+070 <[^>]*> eca0 0b02 vstmia r0!, {d0}
|
||||
0+074 <[^>]*> ed20 0b02 vstmdb r0!, {d0}
|
||||
0+078 <[^>]*> ed20 0b02 vstmdb r0!, {d0}
|
||||
0+07c <[^>]*> eeb8 0bc0 fsitod d0, s0
|
||||
0+080 <[^>]*> eeb8 0b40 fuitod d0, s0
|
||||
0+084 <[^>]*> eebd 0b40 ftosid s0, d0
|
||||
|
|
@ -46,10 +46,10 @@ Disassembly of section .text:
|
|||
0+090 <[^>]*> eebc 0bc0 ftouizd s0, d0
|
||||
0+094 <[^>]*> eeb7 0ac0 fcvtds d0, s0
|
||||
0+098 <[^>]*> eeb7 0bc0 fcvtsd s0, d0
|
||||
0+09c <[^>]*> ee30 0b10 fmrdh r0, d0
|
||||
0+0a0 <[^>]*> ee10 0b10 fmrdl r0, d0
|
||||
0+0a4 <[^>]*> ee20 0b10 fmdhr d0, r0
|
||||
0+0a8 <[^>]*> ee00 0b10 fmdlr d0, r0
|
||||
0+09c <[^>]*> ee30 0b10 vmov\.32 r0, d0\[1\]
|
||||
0+0a0 <[^>]*> ee10 0b10 vmov\.32 r0, d0\[0\]
|
||||
0+0a4 <[^>]*> ee20 0b10 vmov\.32 d0\[1\], r0
|
||||
0+0a8 <[^>]*> ee00 0b10 vmov\.32 d0\[0\], r0
|
||||
0+0ac <[^>]*> eeb5 1b40 fcmpzd d1
|
||||
0+0b0 <[^>]*> eeb5 2b40 fcmpzd d2
|
||||
0+0b4 <[^>]*> eeb5 fb40 fcmpzd d15
|
||||
|
|
@ -89,46 +89,46 @@ Disassembly of section .text:
|
|||
0+13c <[^>]*> eeb7 0bc1 fcvtsd s0, d1
|
||||
0+140 <[^>]*> eeb7 0bc2 fcvtsd s0, d2
|
||||
0+144 <[^>]*> eeb7 0bcf fcvtsd s0, d15
|
||||
0+148 <[^>]*> ee30 1b10 fmrdh r1, d0
|
||||
0+14c <[^>]*> ee30 eb10 fmrdh lr, d0
|
||||
0+150 <[^>]*> ee31 0b10 fmrdh r0, d1
|
||||
0+154 <[^>]*> ee32 0b10 fmrdh r0, d2
|
||||
0+158 <[^>]*> ee3f 0b10 fmrdh r0, d15
|
||||
0+15c <[^>]*> ee10 1b10 fmrdl r1, d0
|
||||
0+160 <[^>]*> ee10 eb10 fmrdl lr, d0
|
||||
0+164 <[^>]*> ee11 0b10 fmrdl r0, d1
|
||||
0+168 <[^>]*> ee12 0b10 fmrdl r0, d2
|
||||
0+16c <[^>]*> ee1f 0b10 fmrdl r0, d15
|
||||
0+170 <[^>]*> ee20 1b10 fmdhr d0, r1
|
||||
0+174 <[^>]*> ee20 eb10 fmdhr d0, lr
|
||||
0+178 <[^>]*> ee21 0b10 fmdhr d1, r0
|
||||
0+17c <[^>]*> ee22 0b10 fmdhr d2, r0
|
||||
0+180 <[^>]*> ee2f 0b10 fmdhr d15, r0
|
||||
0+184 <[^>]*> ee00 1b10 fmdlr d0, r1
|
||||
0+188 <[^>]*> ee00 eb10 fmdlr d0, lr
|
||||
0+18c <[^>]*> ee01 0b10 fmdlr d1, r0
|
||||
0+190 <[^>]*> ee02 0b10 fmdlr d2, r0
|
||||
0+194 <[^>]*> ee0f 0b10 fmdlr d15, r0
|
||||
0+198 <[^>]*> ed91 0b00 fldd d0, \[r1\]
|
||||
0+19c <[^>]*> ed9e 0b00 fldd d0, \[lr\]
|
||||
0+1a0 <[^>]*> ed90 0b00 fldd d0, \[r0\]
|
||||
0+1a4 <[^>]*> ed90 0bff fldd d0, \[r0, #1020\]
|
||||
0+1a8 <[^>]*> ed10 0bff fldd d0, \[r0, #-1020\]
|
||||
0+1ac <[^>]*> ed90 1b00 fldd d1, \[r0\]
|
||||
0+1b0 <[^>]*> ed90 2b00 fldd d2, \[r0\]
|
||||
0+1b4 <[^>]*> ed90 fb00 fldd d15, \[r0\]
|
||||
0+1b8 <[^>]*> ed8c cbc9 fstd d12, \[ip, #804\]
|
||||
0+1bc <[^>]*> ec90 1b02 fldmiad r0, {d1}
|
||||
0+1c0 <[^>]*> ec90 2b02 fldmiad r0, {d2}
|
||||
0+1c4 <[^>]*> ec90 fb02 fldmiad r0, {d15}
|
||||
0+1c8 <[^>]*> ec90 0b04 fldmiad r0, {d0-d1}
|
||||
0+1cc <[^>]*> ec90 0b06 fldmiad r0, {d0-d2}
|
||||
0+1d0 <[^>]*> ec90 0b20 fldmiad r0, {d0-d15}
|
||||
0+1d4 <[^>]*> ec90 1b1e fldmiad r0, {d1-d15}
|
||||
0+1d8 <[^>]*> ec90 2b1c fldmiad r0, {d2-d15}
|
||||
0+1dc <[^>]*> ec90 eb04 fldmiad r0, {d14-d15}
|
||||
0+1e0 <[^>]*> ec91 0b02 fldmiad r1, {d0}
|
||||
0+1e4 <[^>]*> ec9e 0b02 fldmiad lr, {d0}
|
||||
0+148 <[^>]*> ee30 1b10 vmov\.32 r1, d0\[1\]
|
||||
0+14c <[^>]*> ee30 eb10 vmov\.32 lr, d0\[1\]
|
||||
0+150 <[^>]*> ee31 0b10 vmov\.32 r0, d1\[1\]
|
||||
0+154 <[^>]*> ee32 0b10 vmov\.32 r0, d2\[1\]
|
||||
0+158 <[^>]*> ee3f 0b10 vmov\.32 r0, d15\[1\]
|
||||
0+15c <[^>]*> ee10 1b10 vmov\.32 r1, d0\[0\]
|
||||
0+160 <[^>]*> ee10 eb10 vmov\.32 lr, d0\[0\]
|
||||
0+164 <[^>]*> ee11 0b10 vmov\.32 r0, d1\[0\]
|
||||
0+168 <[^>]*> ee12 0b10 vmov\.32 r0, d2\[0\]
|
||||
0+16c <[^>]*> ee1f 0b10 vmov\.32 r0, d15\[0\]
|
||||
0+170 <[^>]*> ee20 1b10 vmov\.32 d0\[1\], r1
|
||||
0+174 <[^>]*> ee20 eb10 vmov\.32 d0\[1\], lr
|
||||
0+178 <[^>]*> ee21 0b10 vmov\.32 d1\[1\], r0
|
||||
0+17c <[^>]*> ee22 0b10 vmov\.32 d2\[1\], r0
|
||||
0+180 <[^>]*> ee2f 0b10 vmov\.32 d15\[1\], r0
|
||||
0+184 <[^>]*> ee00 1b10 vmov\.32 d0\[0\], r1
|
||||
0+188 <[^>]*> ee00 eb10 vmov\.32 d0\[0\], lr
|
||||
0+18c <[^>]*> ee01 0b10 vmov\.32 d1\[0\], r0
|
||||
0+190 <[^>]*> ee02 0b10 vmov\.32 d2\[0\], r0
|
||||
0+194 <[^>]*> ee0f 0b10 vmov\.32 d15\[0\], r0
|
||||
0+198 <[^>]*> ed91 0b00 vldr d0, \[r1\]
|
||||
0+19c <[^>]*> ed9e 0b00 vldr d0, \[lr\]
|
||||
0+1a0 <[^>]*> ed90 0b00 vldr d0, \[r0\]
|
||||
0+1a4 <[^>]*> ed90 0bff vldr d0, \[r0, #1020\]
|
||||
0+1a8 <[^>]*> ed10 0bff vldr d0, \[r0, #-1020\]
|
||||
0+1ac <[^>]*> ed90 1b00 vldr d1, \[r0\]
|
||||
0+1b0 <[^>]*> ed90 2b00 vldr d2, \[r0\]
|
||||
0+1b4 <[^>]*> ed90 fb00 vldr d15, \[r0\]
|
||||
0+1b8 <[^>]*> ed8c cbc9 vstr d12, \[ip, #804\]
|
||||
0+1bc <[^>]*> ec90 1b02 vldmia r0, {d1}
|
||||
0+1c0 <[^>]*> ec90 2b02 vldmia r0, {d2}
|
||||
0+1c4 <[^>]*> ec90 fb02 vldmia r0, {d15}
|
||||
0+1c8 <[^>]*> ec90 0b04 vldmia r0, {d0-d1}
|
||||
0+1cc <[^>]*> ec90 0b06 vldmia r0, {d0-d2}
|
||||
0+1d0 <[^>]*> ec90 0b20 vldmia r0, {d0-d15}
|
||||
0+1d4 <[^>]*> ec90 1b1e vldmia r0, {d1-d15}
|
||||
0+1d8 <[^>]*> ec90 2b1c vldmia r0, {d2-d15}
|
||||
0+1dc <[^>]*> ec90 eb04 vldmia r0, {d14-d15}
|
||||
0+1e0 <[^>]*> ec91 0b02 vldmia r1, {d0}
|
||||
0+1e4 <[^>]*> ec9e 0b02 vldmia lr, {d0}
|
||||
0+1e8 <[^>]*> eeb5 0b40 fcmpzd d0
|
||||
0+1ec <[^>]*> eeb5 1b40 fcmpzd d1
|
||||
0+1f0 <[^>]*> eeb5 2b40 fcmpzd d2
|
||||
|
|
@ -168,23 +168,23 @@ Disassembly of section .text:
|
|||
0+26c <[^>]*> ee24 5b4c fnmuld(eq|) d5, d4, d12
|
||||
0+270 <[^>]*> bf02 ittt eq
|
||||
0+272 <[^>]*> ee3d 3b4e fsubd(eq|) d3, d13, d14
|
||||
0+276 <[^>]*> ed95 2b00 fldd(eq|) d2, \[r5\]
|
||||
0+27a <[^>]*> ed8c 1b00 fstd(eq|) d1, \[ip\]
|
||||
0+276 <[^>]*> ed95 2b00 vldr(eq|) d2, \[r5\]
|
||||
0+27a <[^>]*> ed8c 1b00 vstr(eq|) d1, \[ip\]
|
||||
0+27e <[^>]*> bf01 itttt eq
|
||||
0+280 <[^>]*> ec91 1b02 fldmiad(eq|) r1, {d1}
|
||||
0+284 <[^>]*> ec92 2b02 fldmiad(eq|) r2, {d2}
|
||||
0+288 <[^>]*> ecb3 3b02 fldmiad(eq|) r3!, {d3}
|
||||
0+28c <[^>]*> ecb4 4b02 fldmiad(eq|) r4!, {d4}
|
||||
0+280 <[^>]*> ec91 1b02 vldmia(eq|) r1, {d1}
|
||||
0+284 <[^>]*> ec92 2b02 vldmia(eq|) r2, {d2}
|
||||
0+288 <[^>]*> ecb3 3b02 vldmia(eq|) r3!, {d3}
|
||||
0+28c <[^>]*> ecb4 4b02 vldmia(eq|) r4!, {d4}
|
||||
0+290 <[^>]*> bf01 itttt eq
|
||||
0+292 <[^>]*> ed35 5b02 fldmdbd(eq|) r5!, {d5}
|
||||
0+296 <[^>]*> ed36 6b02 fldmdbd(eq|) r6!, {d6}
|
||||
0+29a <[^>]*> ec87 fb02 fstmiad(eq|) r7, {d15}
|
||||
0+29e <[^>]*> ec88 eb02 fstmiad(eq|) r8, {d14}
|
||||
0+292 <[^>]*> ed35 5b02 vldmdb(eq|) r5!, {d5}
|
||||
0+296 <[^>]*> ed36 6b02 vldmdb(eq|) r6!, {d6}
|
||||
0+29a <[^>]*> ec87 fb02 vstmia(eq|) r7, {d15}
|
||||
0+29e <[^>]*> ec88 eb02 vstmia(eq|) r8, {d14}
|
||||
0+2a2 <[^>]*> bf01 itttt eq
|
||||
0+2a4 <[^>]*> eca9 db02 fstmiad(eq|) r9!, {d13}
|
||||
0+2a8 <[^>]*> ecaa cb02 fstmiad(eq|) sl!, {d12}
|
||||
0+2ac <[^>]*> ed2b bb02 fstmdbd(eq|) fp!, {d11}
|
||||
0+2b0 <[^>]*> ed2c ab02 fstmdbd(eq|) ip!, {d10}
|
||||
0+2a4 <[^>]*> eca9 db02 vstmia(eq|) r9!, {d13}
|
||||
0+2a8 <[^>]*> ecaa cb02 vstmia(eq|) sl!, {d12}
|
||||
0+2ac <[^>]*> ed2b bb02 vstmdb(eq|) fp!, {d11}
|
||||
0+2b0 <[^>]*> ed2c ab02 vstmdb(eq|) ip!, {d10}
|
||||
0+2b4 <[^>]*> bf01 itttt eq
|
||||
0+2b6 <[^>]*> eeb8 fbe0 fsitod(eq|) d15, s1
|
||||
0+2ba <[^>]*> eeb8 1b6f fuitod(eq|) d1, s31
|
||||
|
|
@ -196,10 +196,10 @@ Disassembly of section .text:
|
|||
0+2d0 <[^>]*> eeb7 1ac5 fcvtds(eq|) d1, s10
|
||||
0+2d4 <[^>]*> eef7 5bc1 fcvtsd(eq|) s11, d1
|
||||
0+2d8 <[^>]*> bf01 itttt eq
|
||||
0+2da <[^>]*> ee31 8b10 fmrdh(eq|) r8, d1
|
||||
0+2de <[^>]*> ee1f 7b10 fmrdl(eq|) r7, d15
|
||||
0+2e2 <[^>]*> ee21 fb10 fmdhr(eq|) d1, pc
|
||||
0+2e6 <[^>]*> ee0f 1b10 fmdlr(eq|) d15, r1
|
||||
0+2da <[^>]*> ee31 8b10 vmov(eq|)\.32 r8, d1\[1\]
|
||||
0+2de <[^>]*> ee1f 7b10 vmov(eq|)\.32 r7, d15\[0\]
|
||||
0+2e2 <[^>]*> ee21 fb10 vmov(eq|)\.32 d1\[1\], pc
|
||||
0+2e6 <[^>]*> ee0f 1b10 vmov(eq|)\.32 d15\[0\], r1
|
||||
0+2ea <[^>]*> bf00 nop
|
||||
0+2ec <[^>]*> bf00 nop
|
||||
0+2ee <[^>]*> bf00 nop
|
||||
|
|
|
|||
|
|
@ -33,24 +33,24 @@ Disassembly of section .text:
|
|||
0+05c <[^>]*> ecb00a01 fldmias r0!, {s0}
|
||||
0+060 <[^>]*> ed300a01 fldmdbs r0!, {s0}
|
||||
0+064 <[^>]*> ed300a01 fldmdbs r0!, {s0}
|
||||
0+068 <[^>]*> ec900b03 fldmiax r0, {d0}
|
||||
0+06c <[^>]*> ec900b03 fldmiax r0, {d0}
|
||||
0+070 <[^>]*> ecb00b03 fldmiax r0!, {d0}
|
||||
0+074 <[^>]*> ecb00b03 fldmiax r0!, {d0}
|
||||
0+078 <[^>]*> ed300b03 fldmdbx r0!, {d0}
|
||||
0+07c <[^>]*> ed300b03 fldmdbx r0!, {d0}
|
||||
0+068 <[^>]*> ec900b03 vldmia r0, {d0}
|
||||
0+06c <[^>]*> ec900b03 vldmia r0, {d0}
|
||||
0+070 <[^>]*> ecb00b03 vldmia r0!, {d0}
|
||||
0+074 <[^>]*> ecb00b03 vldmia r0!, {d0}
|
||||
0+078 <[^>]*> ed300b03 vldmdb r0!, {d0}
|
||||
0+07c <[^>]*> ed300b03 vldmdb r0!, {d0}
|
||||
0+080 <[^>]*> ec800a01 fstmias r0, {s0}
|
||||
0+084 <[^>]*> ec800a01 fstmias r0, {s0}
|
||||
0+088 <[^>]*> eca00a01 fstmias r0!, {s0}
|
||||
0+08c <[^>]*> eca00a01 fstmias r0!, {s0}
|
||||
0+090 <[^>]*> ed200a01 fstmdbs r0!, {s0}
|
||||
0+094 <[^>]*> ed200a01 fstmdbs r0!, {s0}
|
||||
0+098 <[^>]*> ec800b03 fstmiax r0, {d0}
|
||||
0+09c <[^>]*> ec800b03 fstmiax r0, {d0}
|
||||
0+0a0 <[^>]*> eca00b03 fstmiax r0!, {d0}
|
||||
0+0a4 <[^>]*> eca00b03 fstmiax r0!, {d0}
|
||||
0+0a8 <[^>]*> ed200b03 fstmdbx r0!, {d0}
|
||||
0+0ac <[^>]*> ed200b03 fstmdbx r0!, {d0}
|
||||
0+098 <[^>]*> ec800b03 vstmia r0, {d0}
|
||||
0+09c <[^>]*> ec800b03 vstmia r0, {d0}
|
||||
0+0a0 <[^>]*> eca00b03 vstmia r0!, {d0}
|
||||
0+0a4 <[^>]*> eca00b03 vstmia r0!, {d0}
|
||||
0+0a8 <[^>]*> ed200b03 vstmdb r0!, {d0}
|
||||
0+0ac <[^>]*> ed200b03 vstmdb r0!, {d0}
|
||||
0+0b0 <[^>]*> eeb80ac0 fsitos s0, s0
|
||||
0+0b4 <[^>]*> eeb80a40 fuitos s0, s0
|
||||
0+0b8 <[^>]*> eebd0a40 ftosis s0, s0
|
||||
|
|
@ -142,17 +142,17 @@ Disassembly of section .text:
|
|||
0+210 <[^>]*> ec90fa02 fldmias r0, {s30-s31}
|
||||
0+214 <[^>]*> ec910a01 fldmias r1, {s0}
|
||||
0+218 <[^>]*> ec9e0a01 fldmias lr, {s0}
|
||||
0+21c <[^>]*> ec801b03 fstmiax r0, {d1}
|
||||
0+220 <[^>]*> ec802b03 fstmiax r0, {d2}
|
||||
0+224 <[^>]*> ec80fb03 fstmiax r0, {d15}
|
||||
0+228 <[^>]*> ec800b05 fstmiax r0, {d0-d1}
|
||||
0+22c <[^>]*> ec800b07 fstmiax r0, {d0-d2}
|
||||
0+230 <[^>]*> ec800b21 fstmiax r0, {d0-d15}
|
||||
0+234 <[^>]*> ec801b1f fstmiax r0, {d1-d15}
|
||||
0+238 <[^>]*> ec802b1d fstmiax r0, {d2-d15}
|
||||
0+23c <[^>]*> ec80eb05 fstmiax r0, {d14-d15}
|
||||
0+240 <[^>]*> ec810b03 fstmiax r1, {d0}
|
||||
0+244 <[^>]*> ec8e0b03 fstmiax lr, {d0}
|
||||
0+21c <[^>]*> ec801b03 vstmia r0, {d1}
|
||||
0+220 <[^>]*> ec802b03 vstmia r0, {d2}
|
||||
0+224 <[^>]*> ec80fb03 vstmia r0, {d15}
|
||||
0+228 <[^>]*> ec800b05 vstmia r0, {d0-d1}
|
||||
0+22c <[^>]*> ec800b07 vstmia r0, {d0-d2}
|
||||
0+230 <[^>]*> ec800b21 vstmia r0, {d0-d15}
|
||||
0+234 <[^>]*> ec801b1f vstmia r0, {d1-d15}
|
||||
0+238 <[^>]*> ec802b1d vstmia r0, {d2-d15}
|
||||
0+23c <[^>]*> ec80eb05 vstmia r0, {d14-d15}
|
||||
0+240 <[^>]*> ec810b03 vstmia r1, {d0}
|
||||
0+244 <[^>]*> ec8e0b03 vstmia lr, {d0}
|
||||
0+248 <[^>]*> eeb50a40 fcmpzs s0
|
||||
0+24c <[^>]*> eef50a40 fcmpzs s1
|
||||
0+250 <[^>]*> eeb51a40 fcmpzs s2
|
||||
|
|
@ -211,24 +211,24 @@ Disassembly of section .text:
|
|||
0+324 <[^>]*> 0cf42a01 fldmiaseq r4!, {s5}
|
||||
0+328 <[^>]*> 0d352a01 fldmdbseq r5!, {s4}
|
||||
0+32c <[^>]*> 0d761a01 fldmdbseq r6!, {s3}
|
||||
0+330 <[^>]*> 0c971b03 fldmiaxeq r7, {d1}
|
||||
0+334 <[^>]*> 0c982b03 fldmiaxeq r8, {d2}
|
||||
0+338 <[^>]*> 0cb93b03 fldmiaxeq r9!, {d3}
|
||||
0+33c <[^>]*> 0cba4b03 fldmiaxeq sl!, {d4}
|
||||
0+340 <[^>]*> 0d3b5b03 fldmdbxeq fp!, {d5}
|
||||
0+344 <[^>]*> 0d3c6b03 fldmdbxeq ip!, {d6}
|
||||
0+330 <[^>]*> 0c971b03 vldmiaeq r7, {d1}
|
||||
0+334 <[^>]*> 0c982b03 vldmiaeq r8, {d2}
|
||||
0+338 <[^>]*> 0cb93b03 vldmiaeq r9!, {d3}
|
||||
0+33c <[^>]*> 0cba4b03 vldmiaeq sl!, {d4}
|
||||
0+340 <[^>]*> 0d3b5b03 vldmdbeq fp!, {d5}
|
||||
0+344 <[^>]*> 0d3c6b03 vldmdbeq ip!, {d6}
|
||||
0+348 <[^>]*> 0c8d1a01 fstmiaseq sp, {s2}
|
||||
0+34c <[^>]*> 0cce0a01 fstmiaseq lr, {s1}
|
||||
0+350 <[^>]*> 0ce1fa01 fstmiaseq r1!, {s31}
|
||||
0+354 <[^>]*> 0ca2fa01 fstmiaseq r2!, {s30}
|
||||
0+358 <[^>]*> 0d63ea01 fstmdbseq r3!, {s29}
|
||||
0+35c <[^>]*> 0d24ea01 fstmdbseq r4!, {s28}
|
||||
0+360 <[^>]*> 0c857b03 fstmiaxeq r5, {d7}
|
||||
0+364 <[^>]*> 0c868b03 fstmiaxeq r6, {d8}
|
||||
0+368 <[^>]*> 0ca79b03 fstmiaxeq r7!, {d9}
|
||||
0+36c <[^>]*> 0ca8ab03 fstmiaxeq r8!, {d10}
|
||||
0+370 <[^>]*> 0d29bb03 fstmdbxeq r9!, {d11}
|
||||
0+374 <[^>]*> 0d2acb03 fstmdbxeq sl!, {d12}
|
||||
0+360 <[^>]*> 0c857b03 vstmiaeq r5, {d7}
|
||||
0+364 <[^>]*> 0c868b03 vstmiaeq r6, {d8}
|
||||
0+368 <[^>]*> 0ca79b03 vstmiaeq r7!, {d9}
|
||||
0+36c <[^>]*> 0ca8ab03 vstmiaeq r8!, {d10}
|
||||
0+370 <[^>]*> 0d29bb03 vstmdbeq r9!, {d11}
|
||||
0+374 <[^>]*> 0d2acb03 vstmdbeq sl!, {d12}
|
||||
0+378 <[^>]*> 0ef8dac3 fsitoseq s27, s6
|
||||
0+37c <[^>]*> 0efdca62 ftosiseq s25, s5
|
||||
0+380 <[^>]*> 0efdbac2 ftosizseq s23, s4
|
||||
|
|
|
|||
|
|
@ -33,24 +33,24 @@ Disassembly of section .text:
|
|||
0+05c <[^>]*> ecb0 0a01 fldmias r0!, {s0}
|
||||
0+060 <[^>]*> ed30 0a01 fldmdbs r0!, {s0}
|
||||
0+064 <[^>]*> ed30 0a01 fldmdbs r0!, {s0}
|
||||
0+068 <[^>]*> ec90 0b03 fldmiax r0, {d0}
|
||||
0+06c <[^>]*> ec90 0b03 fldmiax r0, {d0}
|
||||
0+070 <[^>]*> ecb0 0b03 fldmiax r0!, {d0}
|
||||
0+074 <[^>]*> ecb0 0b03 fldmiax r0!, {d0}
|
||||
0+078 <[^>]*> ed30 0b03 fldmdbx r0!, {d0}
|
||||
0+07c <[^>]*> ed30 0b03 fldmdbx r0!, {d0}
|
||||
0+068 <[^>]*> ec90 0b03 vldmia r0, {d0}
|
||||
0+06c <[^>]*> ec90 0b03 vldmia r0, {d0}
|
||||
0+070 <[^>]*> ecb0 0b03 vldmia r0!, {d0}
|
||||
0+074 <[^>]*> ecb0 0b03 vldmia r0!, {d0}
|
||||
0+078 <[^>]*> ed30 0b03 vldmdb r0!, {d0}
|
||||
0+07c <[^>]*> ed30 0b03 vldmdb r0!, {d0}
|
||||
0+080 <[^>]*> ec80 0a01 fstmias r0, {s0}
|
||||
0+084 <[^>]*> ec80 0a01 fstmias r0, {s0}
|
||||
0+088 <[^>]*> eca0 0a01 fstmias r0!, {s0}
|
||||
0+08c <[^>]*> eca0 0a01 fstmias r0!, {s0}
|
||||
0+090 <[^>]*> ed20 0a01 fstmdbs r0!, {s0}
|
||||
0+094 <[^>]*> ed20 0a01 fstmdbs r0!, {s0}
|
||||
0+098 <[^>]*> ec80 0b03 fstmiax r0, {d0}
|
||||
0+09c <[^>]*> ec80 0b03 fstmiax r0, {d0}
|
||||
0+0a0 <[^>]*> eca0 0b03 fstmiax r0!, {d0}
|
||||
0+0a4 <[^>]*> eca0 0b03 fstmiax r0!, {d0}
|
||||
0+0a8 <[^>]*> ed20 0b03 fstmdbx r0!, {d0}
|
||||
0+0ac <[^>]*> ed20 0b03 fstmdbx r0!, {d0}
|
||||
0+098 <[^>]*> ec80 0b03 vstmia r0, {d0}
|
||||
0+09c <[^>]*> ec80 0b03 vstmia r0, {d0}
|
||||
0+0a0 <[^>]*> eca0 0b03 vstmia r0!, {d0}
|
||||
0+0a4 <[^>]*> eca0 0b03 vstmia r0!, {d0}
|
||||
0+0a8 <[^>]*> ed20 0b03 vstmdb r0!, {d0}
|
||||
0+0ac <[^>]*> ed20 0b03 vstmdb r0!, {d0}
|
||||
0+0b0 <[^>]*> eeb8 0ac0 fsitos s0, s0
|
||||
0+0b4 <[^>]*> eeb8 0a40 fuitos s0, s0
|
||||
0+0b8 <[^>]*> eebd 0a40 ftosis s0, s0
|
||||
|
|
@ -142,17 +142,17 @@ Disassembly of section .text:
|
|||
0+210 <[^>]*> ec90 fa02 fldmias r0, {s30-s31}
|
||||
0+214 <[^>]*> ec91 0a01 fldmias r1, {s0}
|
||||
0+218 <[^>]*> ec9e 0a01 fldmias lr, {s0}
|
||||
0+21c <[^>]*> ec80 1b03 fstmiax r0, {d1}
|
||||
0+220 <[^>]*> ec80 2b03 fstmiax r0, {d2}
|
||||
0+224 <[^>]*> ec80 fb03 fstmiax r0, {d15}
|
||||
0+228 <[^>]*> ec80 0b05 fstmiax r0, {d0-d1}
|
||||
0+22c <[^>]*> ec80 0b07 fstmiax r0, {d0-d2}
|
||||
0+230 <[^>]*> ec80 0b21 fstmiax r0, {d0-d15}
|
||||
0+234 <[^>]*> ec80 1b1f fstmiax r0, {d1-d15}
|
||||
0+238 <[^>]*> ec80 2b1d fstmiax r0, {d2-d15}
|
||||
0+23c <[^>]*> ec80 eb05 fstmiax r0, {d14-d15}
|
||||
0+240 <[^>]*> ec81 0b03 fstmiax r1, {d0}
|
||||
0+244 <[^>]*> ec8e 0b03 fstmiax lr, {d0}
|
||||
0+21c <[^>]*> ec80 1b03 vstmia r0, {d1}
|
||||
0+220 <[^>]*> ec80 2b03 vstmia r0, {d2}
|
||||
0+224 <[^>]*> ec80 fb03 vstmia r0, {d15}
|
||||
0+228 <[^>]*> ec80 0b05 vstmia r0, {d0-d1}
|
||||
0+22c <[^>]*> ec80 0b07 vstmia r0, {d0-d2}
|
||||
0+230 <[^>]*> ec80 0b21 vstmia r0, {d0-d15}
|
||||
0+234 <[^>]*> ec80 1b1f vstmia r0, {d1-d15}
|
||||
0+238 <[^>]*> ec80 2b1d vstmia r0, {d2-d15}
|
||||
0+23c <[^>]*> ec80 eb05 vstmia r0, {d14-d15}
|
||||
0+240 <[^>]*> ec81 0b03 vstmia r1, {d0}
|
||||
0+244 <[^>]*> ec8e 0b03 vstmia lr, {d0}
|
||||
0+248 <[^>]*> eeb5 0a40 fcmpzs s0
|
||||
0+24c <[^>]*> eef5 0a40 fcmpzs s1
|
||||
0+250 <[^>]*> eeb5 1a40 fcmpzs s2
|
||||
|
|
@ -219,13 +219,13 @@ Disassembly of section .text:
|
|||
0+334 <[^>]*> bf01 itttt eq
|
||||
0+336 <[^>]*> ed35 2a01 fldmdbs(eq|) r5!, {s4}
|
||||
0+33a <[^>]*> ed76 1a01 fldmdbs(eq|) r6!, {s3}
|
||||
0+33e <[^>]*> ec97 1b03 fldmiax(eq|) r7, {d1}
|
||||
0+342 <[^>]*> ec98 2b03 fldmiax(eq|) r8, {d2}
|
||||
0+33e <[^>]*> ec97 1b03 vldmia(eq|) r7, {d1}
|
||||
0+342 <[^>]*> ec98 2b03 vldmia(eq|) r8, {d2}
|
||||
0+346 <[^>]*> bf01 itttt eq
|
||||
0+348 <[^>]*> ecb9 3b03 fldmiax(eq|) r9!, {d3}
|
||||
0+34c <[^>]*> ecba 4b03 fldmiax(eq|) sl!, {d4}
|
||||
0+350 <[^>]*> ed3b 5b03 fldmdbx(eq|) fp!, {d5}
|
||||
0+354 <[^>]*> ed3c 6b03 fldmdbx(eq|) ip!, {d6}
|
||||
0+348 <[^>]*> ecb9 3b03 vldmia(eq|) r9!, {d3}
|
||||
0+34c <[^>]*> ecba 4b03 vldmia(eq|) sl!, {d4}
|
||||
0+350 <[^>]*> ed3b 5b03 vldmdb(eq|) fp!, {d5}
|
||||
0+354 <[^>]*> ed3c 6b03 vldmdb(eq|) ip!, {d6}
|
||||
0+358 <[^>]*> bf01 itttt eq
|
||||
0+35a <[^>]*> ec8d 1a01 fstmias(eq|) sp, {s2}
|
||||
0+35e <[^>]*> ecce 0a01 fstmias(eq|) lr, {s1}
|
||||
|
|
@ -234,13 +234,13 @@ Disassembly of section .text:
|
|||
0+36a <[^>]*> bf01 itttt eq
|
||||
0+36c <[^>]*> ed63 ea01 fstmdbs(eq|) r3!, {s29}
|
||||
0+370 <[^>]*> ed24 ea01 fstmdbs(eq|) r4!, {s28}
|
||||
0+374 <[^>]*> ec85 7b03 fstmiax(eq|) r5, {d7}
|
||||
0+378 <[^>]*> ec86 8b03 fstmiax(eq|) r6, {d8}
|
||||
0+374 <[^>]*> ec85 7b03 vstmia(eq|) r5, {d7}
|
||||
0+378 <[^>]*> ec86 8b03 vstmia(eq|) r6, {d8}
|
||||
0+37c <[^>]*> bf01 itttt eq
|
||||
0+37e <[^>]*> eca7 9b03 fstmiax(eq|) r7!, {d9}
|
||||
0+382 <[^>]*> eca8 ab03 fstmiax(eq|) r8!, {d10}
|
||||
0+386 <[^>]*> ed29 bb03 fstmdbx(eq|) r9!, {d11}
|
||||
0+38a <[^>]*> ed2a cb03 fstmdbx(eq|) sl!, {d12}
|
||||
0+37e <[^>]*> eca7 9b03 vstmia(eq|) r7!, {d9}
|
||||
0+382 <[^>]*> eca8 ab03 vstmia(eq|) r8!, {d10}
|
||||
0+386 <[^>]*> ed29 bb03 vstmdb(eq|) r9!, {d11}
|
||||
0+38a <[^>]*> ed2a cb03 vstmdb(eq|) sl!, {d12}
|
||||
0+38e <[^>]*> bf01 itttt eq
|
||||
0+390 <[^>]*> eef8 dac3 fsitos(eq|) s27, s6
|
||||
0+394 <[^>]*> eefd ca62 ftosis(eq|) s25, s5
|
||||
|
|
|
|||
|
|
@ -7,11 +7,11 @@
|
|||
.*: +file format .*arm.*
|
||||
|
||||
Disassembly of section .text:
|
||||
0+000 <[^>]*> ec4a5b10 fmdrr d0, r5, sl
|
||||
0+004 <[^>]*> ec5a5b10 fmrrd r5, sl, d0
|
||||
0+000 <[^>]*> ec4a5b10 vmov d0, r5, sl
|
||||
0+004 <[^>]*> ec5a5b10 vmov r5, sl, d0
|
||||
0+008 <[^>]*> ec4a5a37 fmsrr r5, sl, {s15, s16}
|
||||
0+00c <[^>]*> ec5a5a37 fmrrs r5, sl, {s15, s16}
|
||||
0+010 <[^>]*> ec45ab1f fmdrr d15, sl, r5
|
||||
0+014 <[^>]*> ec55ab1f fmrrd sl, r5, d15
|
||||
0+010 <[^>]*> ec45ab1f vmov d15, sl, r5
|
||||
0+014 <[^>]*> ec55ab1f vmov sl, r5, d15
|
||||
0+018 <[^>]*> ec45aa38 fmsrr sl, r5, {s17, s18}
|
||||
0+01c <[^>]*> ec55aa38 fmrrs sl, r5, {s17, s18}
|
||||
|
|
|
|||
|
|
@ -7,11 +7,11 @@
|
|||
.*: +file format .*arm.*
|
||||
|
||||
Disassembly of section .text:
|
||||
0+000 <[^>]*> ec4a 5b10 fmdrr d0, r5, sl
|
||||
0+004 <[^>]*> ec5a 5b10 fmrrd r5, sl, d0
|
||||
0+000 <[^>]*> ec4a 5b10 vmov d0, r5, sl
|
||||
0+004 <[^>]*> ec5a 5b10 vmov r5, sl, d0
|
||||
0+008 <[^>]*> ec4a 5a37 fmsrr r5, sl, {s15, s16}
|
||||
0+00c <[^>]*> ec5a 5a37 fmrrs r5, sl, {s15, s16}
|
||||
0+010 <[^>]*> ec45 ab1f fmdrr d15, sl, r5
|
||||
0+014 <[^>]*> ec55 ab1f fmrrd sl, r5, d15
|
||||
0+010 <[^>]*> ec45 ab1f vmov d15, sl, r5
|
||||
0+014 <[^>]*> ec55 ab1f vmov sl, r5, d15
|
||||
0+018 <[^>]*> ec45 aa38 fmsrr sl, r5, {s17, s18}
|
||||
0+01c <[^>]*> ec55 aa38 fmrrs sl, r5, {s17, s18}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,73 @@
|
|||
# name: VFPv3 extra D registers
|
||||
# as: -mfpu=vfp3
|
||||
# objdump: -dr --prefix-addresses --show-raw-insn
|
||||
|
||||
.*: +file format .*arm.*
|
||||
|
||||
Disassembly of section \.text:
|
||||
0[0-9a-f]+ <[^>]+> eeb03b66 fcpyd d3, d22
|
||||
0[0-9a-f]+ <[^>]+> eef06b43 fcpyd d22, d3
|
||||
0[0-9a-f]+ <[^>]+> eef76acb fcvtds d22, s22
|
||||
0[0-9a-f]+ <[^>]+> eeb7bbe6 fcvtsd s22, d22
|
||||
0[0-9a-f]+ <[^>]+> ee254b90 vmov\.32 d21\[1\], r4
|
||||
0[0-9a-f]+ <[^>]+> ee0b5b90 vmov\.32 d27\[0\], r5
|
||||
0[0-9a-f]+ <[^>]+> ee376b90 vmov\.32 r6, d23\[1\]
|
||||
0[0-9a-f]+ <[^>]+> ee197b90 vmov\.32 r7, d25\[0\]
|
||||
0[0-9a-f]+ <[^>]+> eef86bcb fsitod d22, s22
|
||||
0[0-9a-f]+ <[^>]+> eef85b6a fuitod d21, s21
|
||||
0[0-9a-f]+ <[^>]+> eebdab64 ftosid s20, d20
|
||||
0[0-9a-f]+ <[^>]+> eebdabe4 ftosizd s20, d20
|
||||
0[0-9a-f]+ <[^>]+> eefc9b63 ftouid s19, d19
|
||||
0[0-9a-f]+ <[^>]+> eefc9be3 ftouizd s19, d19
|
||||
0[0-9a-f]+ <[^>]+> edda3b01 vldr d19, \[sl, #4\]
|
||||
0[0-9a-f]+ <[^>]+> edca5b01 vstr d21, \[sl, #4\]
|
||||
0[0-9a-f]+ <[^>]+> ecba5b04 vldmia sl!, {d5-d6}
|
||||
0[0-9a-f]+ <[^>]+> ecfa2b06 vldmia sl!, {d18-d20}
|
||||
0[0-9a-f]+ <[^>]+> ecba5b05 vldmia sl!, {d5-d6}
|
||||
0[0-9a-f]+ <[^>]+> ecfa2b07 vldmia sl!, {d18-d20}
|
||||
0[0-9a-f]+ <[^>]+> ed7a2b05 vldmdb sl!, {d18-d19}
|
||||
0[0-9a-f]+ <[^>]+> ecc94b0a vstmia r9, {d20-d24}
|
||||
0[0-9a-f]+ <[^>]+> eeb03bc5 fabsd d3, d5
|
||||
0[0-9a-f]+ <[^>]+> eeb0cbe2 fabsd d12, d18
|
||||
0[0-9a-f]+ <[^>]+> eef02be3 fabsd d18, d19
|
||||
0[0-9a-f]+ <[^>]+> eeb13b45 fnegd d3, d5
|
||||
0[0-9a-f]+ <[^>]+> eeb1cb62 fnegd d12, d18
|
||||
0[0-9a-f]+ <[^>]+> eef12b63 fnegd d18, d19
|
||||
0[0-9a-f]+ <[^>]+> eeb13bc5 fsqrtd d3, d5
|
||||
0[0-9a-f]+ <[^>]+> eeb1cbe2 fsqrtd d12, d18
|
||||
0[0-9a-f]+ <[^>]+> eef12be3 fsqrtd d18, d19
|
||||
0[0-9a-f]+ <[^>]+> ee353b06 faddd d3, d5, d6
|
||||
0[0-9a-f]+ <[^>]+> ee32cb84 faddd d12, d18, d4
|
||||
0[0-9a-f]+ <[^>]+> ee732ba4 faddd d18, d19, d20
|
||||
0[0-9a-f]+ <[^>]+> ee353b46 fsubd d3, d5, d6
|
||||
0[0-9a-f]+ <[^>]+> ee32cbc4 fsubd d12, d18, d4
|
||||
0[0-9a-f]+ <[^>]+> ee732be4 fsubd d18, d19, d20
|
||||
0[0-9a-f]+ <[^>]+> ee253b06 fmuld d3, d5, d6
|
||||
0[0-9a-f]+ <[^>]+> ee22cb84 fmuld d12, d18, d4
|
||||
0[0-9a-f]+ <[^>]+> ee632ba4 fmuld d18, d19, d20
|
||||
0[0-9a-f]+ <[^>]+> ee853b06 fdivd d3, d5, d6
|
||||
0[0-9a-f]+ <[^>]+> ee82cb84 fdivd d12, d18, d4
|
||||
0[0-9a-f]+ <[^>]+> eec32ba4 fdivd d18, d19, d20
|
||||
0[0-9a-f]+ <[^>]+> ee053b06 fmacd d3, d5, d6
|
||||
0[0-9a-f]+ <[^>]+> ee02cb84 fmacd d12, d18, d4
|
||||
0[0-9a-f]+ <[^>]+> ee432ba4 fmacd d18, d19, d20
|
||||
0[0-9a-f]+ <[^>]+> ee153b06 fmscd d3, d5, d6
|
||||
0[0-9a-f]+ <[^>]+> ee12cb84 fmscd d12, d18, d4
|
||||
0[0-9a-f]+ <[^>]+> ee532ba4 fmscd d18, d19, d20
|
||||
0[0-9a-f]+ <[^>]+> ee253b46 fnmuld d3, d5, d6
|
||||
0[0-9a-f]+ <[^>]+> ee22cbc4 fnmuld d12, d18, d4
|
||||
0[0-9a-f]+ <[^>]+> ee632be4 fnmuld d18, d19, d20
|
||||
0[0-9a-f]+ <[^>]+> ee053b46 fnmacd d3, d5, d6
|
||||
0[0-9a-f]+ <[^>]+> ee02cbc4 fnmacd d12, d18, d4
|
||||
0[0-9a-f]+ <[^>]+> ee432be4 fnmacd d18, d19, d20
|
||||
0[0-9a-f]+ <[^>]+> ee153b46 fnmscd d3, d5, d6
|
||||
0[0-9a-f]+ <[^>]+> ee12cbc4 fnmscd d12, d18, d4
|
||||
0[0-9a-f]+ <[^>]+> ee532be4 fnmscd d18, d19, d20
|
||||
0[0-9a-f]+ <[^>]+> eeb43b62 fcmpd d3, d18
|
||||
0[0-9a-f]+ <[^>]+> eef42b43 fcmpd d18, d3
|
||||
0[0-9a-f]+ <[^>]+> eef53b40 fcmpzd d19
|
||||
0[0-9a-f]+ <[^>]+> eeb43be2 fcmped d3, d18
|
||||
0[0-9a-f]+ <[^>]+> eef42bc3 fcmped d18, d3
|
||||
0[0-9a-f]+ <[^>]+> eef53bc0 fcmpezd d19
|
||||
0[0-9a-f]+ <[^>]+> ec443b3f vmov d31, r3, r4
|
||||
0[0-9a-f]+ <[^>]+> ec565b3e vmov r5, r6, d30
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
.arm
|
||||
.syntax unified
|
||||
fcpyd d3,d22
|
||||
fcpyd d22,d3
|
||||
fcvtds d22,s22
|
||||
fcvtsd s22,d22
|
||||
fmdhr d21,r4
|
||||
fmdlr d27,r5
|
||||
fmrdh r6,d23
|
||||
fmrdl r7,d25
|
||||
fsitod d22,s22
|
||||
fuitod d21,s21
|
||||
ftosid s20,d20
|
||||
ftosizd s20,d20
|
||||
ftouid s19,d19
|
||||
ftouizd s19,d19
|
||||
fldd d19,[r10,#4]
|
||||
fstd d21,[r10,#4]
|
||||
fldmiad r10!,{d5,d6}
|
||||
fldmiad r10!,{d18,d19,d20}
|
||||
fldmiax r10!,{d5,d6}
|
||||
fldmiax r10!,{d18,d19,d20}
|
||||
fldmdbx r10!,{d18,d19}
|
||||
fstmiad r9,{d20,d21,d22,d23,d24}
|
||||
fabsd d3,d5
|
||||
fabsd d12,d18
|
||||
fabsd d18,d19
|
||||
fnegd d3,d5
|
||||
fnegd d12,d18
|
||||
fnegd d18,d19
|
||||
fsqrtd d3,d5
|
||||
fsqrtd d12,d18
|
||||
fsqrtd d18,d19
|
||||
faddd d3,d5,d6
|
||||
faddd d12,d18,d4
|
||||
faddd d18,d19,d20
|
||||
fsubd d3,d5,d6
|
||||
fsubd d12,d18,d4
|
||||
fsubd d18,d19,d20
|
||||
fmuld d3,d5,d6
|
||||
fmuld d12,d18,d4
|
||||
fmuld d18,d19,d20
|
||||
fdivd d3,d5,d6
|
||||
fdivd d12,d18,d4
|
||||
fdivd d18,d19,d20
|
||||
fmacd d3,d5,d6
|
||||
fmacd d12,d18,d4
|
||||
fmacd d18,d19,d20
|
||||
fmscd d3,d5,d6
|
||||
fmscd d12,d18,d4
|
||||
fmscd d18,d19,d20
|
||||
fnmuld d3,d5,d6
|
||||
fnmuld d12,d18,d4
|
||||
fnmuld d18,d19,d20
|
||||
fnmacd d3,d5,d6
|
||||
fnmacd d12,d18,d4
|
||||
fnmacd d18,d19,d20
|
||||
fnmscd d3,d5,d6
|
||||
fnmscd d12,d18,d4
|
||||
fnmscd d18,d19,d20
|
||||
fcmpd d3,d18
|
||||
fcmpd d18,d3
|
||||
fcmpzd d19
|
||||
fcmped d3,d18
|
||||
fcmped d18,d3
|
||||
fcmpezd d19
|
||||
fmdrr d31,r3,r4
|
||||
fmrrd r5,r6,d30
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
# name: VFPv3 additional constant and conversion ops
|
||||
# as: -mfpu=vfp3
|
||||
# objdump: -dr --prefix-addresses --show-raw-insn
|
||||
|
||||
.*: +file format .*arm.*
|
||||
|
||||
Disassembly of section \.text:
|
||||
0[0-9a-f]+ <[^>]+> eef48a00 fconsts s17, #4
|
||||
0[0-9a-f]+ <[^>]+> eeb59a00 fconsts s18, #5
|
||||
0[0-9a-f]+ <[^>]+> eef69a00 fconsts s19, #6
|
||||
0[0-9a-f]+ <[^>]+> eef41b00 fconstd d17, #4
|
||||
0[0-9a-f]+ <[^>]+> eef52b00 fconstd d18, #5
|
||||
0[0-9a-f]+ <[^>]+> eef63b00 fconstd d19, #6
|
||||
0[0-9a-f]+ <[^>]+> eefa8a63 fshtos s17, #9
|
||||
0[0-9a-f]+ <[^>]+> eefa1b63 fshtod d17, #9
|
||||
0[0-9a-f]+ <[^>]+> eefa8aeb fsltos s17, #9
|
||||
0[0-9a-f]+ <[^>]+> eefa1beb fsltod d17, #9
|
||||
0[0-9a-f]+ <[^>]+> eefb8a63 fuhtos s17, #9
|
||||
0[0-9a-f]+ <[^>]+> eefb1b63 fuhtod d17, #9
|
||||
0[0-9a-f]+ <[^>]+> eefb8aeb fultos s17, #9
|
||||
0[0-9a-f]+ <[^>]+> eefb1beb fultod d17, #9
|
||||
0[0-9a-f]+ <[^>]+> eefe9a64 ftoshs s19, #7
|
||||
0[0-9a-f]+ <[^>]+> eefe3b64 ftoshd d19, #7
|
||||
0[0-9a-f]+ <[^>]+> eefe9aec ftosls s19, #7
|
||||
0[0-9a-f]+ <[^>]+> eefe3bec ftosld d19, #7
|
||||
0[0-9a-f]+ <[^>]+> eeff9a64 ftouhs s19, #7
|
||||
0[0-9a-f]+ <[^>]+> eeff3b64 ftouhd d19, #7
|
||||
0[0-9a-f]+ <[^>]+> eeff9aec ftouls s19, #7
|
||||
0[0-9a-f]+ <[^>]+> eeff3bec ftould d19, #7
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
.arm
|
||||
.syntax unified
|
||||
fconsts s17, #4
|
||||
fconsts s18, #5
|
||||
fconsts s19, #6
|
||||
fconstd d17, #4
|
||||
fconstd d18, #5
|
||||
fconstd d19, #6
|
||||
fshtos s17, 9
|
||||
fshtod d17, 9
|
||||
fsltos s17, 9
|
||||
fsltod d17, 9
|
||||
fuhtos s17, 9
|
||||
fuhtod d17, 9
|
||||
fultos s17, 9
|
||||
fultod d17, 9
|
||||
|
||||
ftoshs s19, 7
|
||||
ftoshd d19, 7
|
||||
ftosls s19, 7
|
||||
ftosld d19, 7
|
||||
ftouhs s19, 7
|
||||
ftouhd d19, 7
|
||||
ftouls s19, 7
|
||||
ftould d19, 7
|
||||
Loading…
Reference in New Issue