Add Score test files
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#as:
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#objdump: -d
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#source: addi.s
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.*: +file format .*
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Disassembly of section \.text:
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00000000 <.text>:
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0: 84008003 addi.c r0, 1
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4: 84008003 addi.c r0, 1
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8: 85e08021 addi.c r15, 16
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c: 85e08021 addi.c r15, 16
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10: 85e18001 addi.c r15, 16384
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14: 85e18001 addi.c r15, 16384
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18: 6818 addei! r8, 3
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1a: 6818 addei! r8, 3
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1c: 6f78 addei! r15, 15
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1e: 0000 nop!
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20: 85e1ffff addi.c r15, 32767
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...
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30: 8403ffff addi.c r0, -1
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34: 8403ffff addi.c r0, -1
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38: 85e3ffe1 addi.c r15, -16
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3c: 85e3ffe1 addi.c r15, -16
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40: 85e38001 addi.c r15, -16384
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44: 85e38001 addi.c r15, -16384
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48: 6898 subei! r8, 3
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4a: 6898 subei! r8, 3
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4c: 6ff8 subei! r15, 15
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4e: 0000 nop!
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50: 85e1ffff addi.c r15, 32767
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#pass
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/*
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* test relax
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* addi <-> addei! : for addei : register number must be in 0-15, offset : 4b, only 16b -> 32b
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* (1)addi rD, simm16 : rD = rD + simm16, -32768 <= simm16 <= 32767
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* (2)addei! rD, imm4 : rD = rD + 2**imm4
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* addi <-> subei! : for addei : register number must be in 0-15, offset : 4b, only 16b -> 32b
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* (1)addi rD, simm16 : rD = rD + simm16, -32768 <= simm16 <= 32767
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* (2)subei! rD, imm4 : rD = rD + 2**imm4
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* Author: ligang
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*/
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/* This macro transform 16b instruction to 32b. */
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.macro tran1632 insn32, insn16, sign
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.align 4
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\insn16 r0, 0 #16b -> 32b
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\insn32 r0, \sign * 1
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\insn16 r15, 4 #16b -> 32b
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\insn32 r15, \sign * 16
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\insn16 r15, 14 #16b -> 32b
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\insn32 r15, \sign * 1024 * 16
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\insn16 r8, 3 #No transform
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\insn16 r8, 3 #No transform
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\insn16 r15, 15 #No transform. Because 2**15 = 32768, extend range of addi
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\insn32 r15, 0x7FFF
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.endm
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.text
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tran1632 "addi.c", "addei!", 1
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tran1632 "addi.c", "subei!", -1
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#as:
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#objdump: -d
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#source: b.s
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.*: +file format .*
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Disassembly of section \.text:
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00000000 <L1>:
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0: 4f00 b! 0x0 <L1>
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2: 4fff b! 0x0 <L1>
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4: 4ffe b! 0x0 <L1>
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6: 4ffd b! 0x0 <L1>
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8: 4ffc b! 0x0 <L1>
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a: 4ffb b! 0x0 <L1>
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c: 93ffbff4 b 0x0 <L1>
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10: 8254e010 add r18, r20, r24
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#pass
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/*
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* test relax
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* b <-> b! : jump range must be in 8 bit, only 32b -> 16b
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* Author: ligang
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*/
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.macro tran insn32, insn16
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/* This block transform 32b instruction to 16b. */
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.align 4
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\insn32 #32b -> 16b
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\insn16
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\insn32 #32b -> 16b
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\insn32 #32b -> 16b
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\insn16
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\insn32 #32b -> 16b
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\insn32 #No transform
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add r18, r20, r24
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.endm
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L1:
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tran "b L1", "b! L1"
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#tran "b 0x8", "b! 0x8"
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@ -0,0 +1,36 @@
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#as:
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#objdump: -d
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#source: bittst.s
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.*: +file format .*
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Disassembly of section \.text:
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00000000 <\.text>:
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0: 6016 bittst! r0, 0x2
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2: 6016 bittst! r0, 0x2
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4: 6f26 bittst! r15, 0x4
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6: 6f26 bittst! r15, 0x4
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8: 6f0e bittst! r15, 0x1
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a: 6f0e bittst! r15, 0x1
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c: 6f1e bittst! r15, 0x3
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e: 6f1e bittst! r15, 0x3
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10: 6816 bittst! r8, 0x2
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12: 6816 bittst! r8, 0x2
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14: 800f842d bittst.c r15, 0x1
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18: 801a902d bittst.c r26, 0x4
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1c: 0000 nop!
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1e: 0000 nop!
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20: 8000882d bittst.c r0, 0x2
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24: 8014882d bittst.c r20, 0x2
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28: 81ef902d bittst.c r15, 0x4
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2c: 8019902d bittst.c r25, 0x4
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30: 81ef842d bittst.c r15, 0x1
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34: 8019842d bittst.c r25, 0x1
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38: 680e bittst! r8, 0x1
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3a: 680e bittst! r8, 0x1
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3c: 6626 bittst! r6, 0x4
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3e: 6626 bittst! r6, 0x4
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40: 671e bittst! r7, 0x3
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42: 671e bittst! r7, 0x3
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#pass
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/*
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* test relax
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* bittst.c <-> bittst! : register number must be in 0-15
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* Author: ligang
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*/
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/* This macro transform 32b instruction to 16b. */
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.macro tran3216 insn32, insn16
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\insn32 r0, 2 #32b -> 16b
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\insn16 r0, 2
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\insn32 r15, 4 #32b -> 16b
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\insn16 r15, 4
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\insn32 r15, 1 #32b -> 16b
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\insn16 r15, 1
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\insn16 r15, 3
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\insn32 r15, 3 #32b -> 16b
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\insn32 r8, 2 #32b -> 16b
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\insn32 r8, 2 #32b -> 16b
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\insn32 r15, 1 #No transform
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\insn32 r26, 4
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.endm
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/* This macro transform 16b instruction to 32b. */
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.macro tran1632 insn32, insn16
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.align 4
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\insn16 r0, 2 #16b -> 32b
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\insn32 r20, 2
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\insn16 r15, 4 #16b -> 32b
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\insn32 r25, 4
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\insn16 r15, 1 #16b -> 32b
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\insn32 r25, 1
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\insn16 r8, 1 #No transform
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\insn16 r8, 1 #No transform
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\insn16 r6, 4 #No transform
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\insn32 r6, 4 #32b -> 16b
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\insn32 r7, 3 #32b -> 16b
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\insn16 r7, 3 #No transform
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.endm
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.text
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tran3216 "bittst.c", "bittst!"
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tran1632 "bittst.c", "bittst!"
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#as:
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#objdump: -d
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#source: br.s
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.*: +file format .*
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Disassembly of section \.text:
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00000000 <.text>:
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0: 0f04 br! r0
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2: 0f04 br! r0
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4: 0ff4 br! r15
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6: 0ff4 br! r15
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8: 0f34 br! r3
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a: 0f34 br! r3
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c: 0f54 br! r5
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e: 0f54 br! r5
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10: 8003bc08 br r3
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14: 801fbc08 br r31
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...
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20: 0f0c brl! r0
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22: 0f0c brl! r0
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24: 0ffc brl! r15
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26: 0ffc brl! r15
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28: 0f3c brl! r3
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2a: 0f3c brl! r3
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2c: 0f5c brl! r5
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2e: 0f5c brl! r5
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30: 8003bc09 brl r3
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34: 801fbc09 brl r31
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...
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40: 8000bc08 br r0
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44: 8017bc08 br r23
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48: 800fbc08 br r15
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4c: 801bbc08 br r27
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50: 0f64 br! r6
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52: 0f64 br! r6
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54: 0f34 br! r3
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56: 0f34 br! r3
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...
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60: 8000bc09 brl r0
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64: 8017bc09 brl r23
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68: 800fbc09 brl r15
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6c: 801bbc09 brl r27
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70: 0f6c brl! r6
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72: 0f6c brl! r6
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74: 0f3c brl! r3
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76: 0f3c brl! r3
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#pass
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@ -0,0 +1,53 @@
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/*
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* test relax
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* br <-> br! : register number must be in 0-15
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* brl <-> brl! : register number must be in 0-15
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* Author: ligang
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*/
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/* This macro transform 32b instruction to 16b. */
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.macro tran3216 insn32, insn16
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.align 4
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\insn32 r0 #32b -> 16b
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\insn16 r0
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\insn32 r15 #32b -> 16b
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\insn16 r15
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\insn32 r3 #32b -> 16b
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\insn32 r3 #32b -> 16b
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\insn16 r5
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\insn32 r5 #32b -> 16b
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\insn32 r3 #No transform
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\insn32 r31 #No transform
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.endm
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/* This macro transform 16b instruction to 32b. */
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.macro tran1632 insn32, insn16
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.align 4
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\insn16 r0 #16b -> 32b
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\insn32 r23
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\insn16 r15 #16b -> 32b
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\insn32 r27
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\insn16 r6 #No transform
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\insn32 r6
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\insn16 r3 #No transform
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\insn16 r3
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.endm
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tran3216 "br", "br!"
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tran3216 "brl", "brl!"
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tran1632 "br", "br!"
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tran1632 "brl", "brl!"
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#as:
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#objdump: -d
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#source: ldi.s
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.*: +file format .*
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Disassembly of section \.text:
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00000000 <\.text>:
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0: 5200 ldiu! r2, 0
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2: 5200 ldiu! r2, 0
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4: 53ff ldiu! r3, 255
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6: 53ff ldiu! r3, 255
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8: 5409 ldiu! r4, 9
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a: 5409 ldiu! r4, 9
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c: 53ff ldiu! r3, 255
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e: 53ff ldiu! r3, 255
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10: 85188006 ldi r8, 0x3\(3\)
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14: 87388006 ldi r25, 0x3\(3\)
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...
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20: 84588000 ldi r2, 0x0\(0\)
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24: 87388000 ldi r25, 0x0\(0\)
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28: 847881fe ldi r3, 0xff\(255\)
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2c: 86f88002 ldi r23, 0x1\(1\)
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30: 5fff ldiu! r15, 255
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32: 5fff ldiu! r15, 255
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34: 5803 ldiu! r8, 3
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36: 5803 ldiu! r8, 3
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#pass
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@ -0,0 +1,53 @@
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/*
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* test relax
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* ldi <-> ldiu! : for ldiu! : register number must be in 0-15, simm16: [0-255]
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* (1)ldi rD, simm16 : rD = simm16
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* (2)ldiu! rD, imm8 : rD = ZE(imm8)
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* Author: ligang
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*/
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/* This macro transform 32b instruction to 16b. */
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.macro tran3216 insn32, insn16
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.align 4
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\insn32 r2, 0 #32b -> 16b
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\insn16 r2, 0
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\insn32 r3, 255 #32b -> 16b
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\insn16 r3, 255
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\insn32 r4, 9 #32b -> 16b
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\insn32 r4, 9 #32b -> 16b
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\insn16 r3, 255
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\insn32 r3, 255 #32b -> 16b
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\insn32 r8, 3 #No transform
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\insn32 r25, 3 #No transform
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.endm
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/* This macro transform 16b instruction to 32b. */
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.macro tran1632 insn32, insn16
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.align 4
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\insn16 r2, 0 #16b -> 32b
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\insn32 r25, 0
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\insn16 r3, 255 #16b -> 32b
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\insn32 r23, 1
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\insn16 r15, 255 #No transform
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\insn32 r15, 255
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\insn16 r8, 3 #No transform
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\insn16 r8, 3 #No transform
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.endm
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.text
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tran3216 "ldi", "ldiu!"
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tran1632 "ldi", "ldiu!"
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@ -0,0 +1,144 @@
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#as:
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#objdump: -d
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#source: ls32ls16.s
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.*: +file format .*
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Disassembly of section \.text:
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00000000 <.text>:
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...
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10: 2038 lw! r0, \[r3\]
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12: 2038 lw! r0, \[r3\]
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14: 23f8 lw! r3, \[r15\]
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16: 23f8 lw! r3, \[r15\]
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18: 2f88 lw! r15, \[r8\]
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1a: 2f88 lw! r15, \[r8\]
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1c: c0888000 lw r4, \[r8, 0\]
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20: c3338000 lw r25, \[r19, 0\]
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24: 2578 lw! r5, \[r7\]
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26: 2578 lw! r5, \[r7\]
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28: 2238 lw! r2, \[r3\]
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2a: 2238 lw! r2, \[r3\]
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...
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40: 2039 lh! r0, \[r3\]
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42: 2039 lh! r0, \[r3\]
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44: 23f9 lh! r3, \[r15\]
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46: 23f9 lh! r3, \[r15\]
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48: 2f89 lh! r15, \[r8\]
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4a: 2f89 lh! r15, \[r8\]
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4c: c4888000 lh r4, \[r8, 0\]
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50: c7338000 lh r25, \[r19, 0\]
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54: 2579 lh! r5, \[r7\]
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56: 2579 lh! r5, \[r7\]
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58: 2239 lh! r2, \[r3\]
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5a: 2239 lh! r2, \[r3\]
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...
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110: 203b lbu! r0, \[r3\]
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112: 203b lbu! r0, \[r3\]
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114: 23fb lbu! r3, \[r15\]
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116: 23fb lbu! r3, \[r15\]
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118: 2f8b lbu! r15, \[r8\]
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11a: 2f8b lbu! r15, \[r8\]
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11c: d8888000 lbu r4, \[r8, 0\]
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120: db338000 lbu r25, \[r19, 0\]
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124: 257b lbu! r5, \[r7\]
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126: 257b lbu! r5, \[r7\]
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128: 223b lbu! r2, \[r3\]
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12a: 223b lbu! r2, \[r3\]
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...
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210: 203c sw! r0, \[r3\]
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212: 203c sw! r0, \[r3\]
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214: 23fc sw! r3, \[r15\]
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216: 23fc sw! r3, \[r15\]
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218: 2f8c sw! r15, \[r8\]
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21a: 2f8c sw! r15, \[r8\]
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21c: d0888000 sw r4, \[r8, 0\]
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220: d3338000 sw r25, \[r19, 0\]
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224: 257c sw! r5, \[r7\]
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226: 257c sw! r5, \[r7\]
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228: 223c sw! r2, \[r3\]
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22a: 223c sw! r2, \[r3\]
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22c: 0000 nop!
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22e: 0000 nop!
|
||||
230: 203d sh! r0, \[r3\]
|
||||
232: 203d sh! r0, \[r3\]
|
||||
234: 23fd sh! r3, \[r15\]
|
||||
236: 23fd sh! r3, \[r15\]
|
||||
238: 2f8d sh! r15, \[r8\]
|
||||
23a: 2f8d sh! r15, \[r8\]
|
||||
23c: d4888000 sh r4, \[r8, 0\]
|
||||
240: d7338000 sh r25, \[r19, 0\]
|
||||
244: 257d sh! r5, \[r7\]
|
||||
246: 257d sh! r5, \[r7\]
|
||||
248: 223d sh! r2, \[r3\]
|
||||
24a: 223d sh! r2, \[r3\]
|
||||
24c: 0000 nop!
|
||||
24e: 0000 nop!
|
||||
250: 203f sb! r0, \[r3\]
|
||||
252: 203f sb! r0, \[r3\]
|
||||
254: 23ff sb! r3, \[r15\]
|
||||
256: 23ff sb! r3, \[r15\]
|
||||
258: 2f8f sb! r15, \[r8\]
|
||||
25a: 2f8f sb! r15, \[r8\]
|
||||
25c: dc888000 sb r4, \[r8, 0\]
|
||||
260: df338000 sb r25, \[r19, 0\]
|
||||
264: 257f sb! r5, \[r7\]
|
||||
266: 257f sb! r5, \[r7\]
|
||||
268: 223f sb! r2, \[r3\]
|
||||
26a: 223f sb! r2, \[r3\]
|
||||
26c: 0000 nop!
|
||||
26e: 0000 nop!
|
||||
270: c0038000 lw r0, \[r3, 0\]
|
||||
274: c257800a lw r18, \[r23, 10\]
|
||||
278: c1e08000 lw r15, \[r0, 0\]
|
||||
27c: c23a800a lw r17, \[r26, 10\]
|
||||
280: 2688 lw! r6, \[r8\]
|
||||
282: 2688 lw! r6, \[r8\]
|
||||
284: 2378 lw! r3, \[r7\]
|
||||
286: 2378 lw! r3, \[r7\]
|
||||
...
|
||||
290: c4038000 lh r0, \[r3, 0\]
|
||||
294: c657800a lh r18, \[r23, 10\]
|
||||
298: c5e08000 lh r15, \[r0, 0\]
|
||||
29c: c63a800a lh r17, \[r26, 10\]
|
||||
2a0: 2689 lh! r6, \[r8\]
|
||||
2a2: 2689 lh! r6, \[r8\]
|
||||
2a4: 2379 lh! r3, \[r7\]
|
||||
2a6: 2379 lh! r3, \[r7\]
|
||||
...
|
||||
2b0: d8038000 lbu r0, \[r3, 0\]
|
||||
2b4: da57800a lbu r18, \[r23, 10\]
|
||||
2b8: d9e08000 lbu r15, \[r0, 0\]
|
||||
2bc: da3a800a lbu r17, \[r26, 10\]
|
||||
2c0: 268b lbu! r6, \[r8\]
|
||||
2c2: 268b lbu! r6, \[r8\]
|
||||
2c4: 237b lbu! r3, \[r7\]
|
||||
2c6: 237b lbu! r3, \[r7\]
|
||||
...
|
||||
2d0: d0038000 sw r0, \[r3, 0\]
|
||||
2d4: d257800a sw r18, \[r23, 10\]
|
||||
2d8: d1e08000 sw r15, \[r0, 0\]
|
||||
2dc: d23a800a sw r17, \[r26, 10\]
|
||||
2e0: 268c sw! r6, \[r8\]
|
||||
2e2: 268c sw! r6, \[r8\]
|
||||
2e4: 237c sw! r3, \[r7\]
|
||||
2e6: 237c sw! r3, \[r7\]
|
||||
...
|
||||
2f0: d4038000 sh r0, \[r3, 0\]
|
||||
2f4: d657800a sh r18, \[r23, 10\]
|
||||
2f8: d5e08000 sh r15, \[r0, 0\]
|
||||
2fc: d63a800a sh r17, \[r26, 10\]
|
||||
300: 268d sh! r6, \[r8\]
|
||||
302: 268d sh! r6, \[r8\]
|
||||
304: 237d sh! r3, \[r7\]
|
||||
306: 237d sh! r3, \[r7\]
|
||||
...
|
||||
310: dc038000 sb r0, \[r3, 0\]
|
||||
314: de57800a sb r18, \[r23, 10\]
|
||||
318: dde08000 sb r15, \[r0, 0\]
|
||||
31c: de3a800a sb r17, \[r26, 10\]
|
||||
320: 268f sb! r6, \[r8\]
|
||||
322: 268f sb! r6, \[r8\]
|
||||
324: 237f sb! r3, \[r7\]
|
||||
326: 237f sb! r3, \[r7\]
|
|
@ -0,0 +1,70 @@
|
|||
/*
|
||||
* test relax
|
||||
* lw <-> lw! : register number must be in 0-15, offset == 0
|
||||
* lh <-> lh! : register number must be in 0-15, offset == 0
|
||||
* lbu <-> lbu! : register number must be in 0-15, offset == 0
|
||||
* sw <-> sw! : register number must be in 0-15, offset == 0
|
||||
* sh <-> sh! : register number must be in 0-15, offset == 0
|
||||
* sb <-> sb! : register number must be in 0-15, offset == 0
|
||||
|
||||
* Author: ligang
|
||||
*/
|
||||
|
||||
/* This macro transform 32b instruction to 16b. */
|
||||
.macro tran3216 insn32, insn16
|
||||
.align 4
|
||||
|
||||
\insn32 r0, [r3, 0] #32b -> 16b
|
||||
\insn16 r0, [r3]
|
||||
|
||||
\insn32 r3, [r15, 0] #32b -> 16b
|
||||
\insn16 r3, [r15]
|
||||
|
||||
\insn32 r15, [r8, 0] #32b -> 16b
|
||||
\insn16 r15, [r8]
|
||||
|
||||
\insn32 r4, [r8, 0] #No transform
|
||||
\insn32 r25, [r19, 0]
|
||||
|
||||
\insn32 r5, [r7, 0] #32b -> 16b
|
||||
\insn32 r5, [r7, 0] #32b -> 16b
|
||||
|
||||
\insn16 r2, [r3]
|
||||
\insn32 r2, [r3, 0] #32b -> 16b
|
||||
|
||||
.endm
|
||||
|
||||
/* This macro transform 16b instruction to 32b. */
|
||||
.macro tran1632 insn32, insn16
|
||||
.align 4
|
||||
|
||||
\insn16 r0, [r3] #16b -> 32b
|
||||
\insn32 r18, [r23, 10]
|
||||
|
||||
\insn16 r15, [r0] #16b -> 32b
|
||||
\insn32 r17, [r26, 10]
|
||||
|
||||
\insn16 r6, [r8] #No transform
|
||||
\insn16 r6, [r8] #No transform
|
||||
|
||||
\insn16 r3, [r7] #No transform
|
||||
\insn32 r3, [r7, 0]
|
||||
|
||||
.endm
|
||||
.space 1
|
||||
tran3216 "lw", "lw!"
|
||||
.fill 10, 1
|
||||
tran3216 "lh", "lh!"
|
||||
.org 0x101
|
||||
tran3216 "lbu", "lbu!"
|
||||
.org 0x203
|
||||
tran3216 "sw", "sw!"
|
||||
tran3216 "sh", "sh!"
|
||||
tran3216 "sb", "sb!"
|
||||
|
||||
tran1632 "lw", "lw!"
|
||||
tran1632 "lh", "lh!"
|
||||
tran1632 "lbu", "lbu!"
|
||||
tran1632 "sw", "sw!"
|
||||
tran1632 "sh", "sh!"
|
||||
tran1632 "sb", "sb!"
|
|
@ -0,0 +1,135 @@
|
|||
#as:
|
||||
#objdump: -d
|
||||
#source: ls32ls16p.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <.text>:
|
||||
0: 7320 lwp! r3, 16
|
||||
2: 7320 lwp! r3, 16
|
||||
4: 7460 lwp! r4, 48
|
||||
6: 7460 lwp! r4, 48
|
||||
8: 7790 lwp! r7, 72
|
||||
a: 7790 lwp! r7, 72
|
||||
c: 7840 lwp! r8, 32
|
||||
e: 7840 lwp! r8, 32
|
||||
10: c0a28080 lw r5, \[r2, 128\]
|
||||
14: c0a28080 lw r5, \[r2, 128\]
|
||||
18: c0c68020 lw r6, \[r6, 32\]
|
||||
1c: c0c68020 lw r6, \[r6, 32\]
|
||||
20: 7321 lhp! r3, 8
|
||||
22: 7321 lhp! r3, 8
|
||||
24: 7461 lhp! r4, 24
|
||||
26: 7461 lhp! r4, 24
|
||||
28: 7791 lhp! r7, 36
|
||||
2a: 7791 lhp! r7, 36
|
||||
2c: 7841 lhp! r8, 16
|
||||
2e: 7841 lhp! r8, 16
|
||||
30: c4a28040 lh r5, \[r2, 64\]
|
||||
34: c4a28040 lh r5, \[r2, 64\]
|
||||
38: c4c68010 lh r6, \[r6, 16\]
|
||||
3c: c4c68010 lh r6, \[r6, 16\]
|
||||
40: 7323 lbup! r3, 4
|
||||
42: 7323 lbup! r3, 4
|
||||
44: 7463 lbup! r4, 12
|
||||
46: 7463 lbup! r4, 12
|
||||
48: 7793 lbup! r7, 18
|
||||
4a: 7793 lbup! r7, 18
|
||||
4c: 7843 lbup! r8, 8
|
||||
4e: 7843 lbup! r8, 8
|
||||
50: d8a28020 lbu r5, \[r2, 32\]
|
||||
54: d8a28020 lbu r5, \[r2, 32\]
|
||||
58: d8c68008 lbu r6, \[r6, 8\]
|
||||
5c: d8c68008 lbu r6, \[r6, 8\]
|
||||
60: 7324 swp! r3, 16
|
||||
62: 7324 swp! r3, 16
|
||||
64: 7464 swp! r4, 48
|
||||
66: 7464 swp! r4, 48
|
||||
68: 7794 swp! r7, 72
|
||||
6a: 7794 swp! r7, 72
|
||||
6c: 7844 swp! r8, 32
|
||||
6e: 7844 swp! r8, 32
|
||||
70: d0a28080 sw r5, \[r2, 128\]
|
||||
74: d0a28080 sw r5, \[r2, 128\]
|
||||
78: d0c68020 sw r6, \[r6, 32\]
|
||||
7c: d0c68020 sw r6, \[r6, 32\]
|
||||
80: 7325 shp! r3, 8
|
||||
82: 7325 shp! r3, 8
|
||||
84: 7465 shp! r4, 24
|
||||
86: 7465 shp! r4, 24
|
||||
88: 7795 shp! r7, 36
|
||||
8a: 7795 shp! r7, 36
|
||||
8c: 7845 shp! r8, 16
|
||||
8e: 7845 shp! r8, 16
|
||||
90: d4a28040 sh r5, \[r2, 64\]
|
||||
94: d4a28040 sh r5, \[r2, 64\]
|
||||
98: d4c68010 sh r6, \[r6, 16\]
|
||||
9c: d4c68010 sh r6, \[r6, 16\]
|
||||
a0: 7327 sbp! r3, 4
|
||||
a2: 7327 sbp! r3, 4
|
||||
a4: 7467 sbp! r4, 12
|
||||
a6: 7467 sbp! r4, 12
|
||||
a8: 7797 sbp! r7, 18
|
||||
aa: 7797 sbp! r7, 18
|
||||
ac: 7847 sbp! r8, 8
|
||||
ae: 7847 sbp! r8, 8
|
||||
b0: dca28020 sb r5, \[r2, 32\]
|
||||
b4: dca28020 sb r5, \[r2, 32\]
|
||||
b8: dcc68008 sb r6, \[r6, 8\]
|
||||
bc: dcc68008 sb r6, \[r6, 8\]
|
||||
c0: c002800c lw r0, \[r2, 12\]
|
||||
c4: c00580ff lw r0, \[r5, 255\]
|
||||
c8: c1e28000 lw r15, \[r2, 0\]
|
||||
cc: c1e480ff lw r15, \[r4, 255\]
|
||||
d0: 7410 lwp! r4, 8
|
||||
d2: 7410 lwp! r4, 8
|
||||
d4: 7710 lwp! r7, 8
|
||||
d6: 7740 lwp! r7, 32
|
||||
...
|
||||
e0: c402800c lh r0, \[r2, 12\]
|
||||
e4: c40580ff lh r0, \[r5, 255\]
|
||||
e8: c5e28000 lh r15, \[r2, 0\]
|
||||
ec: c5e480ff lh r15, \[r4, 255\]
|
||||
f0: 7421 lhp! r4, 8
|
||||
f2: 7421 lhp! r4, 8
|
||||
f4: 7721 lhp! r7, 8
|
||||
f6: 7741 lhp! r7, 16
|
||||
...
|
||||
100: d802800c lbu r0, \[r2, 12\]
|
||||
104: d80580ff lbu r0, \[r5, 255\]
|
||||
108: d9e28000 lbu r15, \[r2, 0\]
|
||||
10c: d9e480ff lbu r15, \[r4, 255\]
|
||||
110: 7443 lbup! r4, 8
|
||||
112: 7443 lbup! r4, 8
|
||||
114: 7743 lbup! r7, 8
|
||||
116: 7743 lbup! r7, 8
|
||||
...
|
||||
120: d002800c sw r0, \[r2, 12\]
|
||||
124: d00580ff sw r0, \[r5, 255\]
|
||||
128: d1e28000 sw r15, \[r2, 0\]
|
||||
12c: d1e480ff sw r15, \[r4, 255\]
|
||||
130: 7414 swp! r4, 8
|
||||
132: 7414 swp! r4, 8
|
||||
134: 7714 swp! r7, 8
|
||||
136: 7744 swp! r7, 32
|
||||
...
|
||||
140: d402800c sh r0, \[r2, 12\]
|
||||
144: d40580ff sh r0, \[r5, 255\]
|
||||
148: d5e28000 sh r15, \[r2, 0\]
|
||||
14c: d5e480ff sh r15, \[r4, 255\]
|
||||
150: 7425 shp! r4, 8
|
||||
152: 7425 shp! r4, 8
|
||||
154: 7725 shp! r7, 8
|
||||
156: 7745 shp! r7, 16
|
||||
...
|
||||
160: dc02800c sb r0, \[r2, 12\]
|
||||
164: dc0580ff sb r0, \[r5, 255\]
|
||||
168: dde28000 sb r15, \[r2, 0\]
|
||||
16c: dde480ff sb r15, \[r4, 255\]
|
||||
170: 7447 sbp! r4, 8
|
||||
172: 7447 sbp! r4, 8
|
||||
174: 7747 sbp! r7, 8
|
||||
176: 7747 sbp! r7, 8
|
||||
#pass
|
|
@ -0,0 +1,68 @@
|
|||
/*
|
||||
* test relax
|
||||
* lw <-> lwp! : rs = r2, offset & 0x3 == 0, offset >> 2 : 5b
|
||||
* lh <-> lhp! : rs = r2, offset & 0x1 == 0, offset >> 1 : 5b
|
||||
* lbu <-> lbu! : rs = r2, offset != 0, offset : 5b
|
||||
* sw <-> swp! : rs = r2, offset & 0x3 == 0, offset >> 2 : 5b
|
||||
* sh <-> shp! : rs = r2, offset & 0x1 == 0, offset >> 1 : 5b
|
||||
* sb <-> sb! : rs = r2, offset != 0, offset : 5b
|
||||
|
||||
* Author: ligang
|
||||
*/
|
||||
|
||||
/* This macro transform 32b instruction to 16b. */
|
||||
.macro tran3216 insn32, insn16, shift
|
||||
.align 4
|
||||
|
||||
\insn32 r3, [r2, 0x4 << \shift] #32b -> 16b
|
||||
\insn16 r3, 0x4 << \shift
|
||||
|
||||
\insn32 r4, [r2, 0xC << \shift] #32b -> 16b
|
||||
\insn16 r4, 0xC << \shift
|
||||
|
||||
\insn32 r7, [r2, 0x12 << \shift] #32b -> 16b
|
||||
\insn32 r7, [r2, 0x12 << \shift] #32b -> 16b
|
||||
|
||||
\insn16 r8, 0x8 << \shift
|
||||
\insn32 r8, [r2, 0x8 << \shift] #32b -> 16b
|
||||
|
||||
\insn32 r5, [r2, 0x20 << \shift] #No transform
|
||||
\insn32 r5, [r2, 0x20 << \shift] #No transform
|
||||
|
||||
\insn32 r6, [r6, 0x8 << \shift] #No transform
|
||||
\insn32 r6, [r6, 0x8 << \shift] #No transform
|
||||
|
||||
.endm
|
||||
|
||||
/* This macro transform 16b instruction to 32b. */
|
||||
.macro tran1632 insn32, insn16, shift
|
||||
.align 4
|
||||
|
||||
\insn16 r0, 0xC #16b -> 32b
|
||||
\insn32 r0, [r5, 0xFF]
|
||||
|
||||
\insn16 r15, 0x0 #16b -> 32b
|
||||
\insn32 r15, [r4, 0xFF]
|
||||
|
||||
\insn16 r4, 0x8 #No transform
|
||||
\insn16 r4, 0x8 #No transform
|
||||
|
||||
\insn16 r7, 0x8 #No transform
|
||||
\insn32 r7, [r2, 0x8 << \shift]
|
||||
|
||||
.endm
|
||||
|
||||
tran3216 "lw", "lwp!", 2
|
||||
tran3216 "lh", "lhp!", 1
|
||||
tran3216 "lbu", "lbup!", 0
|
||||
tran3216 "sw", "swp!", 2
|
||||
tran3216 "sh", "shp!", 1
|
||||
tran3216 "sb", "sbp!", 0
|
||||
|
||||
tran1632 "lw", "lwp!", 2
|
||||
tran1632 "lh", "lhp!", 1
|
||||
tran1632 "lbu", "lbup!", 0
|
||||
tran1632 "sw", "swp!", 2
|
||||
tran1632 "sh", "shp!", 1
|
||||
tran1632 "sb", "sbp!", 0
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
#as:
|
||||
#objdump: -d
|
||||
#source: move.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <.text>:
|
||||
0: 00f3 mv! r0, r15
|
||||
2: 00f3 mv! r0, r15
|
||||
4: 0ff3 mv! r15, r15
|
||||
6: 0ff3 mv! r15, r15
|
||||
8: 0353 mv! r3, r5
|
||||
a: 0353 mv! r3, r5
|
||||
c: 0673 mv! r6, r7
|
||||
e: 0673 mv! r6, r7
|
||||
10: 810abc56 mv r8, r10
|
||||
14: 82b7bc56 mv r21, r23
|
||||
...
|
||||
20: 800fbc56 mv r0, r15
|
||||
24: 82fbbc56 mv r23, r27
|
||||
28: 0283 mv! r2, r8
|
||||
2a: 0283 mv! r2, r8
|
||||
2c: 0283 mv! r2, r8
|
||||
2e: 0283 mv! r2, r8
|
||||
30: 0f02 mhfl! r31, r0
|
||||
32: 0f02 mhfl! r31, r0
|
||||
34: 00f2 mhfl! r16, r15
|
||||
36: 00f2 mhfl! r16, r15
|
||||
38: 0752 mhfl! r23, r5
|
||||
3a: 0752 mhfl! r23, r5
|
||||
3c: 0a72 mhfl! r26, r7
|
||||
3e: 0a72 mhfl! r26, r7
|
||||
40: 838abc56 mv gp, r10
|
||||
44: 82b7bc56 mv r21, r23
|
||||
...
|
||||
50: 83e0bc56 mv r31, r0
|
||||
54: 82fbbc56 mv r23, r27
|
||||
58: 0682 mhfl! r22, r8
|
||||
5a: 0682 mhfl! r22, r8
|
||||
5c: 07f2 mhfl! r23, r15
|
||||
5e: 07f2 mhfl! r23, r15
|
||||
60: 00f1 mlfh! r0, r31
|
||||
62: 00f1 mlfh! r0, r31
|
||||
64: 0f01 mlfh! r15, r16
|
||||
66: 0f01 mlfh! r15, r16
|
||||
68: 0571 mlfh! r5, r23
|
||||
6a: 0571 mlfh! r5, r23
|
||||
6c: 07a1 mlfh! r7, r26
|
||||
6e: 07a1 mlfh! r7, r26
|
||||
70: 815cbc56 mv r10, gp
|
||||
74: 82b7bc56 mv r21, r23
|
||||
...
|
||||
80: 801fbc56 mv r0, r31
|
||||
84: 82fbbc56 mv r23, r27
|
||||
88: 0861 mlfh! r8, r22
|
||||
8a: 0861 mlfh! r8, r22
|
||||
8c: 0f71 mlfh! r15, r23
|
||||
8e: 0f71 mlfh! r15, r23
|
|
@ -0,0 +1,98 @@
|
|||
/*
|
||||
* test relax
|
||||
* mv <-> mv! : for mv! : register number must be in 0-15
|
||||
* mv <-> mhfl! : for mhfl! : rD must be in 16-31, rS must be in 0-15
|
||||
* mv <-> mlfh! : for mhfl! : rD must be in 0-15, rS must be in 16-31
|
||||
|
||||
* Author: ligang
|
||||
*/
|
||||
|
||||
/* This block test mv -> mv! */
|
||||
.align 4
|
||||
|
||||
mv r0, r15 #32b -> 16b
|
||||
mv! r0, r15
|
||||
|
||||
mv r15, r15 #32b -> 16b
|
||||
mv! r15, r15
|
||||
|
||||
mv r3, r5 #32b -> 16b
|
||||
mv r3, r5 #32b -> 16b
|
||||
|
||||
mv! r6, r7
|
||||
mv r6, r7 #32b -> 16b
|
||||
|
||||
mv r8, r10 #No transform
|
||||
mv r21, r23
|
||||
|
||||
/* This block test mv! -> mv */
|
||||
.align 4
|
||||
|
||||
mv! r0, r15 #16b -> 32b
|
||||
mv r23, r27
|
||||
|
||||
mv! r2, r8 #No transform
|
||||
mv! r2, r8 #No transform
|
||||
|
||||
mv! r2, r8 #No transform
|
||||
mv r2, r8
|
||||
|
||||
/* This block test mv -> mhfl! */
|
||||
.align 4
|
||||
|
||||
mv r31, r0 #32b -> 16b
|
||||
mhfl! r31, r0
|
||||
|
||||
mv r16, r15 #32b -> 16b
|
||||
mv! r16, r15
|
||||
|
||||
mv r23, r5 #32b -> 16b
|
||||
mv r23, r5 #32b -> 16b
|
||||
|
||||
mhfl! r26, r7
|
||||
mv r26, r7 #32b -> 16b
|
||||
|
||||
mv r28, r10 #No transform
|
||||
mv r21, r23
|
||||
|
||||
/* This block test mhfl! -> mv */
|
||||
.align 4
|
||||
|
||||
mhfl! r31, r0 #16b -> 32b
|
||||
mv r23, r27
|
||||
|
||||
mhfl! r22, r8 #No transform
|
||||
mhfl! r22, r8 #No transform
|
||||
|
||||
mhfl! r23, r15 #No transform
|
||||
mv r23, r15
|
||||
|
||||
/* This block test mv -> mlfh! */
|
||||
.align 4
|
||||
|
||||
mv r0, r31 #32b -> 16b
|
||||
mlfh! r0, r31
|
||||
|
||||
mv r15, r16 #32b -> 16b
|
||||
mv! r15, r16
|
||||
|
||||
mv r5, r23 #32b -> 16b
|
||||
mv r5, r23 #32b -> 16b
|
||||
|
||||
mlfh! r7, r26
|
||||
mv r7, r26 #32b -> 16b
|
||||
|
||||
mv r10, r28 #No transform
|
||||
mv r21, r23
|
||||
|
||||
/* This block test mhfl! -> mv */
|
||||
.align 4
|
||||
|
||||
mlfh! r0, r31 #16b -> 32b
|
||||
mv r23, r27
|
||||
|
||||
mlfh! r8, r22 #No transform
|
||||
mlfh! r8, r22 #No transform
|
||||
|
||||
mlfh! r15, r23 #No transform
|
||||
mv r15, r23
|
|
@ -0,0 +1,15 @@
|
|||
#as:
|
||||
#objdump: -d
|
||||
#source: nop.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
...
|
||||
c: 80008000 nop
|
||||
10: 8254e010 add r18, r20, r24
|
||||
...
|
||||
28: 80008000 nop
|
||||
2c: 8254e026 xor r18, r20, r24
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* test relax
|
||||
* nop <-> nop!
|
||||
|
||||
* Author: ligang
|
||||
*/
|
||||
|
||||
.macro tran insn32, insn16
|
||||
/* This block transform 32b instruction to 16b. */
|
||||
.align 4
|
||||
|
||||
\insn32 #32b -> 16b
|
||||
\insn16
|
||||
|
||||
\insn32 #32b -> 16b
|
||||
\insn32 #32b -> 16b
|
||||
|
||||
\insn16
|
||||
\insn32 #32b -> 16b
|
||||
|
||||
\insn32 #No transform
|
||||
add r18, r20, r24
|
||||
|
||||
/* This block transform 16b instruction to 32b. */
|
||||
.align 4
|
||||
|
||||
\insn16 #No transform
|
||||
\insn32
|
||||
|
||||
\insn16 #No transform
|
||||
\insn16
|
||||
|
||||
\insn16 #16b -> 32b
|
||||
xor r18, r20, r24
|
||||
|
||||
.endm
|
||||
|
||||
tran "nop", "nop!"
|
|
@ -0,0 +1,32 @@
|
|||
#as:
|
||||
#objdump: -d
|
||||
#source: postlw.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: 27fa pop! r23, \[r7\]
|
||||
2: 27fa pop! r23, \[r7\]
|
||||
4: 202a pop! r0, \[r2\]
|
||||
6: 202a pop! r0, \[r2\]
|
||||
8: 2f0a pop! r15, \[r0\]
|
||||
a: 2f0a pop! r15, \[r0\]
|
||||
c: 2f7a pop! r15, \[r7\]
|
||||
e: 2f7a pop! r15, \[r7\]
|
||||
10: 29ba pop! r25, \[r3\]
|
||||
12: 29ba pop! r25, \[r3\]
|
||||
14: 9f0d8020 lw r24, \[r13\]\+, 4
|
||||
18: 9ee78028 lw r23, \[r7\]\+, 5
|
||||
1c: 0000 nop!
|
||||
1e: 0000 nop!
|
||||
20: 9c078020 lw r0, \[r7\]\+, 4
|
||||
24: 9f2d8020 lw r25, \[r13\]\+, 4
|
||||
28: 9f208020 lw r25, \[r0\]\+, 4
|
||||
2c: 9e578020 lw r18, \[r23\]\+, 4
|
||||
30: 263a pop! r6, \[r3\]
|
||||
32: 263a pop! r6, \[r3\]
|
||||
34: 237a pop! r3, \[r7\]
|
||||
36: 237a pop! r3, \[r7\]
|
||||
#pass
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* test relax
|
||||
* post lw <-> pop! : offset == 4
|
||||
* syntax:
|
||||
lw rD, [rA]+, simm12 : rD and rA can be 0-31
|
||||
pop! rD, [rAg0] : rAg0 must be in 0-7, rD can be 0-31
|
||||
|
||||
* Author: ligang
|
||||
*/
|
||||
|
||||
/* This macro transform 32b instruction to 16b. */
|
||||
.macro tran3216 insn32, insn16
|
||||
.align 4
|
||||
|
||||
\insn32 r23, [r7]+, 4 #32b -> 16b
|
||||
\insn16 r23, [r7]
|
||||
|
||||
\insn32 r0, [r2]+, 4 #32b -> 16b
|
||||
\insn16 r0, [r2]
|
||||
|
||||
\insn32 r15, [r0]+, 4 #32b -> 16b
|
||||
\insn16 r15, [r0]
|
||||
|
||||
\insn16 r15, [r7]
|
||||
\insn32 r15, [r7]+, 4 #32b -> 16b
|
||||
|
||||
\insn32 r25, [r3]+, 4 #32b -> 16b
|
||||
\insn32 r25, [r3]+, 4 #32b -> 16b
|
||||
|
||||
\insn32 r24, [r13]+, 4 #No transform
|
||||
\insn32 r23, [r7]+, 5 #No transform
|
||||
|
||||
.endm
|
||||
|
||||
/* This macro transform 16b instruction to 32b. */
|
||||
.macro tran1632 insn32, insn16
|
||||
.align 4
|
||||
|
||||
\insn16 r0, [r7] #16b -> 32b
|
||||
\insn32 r25, [r13]+, 4
|
||||
|
||||
\insn16 r25, [r0] #16b -> 32b
|
||||
\insn32 r18, [r23]+, 4
|
||||
|
||||
\insn16 r6, [r3] #No transform
|
||||
\insn16 r6, [r3] #No transform
|
||||
|
||||
\insn16 r3, [r7] #No transform
|
||||
\insn32 r3, [r7]+, 4
|
||||
|
||||
.endm
|
||||
|
||||
tran3216 "lw", "pop!"
|
||||
tran1632 "lw", "pop!"
|
|
@ -0,0 +1,32 @@
|
|||
#as:
|
||||
#objdump: -d
|
||||
#source: presw.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <.text>:
|
||||
0: 202e push! r0, \[r2\]
|
||||
2: 202e push! r0, \[r2\]
|
||||
4: 27fe push! r23, \[r7\]
|
||||
6: 27fe push! r23, \[r7\]
|
||||
8: 2f0e push! r15, \[r0\]
|
||||
a: 2f0e push! r15, \[r0\]
|
||||
c: 2f7e push! r15, \[r7\]
|
||||
e: 2f7e push! r15, \[r7\]
|
||||
10: 29be push! r25, \[r3\]
|
||||
12: 29be push! r25, \[r3\]
|
||||
14: 8f0dffe4 sw r24, \[r13, -4\]\+
|
||||
18: 8ee7ffdc sw r23, \[r7, -5\]\+
|
||||
1c: 0000 nop!
|
||||
1e: 0000 nop!
|
||||
20: 8c07ffe4 sw r0, \[r7, -4\]\+
|
||||
24: 8f2dffe4 sw r25, \[r13, -4\]\+
|
||||
28: 8f20ffe4 sw r25, \[r0, -4\]\+
|
||||
2c: 8e57ffe4 sw r18, \[r23, -4\]\+
|
||||
30: 263e push! r6, \[r3\]
|
||||
32: 263e push! r6, \[r3\]
|
||||
34: 237e push! r3, \[r7\]
|
||||
36: 237e push! r3, \[r7\]
|
||||
#pass
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* test relax
|
||||
* pre sw <-> push! : offset == -4
|
||||
* syntax:
|
||||
sw rD, [rA, simm12]+ : rD and rA can be 0-31
|
||||
push! rD, [rAg0] : rAg0 must be in 0-7, rD can be 0-31
|
||||
|
||||
* Author: ligang
|
||||
*/
|
||||
|
||||
/* This macro transform 32b instruction to 16b. */
|
||||
.macro tran3216 insn32, insn16
|
||||
.align 4
|
||||
|
||||
\insn32 r0, [r2, -4]+ #32b -> 16b
|
||||
\insn16 r0, [r2]
|
||||
|
||||
\insn32 r23, [r7, -4]+ #32b -> 16b
|
||||
\insn16 r23, [r7]
|
||||
|
||||
\insn32 r15, [r0, -4]+ #32b -> 16b
|
||||
\insn16 r15, [r0]
|
||||
|
||||
\insn16 r15, [r7]
|
||||
\insn32 r15, [r7, -4]+ #32b -> 16b
|
||||
|
||||
\insn32 r25, [r3, -4]+ #32b -> 16b
|
||||
\insn32 r25, [r3, -4]+ #32b -> 16b
|
||||
|
||||
\insn32 r24, [r13, -4]+ #No transform
|
||||
\insn32 r23, [r7, -5]+ #No transform
|
||||
|
||||
.endm
|
||||
|
||||
/* This macro transform 16b instruction to 32b. */
|
||||
.macro tran1632 insn32, insn16
|
||||
.align 4
|
||||
|
||||
\insn16 r0, [r7] #16b -> 32b
|
||||
\insn32 r25, [r13, -4]+
|
||||
|
||||
\insn16 r25, [r0] #16b -> 32b
|
||||
\insn32 r18, [r23, -4]+
|
||||
|
||||
\insn16 r6, [r3] #No transform
|
||||
\insn16 r6, [r3] #No transform
|
||||
|
||||
\insn16 r3, [r7] #No transform
|
||||
\insn32 r3, [r7, -4]+
|
||||
|
||||
.endm
|
||||
|
||||
tran3216 "sw", "push!"
|
||||
tran1632 "sw", "push!"
|
|
@ -0,0 +1,90 @@
|
|||
#as:
|
||||
#objdump: -d
|
||||
#source: rD_rA.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: 2076 not! r0, r7
|
||||
2: 2076 not! r0, r7
|
||||
4: 2f46 not! r15, r4
|
||||
6: 2f46 not! r15, r4
|
||||
8: 2ff6 not! r15, r15
|
||||
a: 2ff6 not! r15, r15
|
||||
c: 2f36 not! r15, r3
|
||||
e: 2f36 not! r15, r3
|
||||
10: 2826 not! r8, r2
|
||||
12: 2826 not! r8, r2
|
||||
14: 81e58025 not.c r15, r5
|
||||
18: 83578025 not.c r26, r23
|
||||
1c: 0000 nop!
|
||||
1e: 0000 nop!
|
||||
20: 2072 neg! r0, r7
|
||||
22: 2072 neg! r0, r7
|
||||
24: 2f42 neg! r15, r4
|
||||
26: 2f42 neg! r15, r4
|
||||
28: 2ff2 neg! r15, r15
|
||||
2a: 2ff2 neg! r15, r15
|
||||
2c: 2f32 neg! r15, r3
|
||||
2e: 2f32 neg! r15, r3
|
||||
30: 2822 neg! r8, r2
|
||||
32: 2822 neg! r8, r2
|
||||
34: 81e0941f neg.c r15, r5
|
||||
38: 8340dc1f neg.c r26, r23
|
||||
3c: 0000 nop!
|
||||
3e: 0000 nop!
|
||||
40: 2073 cmp! r0, r7
|
||||
42: 2073 cmp! r0, r7
|
||||
44: 2f43 cmp! r15, r4
|
||||
46: 2f43 cmp! r15, r4
|
||||
48: 2ff3 cmp! r15, r15
|
||||
4a: 2ff3 cmp! r15, r15
|
||||
4c: 2f33 cmp! r15, r3
|
||||
4e: 2f33 cmp! r15, r3
|
||||
50: 2823 cmp! r8, r2
|
||||
52: 2823 cmp! r8, r2
|
||||
54: 806f9419 cmp.c r15, r5
|
||||
58: 807adc19 cmp.c r26, r23
|
||||
5c: 0000 nop!
|
||||
5e: 0000 nop!
|
||||
60: 80008825 not.c r0, r0
|
||||
64: 82958025 not.c r20, r21
|
||||
68: 81ef9025 not.c r15, r15
|
||||
6c: 83358025 not.c r25, r21
|
||||
70: 81ef8c25 not.c r15, r15
|
||||
74: 83368025 not.c r25, r22
|
||||
78: 2836 not! r8, r3
|
||||
7a: 2836 not! r8, r3
|
||||
7c: 2626 not! r6, r2
|
||||
7e: 2626 not! r6, r2
|
||||
80: 2746 not! r7, r4
|
||||
82: 2746 not! r7, r4
|
||||
...
|
||||
90: 8000881f neg.c r0, r2
|
||||
94: 8280d41f neg.c r20, r21
|
||||
98: 81ef901f neg.c r15, r4
|
||||
9c: 8320d41f neg.c r25, r21
|
||||
a0: 81ef8c1f neg.c r15, r3
|
||||
a4: 8320d81f neg.c r25, r22
|
||||
a8: 2832 neg! r8, r3
|
||||
aa: 2832 neg! r8, r3
|
||||
ac: 2622 neg! r6, r2
|
||||
ae: 2622 neg! r6, r2
|
||||
b0: 2742 neg! r7, r4
|
||||
b2: 2742 neg! r7, r4
|
||||
...
|
||||
c0: 80608819 cmp.c r0, r2
|
||||
c4: 8074d419 cmp.c r20, r21
|
||||
c8: 806f9019 cmp.c r15, r4
|
||||
cc: 8079d419 cmp.c r25, r21
|
||||
d0: 806f8c19 cmp.c r15, r3
|
||||
d4: 8079d819 cmp.c r25, r22
|
||||
d8: 2833 cmp! r8, r3
|
||||
da: 2833 cmp! r8, r3
|
||||
dc: 2623 cmp! r6, r2
|
||||
de: 2623 cmp! r6, r2
|
||||
e0: 2743 cmp! r7, r4
|
||||
e2: 2743 cmp! r7, r4
|
||||
#pass
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* test relax
|
||||
* not.c <-> not! : register number must be in 0-15
|
||||
* neg.c <-> neg! : register number must be in 0-15
|
||||
* cmp.c <-> cmp! : register number must be in 0-15
|
||||
|
||||
* Author: ligang
|
||||
*/
|
||||
|
||||
/* This macro transform 32b instruction to 16b. */
|
||||
.macro tran3216 insn32, insn16
|
||||
.align 4
|
||||
|
||||
\insn32 r0, r7 #32b -> 16b
|
||||
\insn16 r0, r7
|
||||
|
||||
\insn32 r15, r4 #32b -> 16b
|
||||
\insn16 r15, r4
|
||||
|
||||
\insn32 r15, r15 #32b -> 16b
|
||||
\insn16 r15, r15
|
||||
|
||||
\insn16 r15, r3
|
||||
\insn32 r15, r3 #32b -> 16b
|
||||
|
||||
\insn32 r8, r2 #32b -> 16b
|
||||
\insn32 r8, r2 #32b -> 16b
|
||||
|
||||
\insn32 r15, r5 #No transform
|
||||
\insn32 r26, r23
|
||||
|
||||
.endm
|
||||
|
||||
/* This macro transform 16b instruction to 32b. */
|
||||
.macro tran1632 insn32, insn16
|
||||
.align 4
|
||||
|
||||
\insn16 r0, r2 #16b -> 32b
|
||||
\insn32 r20, r21
|
||||
|
||||
\insn16 r15, r4 #16b -> 32b
|
||||
\insn32 r25, r21
|
||||
|
||||
\insn16 r15, r3 #16b -> 32b
|
||||
\insn32 r25, r22
|
||||
|
||||
\insn16 r8, r3 #No transform
|
||||
\insn16 r8, r3 #No transform
|
||||
|
||||
\insn16 r6, r2 #No transform
|
||||
\insn32 r6, r2 #32b -> 16b
|
||||
|
||||
\insn32 r7, r4 #32b -> 16b
|
||||
\insn16 r7, r4 #No transform
|
||||
|
||||
.endm
|
||||
|
||||
.text
|
||||
|
||||
tran3216 "not.c", "not!"
|
||||
tran3216 "neg.c", "neg!"
|
||||
tran3216 "cmp.c", "cmp!"
|
||||
|
||||
tran1632 "not.c", "not!"
|
||||
tran1632 "neg.c", "neg!"
|
||||
tran1632 "cmp.c", "cmp!"
|
|
@ -0,0 +1,144 @@
|
|||
#as:
|
||||
#objdump: -d
|
||||
#source: rD_rA_BN.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: 6014 bitclr! r0, 0x2
|
||||
2: 6014 bitclr! r0, 0x2
|
||||
4: 6f24 bitclr! r15, 0x4
|
||||
6: 6f24 bitclr! r15, 0x4
|
||||
8: 6f0c bitclr! r15, 0x1
|
||||
a: 6f0c bitclr! r15, 0x1
|
||||
c: 6f1c bitclr! r15, 0x3
|
||||
e: 6f1c bitclr! r15, 0x3
|
||||
10: 681c bitclr! r8, 0x3
|
||||
12: 681c bitclr! r8, 0x3
|
||||
14: 81ef8429 bitclr.c r15, r15, 0x1
|
||||
18: 83579029 bitclr.c r26, r23, 0x4
|
||||
1c: 0000 nop!
|
||||
1e: 0000 nop!
|
||||
20: 6015 bitset! r0, 0x2
|
||||
22: 6015 bitset! r0, 0x2
|
||||
24: 6f25 bitset! r15, 0x4
|
||||
26: 6f25 bitset! r15, 0x4
|
||||
28: 6f0d bitset! r15, 0x1
|
||||
2a: 6f0d bitset! r15, 0x1
|
||||
2c: 6f1d bitset! r15, 0x3
|
||||
2e: 6f1d bitset! r15, 0x3
|
||||
30: 681d bitset! r8, 0x3
|
||||
32: 681d bitset! r8, 0x3
|
||||
34: 81ef842b bitset.c r15, r15, 0x1
|
||||
38: 8357902b bitset.c r26, r23, 0x4
|
||||
3c: 0000 nop!
|
||||
3e: 0000 nop!
|
||||
40: 6017 bittgl! r0, 0x2
|
||||
42: 6017 bittgl! r0, 0x2
|
||||
44: 6f27 bittgl! r15, 0x4
|
||||
46: 6f27 bittgl! r15, 0x4
|
||||
48: 6f0f bittgl! r15, 0x1
|
||||
4a: 6f0f bittgl! r15, 0x1
|
||||
4c: 6f1f bittgl! r15, 0x3
|
||||
4e: 6f1f bittgl! r15, 0x3
|
||||
50: 681f bittgl! r8, 0x3
|
||||
52: 681f bittgl! r8, 0x3
|
||||
54: 81ef842f bittgl.c r15, r15, 0x1
|
||||
58: 8357902f bittgl.c r26, r23, 0x4
|
||||
5c: 0000 nop!
|
||||
5e: 0000 nop!
|
||||
60: 6011 slli! r0, 2
|
||||
62: 6011 slli! r0, 2
|
||||
64: 6f21 slli! r15, 4
|
||||
66: 6f21 slli! r15, 4
|
||||
68: 6f09 slli! r15, 1
|
||||
6a: 6f09 slli! r15, 1
|
||||
6c: 6f19 slli! r15, 3
|
||||
6e: 6f19 slli! r15, 3
|
||||
70: 6819 slli! r8, 3
|
||||
72: 6819 slli! r8, 3
|
||||
74: 81ef8471 slli.c r15, r15, 1
|
||||
78: 83579071 slli.c r26, r23, 4
|
||||
7c: 0000 nop!
|
||||
7e: 0000 nop!
|
||||
80: 6013 srli! r0, 2
|
||||
82: 6013 srli! r0, 2
|
||||
84: 6f23 srli! r15, 4
|
||||
86: 6f23 srli! r15, 4
|
||||
88: 6f0b srli! r15, 1
|
||||
8a: 6f0b srli! r15, 1
|
||||
8c: 6f1b srli! r15, 3
|
||||
8e: 6f1b srli! r15, 3
|
||||
90: 681b srli! r8, 3
|
||||
92: 681b srli! r8, 3
|
||||
94: 81ef8475 srli.c r15, r15, 1
|
||||
98: 83579075 srli.c r26, r23, 4
|
||||
9c: 0000 nop!
|
||||
9e: 0000 nop!
|
||||
a0: 80008829 bitclr.c r0, r0, 0x2
|
||||
a4: 82958829 bitclr.c r20, r21, 0x2
|
||||
a8: 81ef9029 bitclr.c r15, r15, 0x4
|
||||
ac: 83359029 bitclr.c r25, r21, 0x4
|
||||
b0: 81ef8429 bitclr.c r15, r15, 0x1
|
||||
b4: 83368429 bitclr.c r25, r22, 0x1
|
||||
b8: 681c bitclr! r8, 0x3
|
||||
ba: 681c bitclr! r8, 0x3
|
||||
bc: 6624 bitclr! r6, 0x4
|
||||
be: 6624 bitclr! r6, 0x4
|
||||
c0: 6914 bitclr! r9, 0x2
|
||||
c2: 6914 bitclr! r9, 0x2
|
||||
...
|
||||
d0: 8000882b bitset.c r0, r0, 0x2
|
||||
d4: 8295882b bitset.c r20, r21, 0x2
|
||||
d8: 81ef902b bitset.c r15, r15, 0x4
|
||||
dc: 8335902b bitset.c r25, r21, 0x4
|
||||
e0: 81ef842b bitset.c r15, r15, 0x1
|
||||
e4: 8336842b bitset.c r25, r22, 0x1
|
||||
e8: 681d bitset! r8, 0x3
|
||||
ea: 681d bitset! r8, 0x3
|
||||
ec: 6625 bitset! r6, 0x4
|
||||
ee: 6625 bitset! r6, 0x4
|
||||
f0: 6915 bitset! r9, 0x2
|
||||
f2: 6915 bitset! r9, 0x2
|
||||
...
|
||||
100: 8000882f bittgl.c r0, r0, 0x2
|
||||
104: 8295882f bittgl.c r20, r21, 0x2
|
||||
108: 81ef902f bittgl.c r15, r15, 0x4
|
||||
10c: 8335902f bittgl.c r25, r21, 0x4
|
||||
110: 81ef842f bittgl.c r15, r15, 0x1
|
||||
114: 8336842f bittgl.c r25, r22, 0x1
|
||||
118: 681f bittgl! r8, 0x3
|
||||
11a: 681f bittgl! r8, 0x3
|
||||
11c: 6627 bittgl! r6, 0x4
|
||||
11e: 6627 bittgl! r6, 0x4
|
||||
120: 6917 bittgl! r9, 0x2
|
||||
122: 6917 bittgl! r9, 0x2
|
||||
...
|
||||
130: 80008871 slli.c r0, r0, 2
|
||||
134: 82958871 slli.c r20, r21, 2
|
||||
138: 81ef9071 slli.c r15, r15, 4
|
||||
13c: 83359071 slli.c r25, r21, 4
|
||||
140: 81ef8471 slli.c r15, r15, 1
|
||||
144: 83368471 slli.c r25, r22, 1
|
||||
148: 6819 slli! r8, 3
|
||||
14a: 6819 slli! r8, 3
|
||||
14c: 6621 slli! r6, 4
|
||||
14e: 6621 slli! r6, 4
|
||||
150: 6911 slli! r9, 2
|
||||
152: 6911 slli! r9, 2
|
||||
...
|
||||
160: 80008875 srli.c r0, r0, 2
|
||||
164: 82958875 srli.c r20, r21, 2
|
||||
168: 81ef9075 srli.c r15, r15, 4
|
||||
16c: 83359075 srli.c r25, r21, 4
|
||||
170: 81ef8475 srli.c r15, r15, 1
|
||||
174: 83368475 srli.c r25, r22, 1
|
||||
178: 681b srli! r8, 3
|
||||
17a: 681b srli! r8, 3
|
||||
17c: 6623 srli! r6, 4
|
||||
17e: 6623 srli! r6, 4
|
||||
180: 6913 srli! r9, 2
|
||||
182: 6913 srli! r9, 2
|
||||
#pass
|
|
@ -0,0 +1,73 @@
|
|||
/*
|
||||
* test relax
|
||||
* bitclr.c <-> bitclr! : register number must be in 0-15
|
||||
* bitset.c <-> bitset! : register number must be in 0-15
|
||||
* bittgl.c <-> bittgl! : register number must be in 0-15
|
||||
* slli.c <-> slli! : register number must be in 0-15
|
||||
* srli.c <-> srli! : register number must be in 0-15
|
||||
|
||||
* Author: ligang
|
||||
*/
|
||||
|
||||
/* This macro transform 32b instruction to 16b. */
|
||||
.macro tran3216 insn32, insn16
|
||||
.align 4
|
||||
|
||||
\insn32 r0, r0, 2 #32b -> 16b
|
||||
\insn16 r0, 2
|
||||
|
||||
\insn32 r15, r15, 4 #32b -> 16b
|
||||
\insn16 r15, 4
|
||||
|
||||
\insn32 r15, r15, 1 #32b -> 16b
|
||||
\insn16 r15, 1
|
||||
|
||||
\insn16 r15, 3
|
||||
\insn32 r15, r15, 3 #32b -> 16b
|
||||
|
||||
\insn32 r8, r8, 3 #32b -> 16b
|
||||
\insn32 r8, r8, 3 #32b -> 16b
|
||||
|
||||
\insn32 r15, r15, 1 #No transform
|
||||
\insn32 r26, r23, 4
|
||||
|
||||
.endm
|
||||
|
||||
/* This macro transform 16b instruction to 32b. */
|
||||
.macro tran1632 insn32, insn16
|
||||
.align 4
|
||||
|
||||
\insn16 r0, 2 #16b -> 32b
|
||||
\insn32 r20, r21, 2
|
||||
|
||||
\insn16 r15, 4 #16b -> 32b
|
||||
\insn32 r25, r21, 4
|
||||
|
||||
\insn16 r15, 1 #16b -> 32b
|
||||
\insn32 r25, r22, 1
|
||||
|
||||
\insn16 r8, 3 #No transform
|
||||
\insn16 r8, 3 #No transform
|
||||
|
||||
\insn16 r6, 4 #No transform
|
||||
\insn32 r6, r6, 4 #32b -> 16b
|
||||
|
||||
\insn32 r9, r9, 2 #32b -> 16b
|
||||
\insn16 r9, 2 #No transform
|
||||
|
||||
.endm
|
||||
|
||||
.text
|
||||
|
||||
tran3216 "bitclr.c", "bitclr!"
|
||||
tran3216 "bitset.c", "bitset!"
|
||||
tran3216 "bittgl.c", "bittgl!"
|
||||
tran3216 "slli.c", "slli!"
|
||||
tran3216 "srli.c", "srli!"
|
||||
|
||||
tran1632 "bitclr.c", "bitclr!"
|
||||
tran1632 "bitset.c", "bitset!"
|
||||
tran1632 "bittgl.c", "bittgl!"
|
||||
tran1632 "slli.c", "slli!"
|
||||
tran1632 "srli.c", "srli!"
|
||||
|
|
@ -0,0 +1,252 @@
|
|||
#as:
|
||||
#objdump: -d
|
||||
#source: rD_rA_rB.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: 2020 add! r0, r2
|
||||
2: 2020 add! r0, r2
|
||||
4: 2540 add! r5, r4
|
||||
6: 2540 add! r5, r4
|
||||
8: 2f40 add! r15, r4
|
||||
a: 2f40 add! r15, r4
|
||||
c: 2f30 add! r15, r3
|
||||
e: 2f30 add! r15, r3
|
||||
10: 2830 add! r8, r3
|
||||
12: 2830 add! r8, r3
|
||||
14: 81ef9811 add.c r15, r15, r6
|
||||
18: 83579011 add.c r26, r23, r4
|
||||
1c: 0000 nop!
|
||||
1e: 0000 nop!
|
||||
20: 0029 addc! r0, r2
|
||||
22: 0029 addc! r0, r2
|
||||
24: 0549 addc! r5, r4
|
||||
26: 0549 addc! r5, r4
|
||||
28: 0f49 addc! r15, r4
|
||||
2a: 0f49 addc! r15, r4
|
||||
2c: 0f39 addc! r15, r3
|
||||
2e: 0f39 addc! r15, r3
|
||||
30: 0839 addc! r8, r3
|
||||
32: 0839 addc! r8, r3
|
||||
34: 81ef9813 addc.c r15, r15, r6
|
||||
38: 83579013 addc.c r26, r23, r4
|
||||
3c: 0000 nop!
|
||||
3e: 0000 nop!
|
||||
40: 2021 sub! r0, r2
|
||||
42: 2021 sub! r0, r2
|
||||
44: 2541 sub! r5, r4
|
||||
46: 2541 sub! r5, r4
|
||||
48: 2f41 sub! r15, r4
|
||||
4a: 2f41 sub! r15, r4
|
||||
4c: 2f31 sub! r15, r3
|
||||
4e: 2f31 sub! r15, r3
|
||||
50: 2831 sub! r8, r3
|
||||
52: 2831 sub! r8, r3
|
||||
54: 81ef9815 sub.c r15, r15, r6
|
||||
58: 83579015 sub.c r26, r23, r4
|
||||
5c: 0000 nop!
|
||||
5e: 0000 nop!
|
||||
60: 2024 and! r0, r2
|
||||
62: 2024 and! r0, r2
|
||||
64: 2544 and! r5, r4
|
||||
66: 2544 and! r5, r4
|
||||
68: 2f44 and! r15, r4
|
||||
6a: 2f44 and! r15, r4
|
||||
6c: 2f34 and! r15, r3
|
||||
6e: 2f34 and! r15, r3
|
||||
70: 2834 and! r8, r3
|
||||
72: 2834 and! r8, r3
|
||||
74: 81ef9821 and.c r15, r15, r6
|
||||
78: 83579021 and.c r26, r23, r4
|
||||
7c: 0000 nop!
|
||||
7e: 0000 nop!
|
||||
80: 2025 or! r0, r2
|
||||
82: 2025 or! r0, r2
|
||||
84: 2545 or! r5, r4
|
||||
86: 2545 or! r5, r4
|
||||
88: 2f45 or! r15, r4
|
||||
8a: 2f45 or! r15, r4
|
||||
8c: 2f35 or! r15, r3
|
||||
8e: 2f35 or! r15, r3
|
||||
90: 2835 or! r8, r3
|
||||
92: 2835 or! r8, r3
|
||||
94: 81ef9823 or.c r15, r15, r6
|
||||
98: 83579023 or.c r26, r23, r4
|
||||
9c: 0000 nop!
|
||||
9e: 0000 nop!
|
||||
a0: 2027 xor! r0, r2
|
||||
a2: 2027 xor! r0, r2
|
||||
a4: 2547 xor! r5, r4
|
||||
a6: 2547 xor! r5, r4
|
||||
a8: 2f47 xor! r15, r4
|
||||
aa: 2f47 xor! r15, r4
|
||||
ac: 2f37 xor! r15, r3
|
||||
ae: 2f37 xor! r15, r3
|
||||
b0: 2837 xor! r8, r3
|
||||
b2: 2837 xor! r8, r3
|
||||
b4: 81ef9827 xor.c r15, r15, r6
|
||||
b8: 83579027 xor.c r26, r23, r4
|
||||
bc: 0000 nop!
|
||||
be: 0000 nop!
|
||||
c0: 002b sra! r0, r2
|
||||
c2: 002b sra! r0, r2
|
||||
c4: 054b sra! r5, r4
|
||||
c6: 054b sra! r5, r4
|
||||
c8: 0f4b sra! r15, r4
|
||||
ca: 0f4b sra! r15, r4
|
||||
cc: 0f3b sra! r15, r3
|
||||
ce: 0f3b sra! r15, r3
|
||||
d0: 083b sra! r8, r3
|
||||
d2: 083b sra! r8, r3
|
||||
d4: 81ef9837 sra.c r15, r15, r6
|
||||
d8: 83579037 sra.c r26, r23, r4
|
||||
dc: 0000 nop!
|
||||
de: 0000 nop!
|
||||
e0: 002a srl! r0, r2
|
||||
e2: 002a srl! r0, r2
|
||||
e4: 054a srl! r5, r4
|
||||
e6: 054a srl! r5, r4
|
||||
e8: 0f4a srl! r15, r4
|
||||
ea: 0f4a srl! r15, r4
|
||||
ec: 0f3a srl! r15, r3
|
||||
ee: 0f3a srl! r15, r3
|
||||
f0: 083a srl! r8, r3
|
||||
f2: 083a srl! r8, r3
|
||||
f4: 81ef9835 srl.c r15, r15, r6
|
||||
f8: 83579035 srl.c r26, r23, r4
|
||||
fc: 0000 nop!
|
||||
fe: 0000 nop!
|
||||
100: 0028 sll! r0, r2
|
||||
102: 0028 sll! r0, r2
|
||||
104: 0548 sll! r5, r4
|
||||
106: 0548 sll! r5, r4
|
||||
108: 0f48 sll! r15, r4
|
||||
10a: 0f48 sll! r15, r4
|
||||
10c: 0f38 sll! r15, r3
|
||||
10e: 0f38 sll! r15, r3
|
||||
110: 0838 sll! r8, r3
|
||||
112: 0838 sll! r8, r3
|
||||
114: 81ef9831 sll.c r15, r15, r6
|
||||
118: 83579031 sll.c r26, r23, r4
|
||||
11c: 0000 nop!
|
||||
11e: 0000 nop!
|
||||
120: 80008811 add.c r0, r0, r2
|
||||
124: 82958811 add.c r20, r21, r2
|
||||
128: 81ef9011 add.c r15, r15, r4
|
||||
12c: 83359011 add.c r25, r21, r4
|
||||
130: 81ef8c11 add.c r15, r15, r3
|
||||
134: 83368c11 add.c r25, r22, r3
|
||||
138: 2870 add! r8, r7
|
||||
13a: 2870 add! r8, r7
|
||||
13c: 2640 add! r6, r4
|
||||
13e: 2640 add! r6, r4
|
||||
140: 2740 add! r7, r4
|
||||
142: 2740 add! r7, r4
|
||||
...
|
||||
150: 80008813 addc.c r0, r0, r2
|
||||
154: 82958813 addc.c r20, r21, r2
|
||||
158: 81ef9013 addc.c r15, r15, r4
|
||||
15c: 83359013 addc.c r25, r21, r4
|
||||
160: 81ef8c13 addc.c r15, r15, r3
|
||||
164: 83368c13 addc.c r25, r22, r3
|
||||
168: 0879 addc! r8, r7
|
||||
16a: 0879 addc! r8, r7
|
||||
16c: 0649 addc! r6, r4
|
||||
16e: 0649 addc! r6, r4
|
||||
170: 0749 addc! r7, r4
|
||||
172: 0749 addc! r7, r4
|
||||
...
|
||||
180: 80008815 sub.c r0, r0, r2
|
||||
184: 82958815 sub.c r20, r21, r2
|
||||
188: 81ef9015 sub.c r15, r15, r4
|
||||
18c: 83359015 sub.c r25, r21, r4
|
||||
190: 81ef8c15 sub.c r15, r15, r3
|
||||
194: 83368c15 sub.c r25, r22, r3
|
||||
198: 2871 sub! r8, r7
|
||||
19a: 2871 sub! r8, r7
|
||||
19c: 2641 sub! r6, r4
|
||||
19e: 2641 sub! r6, r4
|
||||
1a0: 2741 sub! r7, r4
|
||||
1a2: 2741 sub! r7, r4
|
||||
...
|
||||
1b0: 80008821 and.c r0, r0, r2
|
||||
1b4: 82958821 and.c r20, r21, r2
|
||||
1b8: 81ef9021 and.c r15, r15, r4
|
||||
1bc: 83359021 and.c r25, r21, r4
|
||||
1c0: 81ef8c21 and.c r15, r15, r3
|
||||
1c4: 83368c21 and.c r25, r22, r3
|
||||
1c8: 2874 and! r8, r7
|
||||
1ca: 2874 and! r8, r7
|
||||
1cc: 2644 and! r6, r4
|
||||
1ce: 2644 and! r6, r4
|
||||
1d0: 2744 and! r7, r4
|
||||
1d2: 2744 and! r7, r4
|
||||
...
|
||||
1e0: 80008823 or.c r0, r0, r2
|
||||
1e4: 82958823 or.c r20, r21, r2
|
||||
1e8: 81ef9023 or.c r15, r15, r4
|
||||
1ec: 83359023 or.c r25, r21, r4
|
||||
1f0: 81ef8c23 or.c r15, r15, r3
|
||||
1f4: 83368c23 or.c r25, r22, r3
|
||||
1f8: 2875 or! r8, r7
|
||||
1fa: 2875 or! r8, r7
|
||||
1fc: 2645 or! r6, r4
|
||||
1fe: 2645 or! r6, r4
|
||||
200: 2745 or! r7, r4
|
||||
202: 2745 or! r7, r4
|
||||
...
|
||||
210: 80008827 xor.c r0, r0, r2
|
||||
214: 82958827 xor.c r20, r21, r2
|
||||
218: 81ef9027 xor.c r15, r15, r4
|
||||
21c: 83359027 xor.c r25, r21, r4
|
||||
220: 81ef8c27 xor.c r15, r15, r3
|
||||
224: 83368c27 xor.c r25, r22, r3
|
||||
228: 2877 xor! r8, r7
|
||||
22a: 2877 xor! r8, r7
|
||||
22c: 2647 xor! r6, r4
|
||||
22e: 2647 xor! r6, r4
|
||||
230: 2747 xor! r7, r4
|
||||
232: 2747 xor! r7, r4
|
||||
...
|
||||
240: 80008837 sra.c r0, r0, r2
|
||||
244: 82958837 sra.c r20, r21, r2
|
||||
248: 81ef9037 sra.c r15, r15, r4
|
||||
24c: 83359037 sra.c r25, r21, r4
|
||||
250: 81ef8c37 sra.c r15, r15, r3
|
||||
254: 83368c37 sra.c r25, r22, r3
|
||||
258: 087b sra! r8, r7
|
||||
25a: 087b sra! r8, r7
|
||||
25c: 064b sra! r6, r4
|
||||
25e: 064b sra! r6, r4
|
||||
260: 074b sra! r7, r4
|
||||
262: 074b sra! r7, r4
|
||||
...
|
||||
270: 80008835 srl.c r0, r0, r2
|
||||
274: 82958835 srl.c r20, r21, r2
|
||||
278: 81ef9035 srl.c r15, r15, r4
|
||||
27c: 83359035 srl.c r25, r21, r4
|
||||
280: 81ef8c35 srl.c r15, r15, r3
|
||||
284: 83368c35 srl.c r25, r22, r3
|
||||
288: 087a srl! r8, r7
|
||||
28a: 087a srl! r8, r7
|
||||
28c: 064a srl! r6, r4
|
||||
28e: 064a srl! r6, r4
|
||||
290: 074a srl! r7, r4
|
||||
292: 074a srl! r7, r4
|
||||
...
|
||||
2a0: 80008831 sll.c r0, r0, r2
|
||||
2a4: 82958831 sll.c r20, r21, r2
|
||||
2a8: 81ef9031 sll.c r15, r15, r4
|
||||
2ac: 83359031 sll.c r25, r21, r4
|
||||
2b0: 81ef8c31 sll.c r15, r15, r3
|
||||
2b4: 83368c31 sll.c r25, r22, r3
|
||||
2b8: 0878 sll! r8, r7
|
||||
2ba: 0878 sll! r8, r7
|
||||
2bc: 0648 sll! r6, r4
|
||||
2be: 0648 sll! r6, r4
|
||||
2c0: 0748 sll! r7, r4
|
||||
2c2: 0748 sll! r7, r4
|
||||
#pass
|
|
@ -0,0 +1,86 @@
|
|||
/*
|
||||
* test relax
|
||||
* add.c <-> add! : register number must be in 0-15
|
||||
* addc.c <-> addc! : register number must be in 0-15
|
||||
* sub.c <-> sub! : register number must be in 0-15
|
||||
* and.c <-> and! : register number must be in 0-15
|
||||
* or.c <-> or! : register number must be in 0-15
|
||||
* xor.c <-> xor! : register number must be in 0-15
|
||||
* sra.c <-> sra! : register number must be in 0-15
|
||||
* srl.c <-> srl! : register number must be in 0-15
|
||||
* sll.c <-> sll! : register number must be in 0-15
|
||||
|
||||
* Author: ligang
|
||||
*/
|
||||
|
||||
|
||||
/* This macro transform 32b instruction to 16b. */
|
||||
.macro tran3216 insn32, insn16
|
||||
.align 4
|
||||
|
||||
\insn32 r0, r0, r2 #32b -> 16b
|
||||
\insn16 r0, r2
|
||||
|
||||
\insn32 r5, r5, r4 #32b -> 16b
|
||||
\insn16 r5, r4
|
||||
|
||||
\insn32 r15, r15, r4 #32b -> 16b
|
||||
\insn16 r15, r4
|
||||
|
||||
\insn16 r15, r3
|
||||
\insn32 r15, r15, r3 #32b -> 16b
|
||||
|
||||
\insn32 r8, r8, r3 #32b -> 16b
|
||||
\insn32 r8, r8, r3 #32b -> 16b
|
||||
|
||||
\insn32 r15, r15, r6 #No transform
|
||||
\insn32 r26, r23, r4
|
||||
|
||||
.endm
|
||||
|
||||
/* This macro transform 16b instruction to 32b. */
|
||||
.macro tran1632 insn32, insn16
|
||||
.align 4
|
||||
|
||||
\insn16 r0, r2 #16b -> 32b
|
||||
\insn32 r20, r21, r2
|
||||
|
||||
\insn16 r15, r4 #16b -> 32b
|
||||
\insn32 r25, r21, r4
|
||||
|
||||
\insn16 r15, r3 #16b -> 32b
|
||||
\insn32 r25, r22, r3
|
||||
|
||||
\insn16 r8, r7 #No transform
|
||||
\insn16 r8, r7 #No transform
|
||||
|
||||
\insn16 r6, r4 #No transform
|
||||
\insn32 r6, r6, r4
|
||||
|
||||
\insn32 r7, r7, r4 #32b -> 16b
|
||||
\insn16 r7, r4 #No transform
|
||||
|
||||
.endm
|
||||
|
||||
.text
|
||||
|
||||
tran3216 "add.c", "add!"
|
||||
tran3216 "addc.c", "addc!"
|
||||
tran3216 "sub.c", "sub!"
|
||||
tran3216 "and.c", "and!"
|
||||
tran3216 "or.c", "or!"
|
||||
tran3216 "xor.c", "xor!"
|
||||
tran3216 "sra.c", "sra!"
|
||||
tran3216 "srl.c", "srl!"
|
||||
tran3216 "sll.c", "sll!"
|
||||
|
||||
tran1632 "add.c", "add!"
|
||||
tran1632 "addc.c", "addc!"
|
||||
tran1632 "sub.c", "sub!"
|
||||
tran1632 "and.c", "and!"
|
||||
tran1632 "or.c", "or!"
|
||||
tran1632 "xor.c", "xor!"
|
||||
tran1632 "sra.c", "sra!"
|
||||
tran1632 "srl.c", "srl!"
|
||||
tran1632 "sll.c", "sll!"
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
# test relax
|
||||
|
||||
if [istarget score-*-*] then {
|
||||
run_dump_test "ldi"
|
||||
run_dump_test "nop"
|
||||
run_dump_test "tcond"
|
||||
run_dump_test "ls32ls16"
|
||||
run_dump_test "ls32ls16p"
|
||||
run_dump_test "postlw"
|
||||
run_dump_test "presw"
|
||||
run_dump_test "rD_rA_rB"
|
||||
run_dump_test "bittst"
|
||||
run_dump_test "addi"
|
||||
run_dump_test "br"
|
||||
run_dump_test "b"
|
||||
run_dump_test "move"
|
||||
run_dump_test "rD_rA_BN"
|
||||
run_dump_test "rD_rA"
|
||||
}
|
||||
|
|
@ -0,0 +1,264 @@
|
|||
#as:
|
||||
#objdump: -d
|
||||
#source: tcond.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: 0f05 tset!
|
||||
2: 0f05 tset!
|
||||
4: 0f05 tset!
|
||||
6: 0f05 tset!
|
||||
8: 0f05 tset!
|
||||
a: 0f05 tset!
|
||||
c: 8000bc54 tset
|
||||
10: 8254e010 add r18, r20, r24
|
||||
...
|
||||
20: 0f05 tset!
|
||||
22: 0f05 tset!
|
||||
24: 0f05 tset!
|
||||
26: 0f05 tset!
|
||||
28: 8000bc54 tset
|
||||
2c: 8254e026 xor r18, r20, r24
|
||||
30: 0005 tcs!
|
||||
32: 0005 tcs!
|
||||
34: 0005 tcs!
|
||||
36: 0005 tcs!
|
||||
38: 0005 tcs!
|
||||
3a: 0005 tcs!
|
||||
3c: 80008054 tcs
|
||||
40: 8254e010 add r18, r20, r24
|
||||
...
|
||||
50: 0005 tcs!
|
||||
52: 0005 tcs!
|
||||
54: 0005 tcs!
|
||||
56: 0005 tcs!
|
||||
58: 80008054 tcs
|
||||
5c: 8254e026 xor r18, r20, r24
|
||||
60: 0105 tcc!
|
||||
62: 0105 tcc!
|
||||
64: 0105 tcc!
|
||||
66: 0105 tcc!
|
||||
68: 0105 tcc!
|
||||
6a: 0105 tcc!
|
||||
6c: 80008454 tcc
|
||||
70: 8254e010 add r18, r20, r24
|
||||
...
|
||||
80: 0105 tcc!
|
||||
82: 0105 tcc!
|
||||
84: 0105 tcc!
|
||||
86: 0105 tcc!
|
||||
88: 80008454 tcc
|
||||
8c: 8254e026 xor r18, r20, r24
|
||||
90: 0205 tgtu!
|
||||
92: 0205 tgtu!
|
||||
94: 0205 tgtu!
|
||||
96: 0205 tgtu!
|
||||
98: 0205 tgtu!
|
||||
9a: 0205 tgtu!
|
||||
9c: 80008854 tgtu
|
||||
a0: 8254e010 add r18, r20, r24
|
||||
...
|
||||
b0: 0205 tgtu!
|
||||
b2: 0205 tgtu!
|
||||
b4: 0205 tgtu!
|
||||
b6: 0205 tgtu!
|
||||
b8: 80008854 tgtu
|
||||
bc: 8254e026 xor r18, r20, r24
|
||||
c0: 0305 tleu!
|
||||
c2: 0305 tleu!
|
||||
c4: 0305 tleu!
|
||||
c6: 0305 tleu!
|
||||
c8: 0305 tleu!
|
||||
ca: 0305 tleu!
|
||||
cc: 80008c54 tleu
|
||||
d0: 8254e010 add r18, r20, r24
|
||||
...
|
||||
e0: 0305 tleu!
|
||||
e2: 0305 tleu!
|
||||
e4: 0305 tleu!
|
||||
e6: 0305 tleu!
|
||||
e8: 80008c54 tleu
|
||||
ec: 8254e026 xor r18, r20, r24
|
||||
f0: 0405 teq!
|
||||
f2: 0405 teq!
|
||||
f4: 0405 teq!
|
||||
f6: 0405 teq!
|
||||
f8: 0405 teq!
|
||||
fa: 0405 teq!
|
||||
fc: 80009054 teq
|
||||
100: 8254e010 add r18, r20, r24
|
||||
...
|
||||
110: 0405 teq!
|
||||
112: 0405 teq!
|
||||
114: 0405 teq!
|
||||
116: 0405 teq!
|
||||
118: 80009054 teq
|
||||
11c: 8254e026 xor r18, r20, r24
|
||||
120: 0505 tne!
|
||||
122: 0505 tne!
|
||||
124: 0505 tne!
|
||||
126: 0505 tne!
|
||||
128: 0505 tne!
|
||||
12a: 0505 tne!
|
||||
12c: 80009454 tne
|
||||
130: 8254e010 add r18, r20, r24
|
||||
...
|
||||
140: 0505 tne!
|
||||
142: 0505 tne!
|
||||
144: 0505 tne!
|
||||
146: 0505 tne!
|
||||
148: 80009454 tne
|
||||
14c: 8254e026 xor r18, r20, r24
|
||||
150: 0605 tgt!
|
||||
152: 0605 tgt!
|
||||
154: 0605 tgt!
|
||||
156: 0605 tgt!
|
||||
158: 0605 tgt!
|
||||
15a: 0605 tgt!
|
||||
15c: 80009854 tgt
|
||||
160: 8254e010 add r18, r20, r24
|
||||
...
|
||||
170: 0605 tgt!
|
||||
172: 0605 tgt!
|
||||
174: 0605 tgt!
|
||||
176: 0605 tgt!
|
||||
178: 80009854 tgt
|
||||
17c: 8254e026 xor r18, r20, r24
|
||||
180: 0705 tle!
|
||||
182: 0705 tle!
|
||||
184: 0705 tle!
|
||||
186: 0705 tle!
|
||||
188: 0705 tle!
|
||||
18a: 0705 tle!
|
||||
18c: 80009c54 tle
|
||||
190: 8254e010 add r18, r20, r24
|
||||
...
|
||||
1a0: 0705 tle!
|
||||
1a2: 0705 tle!
|
||||
1a4: 0705 tle!
|
||||
1a6: 0705 tle!
|
||||
1a8: 80009c54 tle
|
||||
1ac: 8254e026 xor r18, r20, r24
|
||||
1b0: 0805 tge!
|
||||
1b2: 0805 tge!
|
||||
1b4: 0805 tge!
|
||||
1b6: 0805 tge!
|
||||
1b8: 0805 tge!
|
||||
1ba: 0805 tge!
|
||||
1bc: 8000a054 tge
|
||||
1c0: 8254e010 add r18, r20, r24
|
||||
...
|
||||
1d0: 0805 tge!
|
||||
1d2: 0805 tge!
|
||||
1d4: 0805 tge!
|
||||
1d6: 0805 tge!
|
||||
1d8: 8000a054 tge
|
||||
1dc: 8254e026 xor r18, r20, r24
|
||||
1e0: 0905 tlt!
|
||||
1e2: 0905 tlt!
|
||||
1e4: 0905 tlt!
|
||||
1e6: 0905 tlt!
|
||||
1e8: 0905 tlt!
|
||||
1ea: 0905 tlt!
|
||||
1ec: 8000a454 tlt
|
||||
1f0: 8254e010 add r18, r20, r24
|
||||
...
|
||||
200: 0905 tlt!
|
||||
202: 0905 tlt!
|
||||
204: 0905 tlt!
|
||||
206: 0905 tlt!
|
||||
208: 8000a454 tlt
|
||||
20c: 8254e026 xor r18, r20, r24
|
||||
210: 0a05 tmi!
|
||||
212: 0a05 tmi!
|
||||
214: 0a05 tmi!
|
||||
216: 0a05 tmi!
|
||||
218: 0a05 tmi!
|
||||
21a: 0a05 tmi!
|
||||
21c: 8000a854 tmi
|
||||
220: 8254e010 add r18, r20, r24
|
||||
...
|
||||
230: 0a05 tmi!
|
||||
232: 0a05 tmi!
|
||||
234: 0a05 tmi!
|
||||
236: 0a05 tmi!
|
||||
238: 8000a854 tmi
|
||||
23c: 8254e026 xor r18, r20, r24
|
||||
240: 0b05 tpl!
|
||||
242: 0b05 tpl!
|
||||
244: 0b05 tpl!
|
||||
246: 0b05 tpl!
|
||||
248: 0b05 tpl!
|
||||
24a: 0b05 tpl!
|
||||
24c: 8000ac54 tpl
|
||||
250: 8254e010 add r18, r20, r24
|
||||
...
|
||||
260: 0b05 tpl!
|
||||
262: 0b05 tpl!
|
||||
264: 0b05 tpl!
|
||||
266: 0b05 tpl!
|
||||
268: 8000ac54 tpl
|
||||
26c: 8254e026 xor r18, r20, r24
|
||||
270: 0c05 tvs!
|
||||
272: 0c05 tvs!
|
||||
274: 0c05 tvs!
|
||||
276: 0c05 tvs!
|
||||
278: 0c05 tvs!
|
||||
27a: 0c05 tvs!
|
||||
27c: 8000b054 tvs
|
||||
280: 8254e010 add r18, r20, r24
|
||||
...
|
||||
290: 0c05 tvs!
|
||||
292: 0c05 tvs!
|
||||
294: 0c05 tvs!
|
||||
296: 0c05 tvs!
|
||||
298: 8000b054 tvs
|
||||
29c: 8254e026 xor r18, r20, r24
|
||||
2a0: 0d05 tvc!
|
||||
2a2: 0d05 tvc!
|
||||
2a4: 0d05 tvc!
|
||||
2a6: 0d05 tvc!
|
||||
2a8: 0d05 tvc!
|
||||
2aa: 0d05 tvc!
|
||||
2ac: 8000b454 tvc
|
||||
2b0: 8254e010 add r18, r20, r24
|
||||
...
|
||||
2c0: 0d05 tvc!
|
||||
2c2: 0d05 tvc!
|
||||
2c4: 0d05 tvc!
|
||||
2c6: 0d05 tvc!
|
||||
2c8: 8000b454 tvc
|
||||
2cc: 8254e026 xor r18, r20, r24
|
||||
2d0: 0e05 tcnz!
|
||||
2d2: 0e05 tcnz!
|
||||
2d4: 0e05 tcnz!
|
||||
2d6: 0e05 tcnz!
|
||||
2d8: 0e05 tcnz!
|
||||
2da: 0e05 tcnz!
|
||||
2dc: 8000b854 tcnz
|
||||
2e0: 8254e010 add r18, r20, r24
|
||||
...
|
||||
2f0: 0e05 tcnz!
|
||||
2f2: 0e05 tcnz!
|
||||
2f4: 0e05 tcnz!
|
||||
2f6: 0e05 tcnz!
|
||||
2f8: 8000b854 tcnz
|
||||
2fc: 8254e026 xor r18, r20, r24
|
||||
300: 6062 sdbbp! 12
|
||||
302: 6062 sdbbp! 12
|
||||
304: 6062 sdbbp! 12
|
||||
306: 6062 sdbbp! 12
|
||||
308: 6062 sdbbp! 12
|
||||
30a: 6062 sdbbp! 12
|
||||
30c: 800c8006 sdbbp 12
|
||||
310: 8254e010 add r18, r20, r24
|
||||
...
|
||||
320: 6062 sdbbp! 12
|
||||
322: 6062 sdbbp! 12
|
||||
324: 6062 sdbbp! 12
|
||||
326: 6062 sdbbp! 12
|
||||
328: 800c8006 sdbbp 12
|
||||
32c: 8254e026 xor r18, r20, r24
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* test relax
|
||||
* Tcond <-> Tcond!
|
||||
* sdbbp <-> sdbbp!
|
||||
|
||||
* Author: ligang
|
||||
*/
|
||||
|
||||
.macro tran insn32, insn16
|
||||
/* This block transform 32b instruction to 16b. */
|
||||
.align 4
|
||||
|
||||
\insn32 #32b -> 16b
|
||||
\insn16
|
||||
|
||||
\insn32 #32b -> 16b
|
||||
\insn32 #32b -> 16b
|
||||
|
||||
\insn16
|
||||
\insn32 #32b -> 16b
|
||||
|
||||
\insn32 #No transform
|
||||
add r18, r20, r24
|
||||
|
||||
/* This block transform 16b instruction to 32b. */
|
||||
.align 4
|
||||
|
||||
\insn16 #No transform
|
||||
\insn32
|
||||
|
||||
\insn16 #No transform
|
||||
\insn16
|
||||
|
||||
\insn16 #16b -> 32b
|
||||
xor r18, r20, r24
|
||||
|
||||
.endm
|
||||
|
||||
tran "tset", "tset!"
|
||||
tran "tcs", "tcs!"
|
||||
tran "tcc", "tcc!"
|
||||
tran "tgtu", "tgtu!"
|
||||
tran "tleu", "tleu!"
|
||||
tran "teq", "teq!"
|
||||
tran "tne", "tne!"
|
||||
tran "tgt", "tgt!"
|
||||
tran "tle", "tle!"
|
||||
tran "tge", "tge!"
|
||||
tran "tlt", "tlt!"
|
||||
tran "tmi", "tmi!"
|
||||
tran "tpl", "tpl!"
|
||||
tran "tvs", "tvs!"
|
||||
tran "tvc", "tvc!"
|
||||
tran "tcnz", "tcnz!"
|
||||
tran "sdbbp 12", "sdbbp! 12"
|
Loading…
Reference in New Issue