2008-04-23 Maxim Grigoriev <maxim2405@gmail.com>
* Makefile.in (xtensa-tdep.o): Update dependencies. * configure.tgt (xtensa*): Update dependencies. * xtensa-tdep.c (arreg_number): Renamed from areg_number. Local variable areg renamed to arreg. (areg_number): New function. (xtensa_pseudo_register_read, xtensa_pseudo_register_write) (xtensa_extract_return_value, xtensa_store_return_value): areg_number replaced by arreg_number. (xtensa_windowed_frame_cache, struct xtensa_frame_cache): New comments. (xtensa_alloc_frame_cache): Initialize cache->wd.ws. (xtensa_scan_prologue): New function. (xtensa_frame_cache): New local fp_regnum. Handle separately the case, when ENTRY instraction hasn't been executed yet. Get the frame pointer value based on prologue analysis. Fix the bugs preventing WS and AR4-AR7/A11 registers from getting right values for intermediate frames, whose registers have been already spilled. (xtensa_frame_prev_register): Fix WS register value. Use are_number and arreg_number appropriately. (xtensa_gdbarch_init): Set solib_svr4_fetch_link_map_offsets to svr4_ilp32_fetch_link_map_offsets.
This commit is contained in:
Maxim Grigoriev
parent
fe4fa32c96
commit
ee967b5f61
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@ -1,3 +1,26 @@
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2008-04-23 Maxim Grigoriev <maxim2405@gmail.com>
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* Makefile.in (xtensa-tdep.o): Update dependencies.
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* configure.tgt (xtensa*): Update dependencies.
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* xtensa-tdep.c (arreg_number): Renamed from areg_number.
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Local variable areg renamed to arreg.
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(areg_number): New function.
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(xtensa_pseudo_register_read, xtensa_pseudo_register_write)
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(xtensa_extract_return_value, xtensa_store_return_value): areg_number
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replaced by arreg_number.
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(xtensa_windowed_frame_cache, struct xtensa_frame_cache): New comments.
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(xtensa_alloc_frame_cache): Initialize cache->wd.ws.
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(xtensa_scan_prologue): New function.
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(xtensa_frame_cache): New local fp_regnum. Handle separately the case,
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when ENTRY instraction hasn't been executed yet. Get the frame pointer
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value based on prologue analysis. Fix the bugs preventing WS and
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AR4-AR7/A11 registers from getting right values for intermediate frames,
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whose registers have been already spilled.
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(xtensa_frame_prev_register): Fix WS register value. Use are_number
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and arreg_number appropriately.
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(xtensa_gdbarch_init): Set solib_svr4_fetch_link_map_offsets to
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svr4_ilp32_fetch_link_map_offsets.
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2008-04-23 Andrew Stubbs <andrew.stubbs@st.com>
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* printcmd.c: Define USE_PRINTF_I64 and PRINTF_HAS_LONG_LONG on MinGW.
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@ -3016,7 +3016,7 @@ xtensa-tdep.o: xtensa-tdep.c $(defs_h) $(doublest_h) $(frame_h) \
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$(value_h) $(gdbcmd_h) $(gdbcore_h) $(dis_asm_h) $(symfile_h) \
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$(objfiles_h) $(gdb_string_h) $(linespec_h) $(regcache_h) \
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$(reggroups_h) $(arch_utils_h) $(osabi_h) $(block_h) $(gdb_assert_h) \
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$(elf_bfd_h) $(xtensa_tdep_h) $(dwarf2_frame_h)
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$(elf_bfd_h) $(xtensa_tdep_h) $(dwarf2_frame_h) $(solib_svr4_h)
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xtensa-config.o: $(defs_h) $(xtensa_tdep_h)
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#
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@ -523,7 +523,7 @@ xtensa*-*-linux*) gdb_target=linux
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;;
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xtensa*)
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# Target: Tensilica Xtensa processors
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gdb_target_obs="xtensa-tdep.o xtensa-config.o"
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gdb_target_obs="xtensa-tdep.o xtensa-config.o solib.o solib-svr4.o"
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;;
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esac
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@ -19,6 +19,7 @@
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#include "defs.h"
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#include "frame.h"
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#include "solib-svr4.h"
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#include "symtab.h"
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#include "symfile.h"
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#include "objfiles.h"
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@ -114,18 +115,33 @@ static int xtensa_debug_level = 0;
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#define PS_WOE (1<<18)
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#define PS_EXC (1<<4)
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/* Convert a live Ax register number to the corresponding Areg number. */
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/* Convert a live A-register number to the corresponding AR-register number. */
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static int
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areg_number (struct gdbarch *gdbarch, int regnum, ULONGEST wb)
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arreg_number (struct gdbarch *gdbarch, int a_regnum, ULONGEST wb)
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{
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struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
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int arreg;
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arreg = a_regnum - tdep->a0_base;
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arreg += (wb & ((tdep->num_aregs - 1) >> 2)) << WB_SHIFT;
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arreg &= tdep->num_aregs - 1;
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return arreg + tdep->ar_base;
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}
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/* Convert a live AR-register number to the corresponding A-register order
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number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
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static int
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areg_number (struct gdbarch *gdbarch, int ar_regnum, unsigned int wb)
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{
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struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
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int areg;
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areg = regnum - tdep->a0_base;
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areg += (wb & ((tdep->num_aregs - 1) >> 2)) << WB_SHIFT;
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areg &= tdep->num_aregs - 1;
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return areg + tdep->ar_base;
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areg = ar_regnum - tdep->ar_base;
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if (areg < 0 || areg >= tdep->num_aregs)
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return -1;
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areg = (areg - wb * 4) & (tdep->num_aregs - 1);
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return (areg > 15) ? -1 : areg;
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}
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static inline int
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@ -516,7 +532,8 @@ xtensa_pseudo_register_read (struct gdbarch *gdbarch,
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gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
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regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
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regnum = areg_number (gdbarch, regnum, extract_unsigned_integer (buf, 4));
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regnum = arreg_number (gdbarch, regnum,
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extract_unsigned_integer (buf, 4));
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}
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/* We can always read non-pseudo registers. */
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@ -613,7 +630,8 @@ xtensa_pseudo_register_write (struct gdbarch *gdbarch,
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regcache_raw_read (regcache,
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gdbarch_tdep (gdbarch)->wb_regnum, buf);
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regnum = areg_number (gdbarch, regnum, extract_unsigned_integer (buf, 4));
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regnum = arreg_number (gdbarch, regnum,
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extract_unsigned_integer (buf, 4));
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}
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/* We can always write 'core' registers.
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@ -880,9 +898,15 @@ xtensa_regset_from_core_section (struct gdbarch *core_arch,
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/* Frame cache part for Windowed ABI. */
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typedef struct xtensa_windowed_frame_cache
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{
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int wb; /* Base for this frame; -1 if not in regfile. */
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int callsize; /* Call size to next frame. */
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int ws;
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int wb; /* WINDOWBASE of the previous frame. */
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int callsize; /* Call size of this frame. */
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int ws; /* WINDOWSTART of the previous frame. It keeps track of
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life windows only. If there is no bit set for the
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window, that means it had been already spilled
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because of window overflow. */
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/* Spilled A-registers from the previous frame.
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AREGS[i] == -1, if corresponding AR is alive. */
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CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS];
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} xtensa_windowed_frame_cache_t;
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@ -932,11 +956,11 @@ typedef struct xtensa_call0_frame_cache
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typedef struct xtensa_frame_cache
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{
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CORE_ADDR base; /* Stack pointer of the next frame. */
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CORE_ADDR base; /* Stack pointer of this frame. */
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CORE_ADDR pc; /* PC at the entry point to the function. */
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CORE_ADDR ra; /* The raw return address. */
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CORE_ADDR ps; /* The PS register of the frame. */
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CORE_ADDR prev_sp; /* Stack Pointer of the frame. */
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CORE_ADDR ra; /* The raw return address (without CALLINC). */
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CORE_ADDR ps; /* The PS register of the previous frame. */
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CORE_ADDR prev_sp; /* Stack Pointer of the previous frame. */
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int call0; /* It's a call0 framework (else windowed). */
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union
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{
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@ -979,6 +1003,7 @@ xtensa_alloc_frame_cache (int windowed)
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else
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{
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cache->wd.wb = 0;
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cache->wd.ws = 0;
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cache->wd.callsize = -1;
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for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
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@ -1028,9 +1053,126 @@ xtensa_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
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return frame_id_build (fp + SP_ALIGNMENT, pc);
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}
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/* Returns the best guess about which register is a frame pointer
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for the function containing CURRENT_PC. */
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#define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
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static unsigned int
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xtensa_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR current_pc)
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{
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#define RETURN_FP goto done
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unsigned int fp_regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
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CORE_ADDR start_addr;
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xtensa_isa isa;
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xtensa_insnbuf ins, slot;
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char ibuf[XTENSA_ISA_BSZ];
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CORE_ADDR ia, bt, ba;
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xtensa_format ifmt;
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int ilen, islots, is;
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xtensa_opcode opc;
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const char *opcname;
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find_pc_partial_function (current_pc, NULL, &start_addr, NULL);
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if (start_addr == 0)
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return fp_regnum;
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if (!xtensa_default_isa)
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xtensa_default_isa = xtensa_isa_init (0, 0);
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isa = xtensa_default_isa;
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gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
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ins = xtensa_insnbuf_alloc (isa);
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slot = xtensa_insnbuf_alloc (isa);
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ba = 0;
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for (ia = start_addr, bt = ia; ia < current_pc ; ia += ilen)
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{
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if (ia + xtensa_isa_maxlength (isa) > bt)
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{
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ba = ia;
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bt = (ba + XTENSA_ISA_BSZ) < current_pc
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? ba + XTENSA_ISA_BSZ : current_pc;
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read_memory (ba, ibuf, bt - ba);
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}
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xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
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ifmt = xtensa_format_decode (isa, ins);
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if (ifmt == XTENSA_UNDEFINED)
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RETURN_FP;
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ilen = xtensa_format_length (isa, ifmt);
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if (ilen == XTENSA_UNDEFINED)
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RETURN_FP;
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islots = xtensa_format_num_slots (isa, ifmt);
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if (islots == XTENSA_UNDEFINED)
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RETURN_FP;
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for (is = 0; is < islots; ++is)
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{
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if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
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RETURN_FP;
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opc = xtensa_opcode_decode (isa, ifmt, is, slot);
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if (opc == XTENSA_UNDEFINED)
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RETURN_FP;
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opcname = xtensa_opcode_name (isa, opc);
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if (strcasecmp (opcname, "mov.n") == 0
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|| strcasecmp (opcname, "or") == 0)
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{
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unsigned int register_operand;
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/* Possible candidate for setting frame pointer
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from A1. This is what we are looking for. */
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if (xtensa_operand_get_field (isa, opc, 1, ifmt,
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is, slot, ®ister_operand) != 0)
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RETURN_FP;
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if (xtensa_operand_decode (isa, opc, 1, ®ister_operand) != 0)
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RETURN_FP;
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if (register_operand == 1) /* Mov{.n} FP A1. */
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{
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if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot,
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®ister_operand) != 0)
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RETURN_FP;
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if (xtensa_operand_decode (isa, opc, 0,
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®ister_operand) != 0)
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RETURN_FP;
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fp_regnum = gdbarch_tdep (gdbarch)->a0_base + register_operand;
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RETURN_FP;
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}
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}
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if (
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/* We have problems decoding the memory. */
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opcname == NULL
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|| strcasecmp (opcname, "ill") == 0
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|| strcasecmp (opcname, "ill.n") == 0
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/* Hit planted breakpoint. */
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|| strcasecmp (opcname, "break") == 0
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|| strcasecmp (opcname, "break.n") == 0
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/* Flow control instructions finish prologue. */
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|| xtensa_opcode_is_branch (isa, opc) > 0
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|| xtensa_opcode_is_jump (isa, opc) > 0
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|| xtensa_opcode_is_loop (isa, opc) > 0
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|| xtensa_opcode_is_call (isa, opc) > 0
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|| strcasecmp (opcname, "simcall") == 0
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|| strcasecmp (opcname, "syscall") == 0)
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/* Can not continue analysis. */
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RETURN_FP;
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}
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}
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done:
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xtensa_insnbuf_free(isa, slot);
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xtensa_insnbuf_free(isa, ins);
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return fp_regnum;
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}
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/* The key values to identify the frame using "cache" are
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cache->base = SP of this frame;
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cache->base = SP (or best guess about FP) of this frame;
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cache->pc = entry-PC (entry point of the frame function);
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cache->prev_sp = SP of the previous frame.
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*/
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@ -1047,6 +1189,7 @@ xtensa_frame_cache (struct frame_info *next_frame, void **this_cache)
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CORE_ADDR ra, wb, ws, pc, sp, ps;
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struct gdbarch *gdbarch = get_frame_arch (next_frame);
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unsigned int ps_regnum = gdbarch_ps_regnum (gdbarch);
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unsigned int fp_regnum;
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char op1;
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int windowed;
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@ -1090,21 +1233,35 @@ xtensa_frame_cache (struct frame_info *next_frame, void **this_cache)
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cache->wd.ws = ws;
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cache->prev_sp = frame_unwind_register_unsigned
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(next_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
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/* This only can be the outermost frame since we are
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just about to execute ENTRY. SP hasn't been set yet.
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We can assume any frame size, because it does not
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matter, and, let's fake frame base in cache. */
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cache->base = cache->prev_sp + 16;
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cache->pc = pc;
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cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff);
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cache->ps = (ps & ~PS_CALLINC_MASK)
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| ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
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return cache;
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}
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else
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{
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fp_regnum = xtensa_scan_prologue (gdbarch, pc);
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ra = frame_unwind_register_unsigned
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(next_frame, gdbarch_tdep (gdbarch)->a0_base);
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cache->wd.callsize = WINSIZE (ra);
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cache->wd.wb = (wb - cache->wd.callsize / 4)
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& (gdbarch_tdep (gdbarch)->num_aregs / 4 - 1);
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cache->wd.ws = ws & ~(1 << wb);
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}
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cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME);
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cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff);
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cache->ps = (ps & ~PS_CALLINC_MASK)
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| ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
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cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME);
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cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff);
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cache->ps = (ps & ~PS_CALLINC_MASK)
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| ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
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}
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if (cache->wd.ws == 0)
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{
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@ -1122,12 +1279,13 @@ xtensa_frame_cache (struct frame_info *next_frame, void **this_cache)
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if (cache->wd.callsize > 4)
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{
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/* Set A4...A7/A11. */
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/* Read an SP of the previous frame. */
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/* Get the SP of the frame previous to the previous one.
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To achieve this, we have to dereference SP twice. */
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sp = (CORE_ADDR) read_memory_integer (sp - 12, 4);
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sp = (CORE_ADDR) read_memory_integer (sp - 12, 4);
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sp -= cache->wd.callsize * 4;
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for ( /* i=4 */ ; i < cache->wd.callsize; i++, sp += 4)
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for ( i = 4; i < cache->wd.callsize; i++, sp += 4)
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{
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cache->wd.aregs[i] = sp;
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}
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@ -1138,19 +1296,18 @@ xtensa_frame_cache (struct frame_info *next_frame, void **this_cache)
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/* If RA is equal to 0 this frame is an outermost frame. Leave
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cache->prev_sp unchanged marking the boundary of the frame stack. */
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{
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if (cache->wd.ws == 0)
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if ((cache->wd.ws & (1 << cache->wd.wb)) == 0)
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{
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/* Register window overflow already happened.
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We can read caller's SP from the proper spill loction. */
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cache->prev_sp =
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read_memory_integer (cache->wd.aregs[1],
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register_size (gdbarch,
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gdbarch_tdep (gdbarch)->a0_base + 1));
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sp = frame_unwind_register_unsigned (next_frame,
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gdbarch_tdep (gdbarch)->a0_base + 1);
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cache->prev_sp = read_memory_integer (sp - 12, 4);
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}
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else
|
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{
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/* Read caller's frame SP directly from the previous window. */
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int regnum = areg_number
|
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int regnum = arreg_number
|
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(gdbarch, gdbarch_tdep (gdbarch)->a0_base + 1,
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cache->wd.wb);
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|
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@ -1161,10 +1318,10 @@ xtensa_frame_cache (struct frame_info *next_frame, void **this_cache)
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else /* Call0 framework. */
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||||
{
|
||||
call0_frame_cache (next_frame, cache, pc);
|
||||
fp_regnum = cache->c0.fp_regnum;
|
||||
}
|
||||
|
||||
cache->base = frame_unwind_register_unsigned
|
||||
(next_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
|
||||
cache->base = frame_unwind_register_unsigned (next_frame, fp_regnum);
|
||||
|
||||
return cache;
|
||||
}
|
||||
|
|
@ -1272,12 +1429,7 @@ xtensa_frame_prev_register (struct frame_info *next_frame,
|
|||
else if (!cache->call0)
|
||||
{
|
||||
if (regnum == gdbarch_tdep (gdbarch)->ws_regnum)
|
||||
{
|
||||
if (cache->wd.ws != 0)
|
||||
saved_reg = cache->wd.ws;
|
||||
else
|
||||
saved_reg = 1 << cache->wd.wb;
|
||||
}
|
||||
saved_reg = cache->wd.ws;
|
||||
else if (regnum == gdbarch_tdep (gdbarch)->wb_regnum)
|
||||
saved_reg = cache->wd.wb;
|
||||
else if (regnum == gdbarch_ps_regnum (gdbarch))
|
||||
|
|
@ -1302,18 +1454,18 @@ xtensa_frame_prev_register (struct frame_info *next_frame,
|
|||
|
||||
if (!cache->call0) /* Windowed ABI. */
|
||||
{
|
||||
/* Convert A-register numbers to AR-register numbers. */
|
||||
/* Convert A-register numbers to AR-register numbers,
|
||||
if we deal with A-register. */
|
||||
if (regnum >= gdbarch_tdep (gdbarch)->a0_base
|
||||
&& regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)
|
||||
regnum = areg_number (gdbarch, regnum, cache->wd.wb);
|
||||
regnum = arreg_number (gdbarch, regnum, cache->wd.wb);
|
||||
|
||||
/* Check if AR-register has been saved to stack. */
|
||||
/* Check, if we deal with AR-register saved on stack. */
|
||||
if (regnum >= gdbarch_tdep (gdbarch)->ar_base
|
||||
&& regnum <= (gdbarch_tdep (gdbarch)->ar_base
|
||||
+ gdbarch_tdep (gdbarch)->num_aregs))
|
||||
{
|
||||
int areg = regnum - gdbarch_tdep (gdbarch)->ar_base
|
||||
- (cache->wd.wb * 4);
|
||||
int areg = areg_number (gdbarch, regnum, cache->wd.wb);
|
||||
|
||||
if (areg >= 0
|
||||
&& areg < XTENSA_NUM_SAVED_AREGS
|
||||
|
|
@ -1443,7 +1595,7 @@ xtensa_extract_return_value (struct type *type,
|
|||
register (A2) in the caller window. */
|
||||
regcache_raw_read_unsigned
|
||||
(regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
|
||||
areg = areg_number (gdbarch,
|
||||
areg = arreg_number (gdbarch,
|
||||
gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
|
||||
}
|
||||
else
|
||||
|
|
@ -1493,8 +1645,8 @@ xtensa_store_return_value (struct type *type,
|
|||
internal_error (__FILE__, __LINE__,
|
||||
_("unimplemented for this length: %d"),
|
||||
TYPE_LENGTH (type));
|
||||
areg = areg_number (gdbarch,
|
||||
gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
|
||||
areg = arreg_number (gdbarch,
|
||||
gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
|
||||
|
||||
DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
|
||||
callsize, (int) wb);
|
||||
|
|
@ -2666,6 +2818,9 @@ xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
|
|||
set_gdbarch_regset_from_core_section (gdbarch,
|
||||
xtensa_regset_from_core_section);
|
||||
|
||||
set_solib_svr4_fetch_link_map_offsets
|
||||
(gdbarch, svr4_ilp32_fetch_link_map_offsets);
|
||||
|
||||
return gdbarch;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue