* gas/config/tc-arm.c (arm_ext_adiv): New variable.
(do_div): New function. (insns): Accept UDIV and SDIV in ARM state. (arm_cpus): The cortex-a15 option has all current v7-A extensions. (arm_extensions): Add 'idiv' extension. (aeabi_set_public_attributes): Update Tag_DIV_use values for the Integer Divide extension. * gas/doc/c-arm.texi: Document the idiv extension. * gas/testsuite/gas/arm/armv7-a+idiv.d: New test. * gas/testsuite/gas/arm/armv7-a+idiv.s: Likewise. * gas/testsuite/gas/arm/attr-march-all.d: Update for Integer divide extension. * gas/testsuite/gas/arm/attr-march-armv7-a+idiv.d: New test. * include/opcode/arm.h (ARM_AEXT_ADIV): New define. (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise. * opcodes/arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in ARM state.
This commit is contained in:
Matthew Gretton-Dann
parent
b2a5fbdc94
commit
eea54501f7
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@ -1,3 +1,14 @@
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2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* config/tc-arm.c (arm_ext_adiv): New variable.
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(do_div): New function.
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(insns): Accept UDIV and SDIV in ARM state.
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(arm_cpus): The cortex-a15 option has all current v7-A extensions.
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(arm_extensions): Add 'idiv' extension.
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(aeabi_set_public_attributes): Update Tag_DIV_use values for the
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Integer Divide extension.
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* doc/c-arm.texi: Document the idiv extension.
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2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* config/tc-arm.c (arm_ext_v6m): New variable.
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@ -200,6 +200,7 @@ static const arm_feature_set arm_ext_m =
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static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
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static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
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static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0);
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static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0);
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static const arm_feature_set arm_arch_any = ARM_ANY;
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static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
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@ -7491,6 +7492,25 @@ do_dbg (void)
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inst.instruction |= inst.operands[0].imm;
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}
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static void
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do_div (void)
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{
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unsigned Rd, Rn, Rm;
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Rd = inst.operands[0].reg;
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Rn = (inst.operands[1].present
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? inst.operands[1].reg : Rd);
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Rm = inst.operands[2].reg;
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constraint ((Rd == REG_PC), BAD_PC);
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constraint ((Rn == REG_PC), BAD_PC);
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constraint ((Rm == REG_PC), BAD_PC);
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inst.instruction |= Rd << 16;
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inst.instruction |= Rn << 0;
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inst.instruction |= Rm << 8;
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}
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static void
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do_it (void)
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{
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@ -17130,12 +17150,14 @@ static const struct asm_opcode insns[] =
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TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
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TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
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/* Thumb-2 hardware division instructions (R and M profiles only). */
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/* Hardware division instructions. */
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#undef ARM_VARIANT
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#define ARM_VARIANT & arm_ext_adiv
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#undef THUMB_VARIANT
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#define THUMB_VARIANT & arm_ext_div
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TCE("sdiv", 0, fb90f0f0, 3, (RR, oRR, RR), 0, t_div),
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TCE("udiv", 0, fbb0f0f0, 3, (RR, oRR, RR), 0, t_div),
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TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
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TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
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/* ARM V6M/V7 instructions. */
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#undef ARM_VARIANT
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@ -22408,8 +22430,8 @@ static const struct arm_cpu_option_table arm_cpus[] =
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ARM_FEATURE (0, FPU_VFP_V3
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| FPU_NEON_EXT_V1),
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"Cortex-A9"},
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{"cortex-a15", ARM_ARCH_V7A_MP_SEC,
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FPU_ARCH_NEON_VFP_V4,
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{"cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC,
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FPU_ARCH_NEON_VFP_V4,
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"Cortex-A15"},
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{"cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"},
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{"cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
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@ -22496,6 +22518,8 @@ struct arm_option_extension_value_table
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*/
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static const struct arm_option_extension_value_table arm_extensions[] =
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{
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{"idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
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ARM_FEATURE (ARM_EXT_V7A, 0)},
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{"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY},
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{"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY},
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{"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY},
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@ -23177,11 +23201,10 @@ aeabi_set_public_attributes (void)
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aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
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/* Tag_DIV_use. */
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if (ARM_CPU_HAS_FEATURE (flags, arm_ext_div))
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if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv))
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aeabi_set_attribute_int (Tag_DIV_use, 2);
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else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_div))
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aeabi_set_attribute_int (Tag_DIV_use, 0);
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/* Fill this in when gas supports v7a sdiv/udiv.
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else if (... v7a with div extension used ...)
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aeabi_set_attribute_int (Tag_DIV_use, 2); */
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else
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aeabi_set_attribute_int (Tag_DIV_use, 1);
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@ -148,7 +148,8 @@ been added, again in ascending alphabetical order. For example,
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@code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
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The following extensions are currently supported:
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The following extensions are currently supported:
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@code{idiv}, (Integer Divide Extensions for v7-A architecture),
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@code{iwmmxt},
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@code{iwmmxt2},
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@code{maverick},
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@ -1,3 +1,10 @@
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2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* gas/arm/armv7-a+idiv.d: New test.
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* gas/arm/armv7-a+idiv.s: Likewise.
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* gas/arm/attr-march-all.d: Update for Integer divide extension.
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* gas/arm/attr-march-armv7-a+idiv.d: New test.
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2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* gas/arm/archv6s-m-bad.d: New test.
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@ -0,0 +1,10 @@
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#name: Valid v7-A+IDIV
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#objdump: -dr --prefix-addresses --show-raw-insn
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.*: +file format .*arm.*
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Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> e730f211 udiv r0, r1, r2
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0[0-9a-f]+ <[^>]+> e710f211 sdiv r0, r1, r2
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0[0-9a-f]+ <[^>]+> fbb1 f0f2 udiv r0, r1, r2
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0[0-9a-f]+ <[^>]+> fb91 f0f2 sdiv r0, r1, r2
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@ -0,0 +1,14 @@
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.syntax unified
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.text
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.arch armv7-a
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.arch_extension idiv
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foo:
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udiv r0, r1, r2
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sdiv r0, r1, r2
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.thumb
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.thumb_func
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bar:
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udiv r0, r1, r2
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sdiv r0, r1, r2
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@ -13,4 +13,5 @@ File Attributes
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Tag_ARM_ISA_use: Yes
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Tag_THUMB_ISA_use: Thumb-2
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Tag_MPextension_use: Allowed
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Tag_DIV_use: Allowed in v7-A with integer division extension
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Tag_Virtualization_use: TrustZone
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@ -0,0 +1,15 @@
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# name: attributes for -march=armv7-a+idiv
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# source: blank.s
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# as: -march=armv7-a+idiv
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# readelf: -A
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# This test is only valid on EABI based ports.
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# target: *-*-*eabi
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Attribute Section: aeabi
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File Attributes
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Tag_CPU_name: "7-A"
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Tag_CPU_arch: v7
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Tag_CPU_arch_profile: Application
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Tag_ARM_ISA_use: Yes
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Tag_THUMB_ISA_use: Thumb-2
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Tag_DIV_use: Allowed in v7-A with integer division extension
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@ -1,3 +1,8 @@
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2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* arm.h (ARM_AEXT_ADIV): New define.
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(ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
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2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* arm.h (ARM_EXT_OS): New define.
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@ -52,6 +52,8 @@
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#define ARM_EXT_MP 0x08000000 /* Multiprocessing Extensions. */
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#define ARM_EXT_SEC 0x10000000 /* Security extensions. */
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#define ARM_EXT_OS 0x20000000 /* OS Extensions. */
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#define ARM_EXT_ADIV 0x40000000 /* Integer divide extensions in ARM
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state. */
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/* Co-processor space extensions. */
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#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
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@ -220,6 +222,10 @@
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#define ARM_ARCH_V7A_MP_SEC \
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ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, \
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0)
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/* v7-a+idiv+mp+sec. */
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#define ARM_ARCH_V7A_IDIV_MP_SEC \
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ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC \
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| ARM_EXT_DIV | ARM_EXT_ADIV, 0)
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/* There are too many feature bits to fit in a single word, so use a
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structure. For simplicity we put all core features in one word and
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@ -1,3 +1,8 @@
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2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
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ARM state.
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2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* arm-dis.c (arm_opcodes): SMC implies Security Extensions.
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@ -829,6 +829,10 @@ static const struct opcode32 arm_opcodes[] =
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{ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
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{ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
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/* Integer Divide Extension instructions. */
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{ARM_EXT_ADIV, 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
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{ARM_EXT_ADIV, 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
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/* MP Extension instructions. */
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{ARM_EXT_MP, 0xf410f000, 0xfc70f000, "pldw\t%a"},
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