2004-08-01 Andrew Cagney <cagney@gnu.org>
* mips-tdep.c (mips16_frame_cache) (mips16_frame_this_id, mips16_frame_prev_register) (mips16_frame_unwind, mips16_frame_sniffer) (mips16_frame_base_address, mips16_frame_base) (mips16_frame_base_sniffer, mips32_frame_cache) (mips32_frame_this_id, mips32_frame_prev_register) (mips32_frame_unwind, mips32_frame_sniffer) (mips32_frame_base_address, mips32_frame_base) (mips32_frame_base_sniffer): Clone the mdebug unwinder into separate heuristic mips16 and mips32 unwinders. (mips_stub_frame_cache, mips_stub_frame_this_id) (mips_stub_frame_prev_register) (mips_stub_frame_unwind, mips_stub_frame_sniffer) (mips_stub_frame_base_address, mips_stub_frame_base) (mips_stub_frame_base_sniffer): Add a simple stub unwinder. (mips_mdebug_frame_base_sniffer, mips_mdebug_frame_sniffer): Only match true mdebug frames. (non_heuristic_proc_desc): Add forward declaration.
This commit is contained in:
Andrew Cagney
parent
83cbbf3ecb
commit
eec6393997
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@ -1,3 +1,24 @@
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2004-08-01 Andrew Cagney <cagney@gnu.org>
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* mips-tdep.c (mips16_frame_cache)
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(mips16_frame_this_id, mips16_frame_prev_register)
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(mips16_frame_unwind, mips16_frame_sniffer)
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(mips16_frame_base_address, mips16_frame_base)
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(mips16_frame_base_sniffer, mips32_frame_cache)
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(mips32_frame_this_id, mips32_frame_prev_register)
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(mips32_frame_unwind, mips32_frame_sniffer)
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(mips32_frame_base_address, mips32_frame_base)
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(mips32_frame_base_sniffer): Clone the mdebug unwinder into
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separate heuristic mips16 and mips32 unwinders.
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(mips_stub_frame_cache, mips_stub_frame_this_id)
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(mips_stub_frame_prev_register)
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(mips_stub_frame_unwind, mips_stub_frame_sniffer)
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(mips_stub_frame_base_address, mips_stub_frame_base)
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(mips_stub_frame_base_sniffer): Add a simple stub unwinder.
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(mips_mdebug_frame_base_sniffer, mips_mdebug_frame_sniffer): Only
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match true mdebug frames.
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(non_heuristic_proc_desc): Add forward declaration.
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2004-08-01 Andrew Cagney <cagney@gnu.org>
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* config/mips/tm-irix6.h: Delete file.
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634
gdb/mips-tdep.c
634
gdb/mips-tdep.c
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@ -395,6 +395,8 @@ mips_stack_argsize (struct gdbarch *gdbarch)
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static mips_extra_func_info_t heuristic_proc_desc (CORE_ADDR, CORE_ADDR,
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struct frame_info *, int);
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static mips_extra_func_info_t non_heuristic_proc_desc (CORE_ADDR pc,
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CORE_ADDR *addrptr);
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static CORE_ADDR heuristic_proc_start (CORE_ADDR);
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@ -1720,7 +1722,35 @@ static const struct frame_unwind mips_mdebug_frame_unwind =
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static const struct frame_unwind *
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mips_mdebug_frame_sniffer (struct frame_info *next_frame)
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{
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return &mips_mdebug_frame_unwind;
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CORE_ADDR pc = frame_pc_unwind (next_frame);
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CORE_ADDR startaddr = 0;
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mips_extra_func_info_t proc_desc;
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int kernel_trap;
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/* Only use the mdebug frame unwinder on mdebug frames where all the
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registers have been saved. Leave hard cases such as no mdebug or
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in prologue for the heuristic unwinders. */
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proc_desc = non_heuristic_proc_desc (pc, &startaddr);
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if (proc_desc == NULL)
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return NULL;
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/* Not sure exactly what kernel_trap means, but if it means the
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kernel saves the registers without a prologue doing it, we better
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not examine the prologue to see whether registers have been saved
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yet. */
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kernel_trap = PROC_REG_MASK (proc_desc) & 1;
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if (kernel_trap)
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return &mips_mdebug_frame_unwind;
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/* In any frame other than the innermost or a frame interrupted by a
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signal, we assume that all registers have been saved. This
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assumes that all register saves in a function happen before the
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first function call. */
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if (!in_prologue (pc, PROC_LOW_ADDR (proc_desc)))
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return &mips_mdebug_frame_unwind;
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return NULL;
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}
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static CORE_ADDR
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@ -1742,7 +1772,601 @@ static const struct frame_base mips_mdebug_frame_base = {
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static const struct frame_base *
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mips_mdebug_frame_base_sniffer (struct frame_info *next_frame)
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{
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return &mips_mdebug_frame_base;
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if (mips_mdebug_frame_sniffer (next_frame) != NULL)
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return &mips_mdebug_frame_base;
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else
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return NULL;
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}
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static struct mips_frame_cache *
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mips16_frame_cache (struct frame_info *next_frame, void **this_cache)
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{
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mips_extra_func_info_t proc_desc;
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struct mips_frame_cache *cache;
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struct gdbarch *gdbarch = get_frame_arch (next_frame);
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struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
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/* r0 bit means kernel trap */
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int kernel_trap;
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/* What registers have been saved? Bitmasks. */
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unsigned long gen_mask, float_mask;
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if ((*this_cache) != NULL)
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return (*this_cache);
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cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
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(*this_cache) = cache;
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cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
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/* Get the mdebug proc descriptor. */
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proc_desc = find_proc_desc (frame_pc_unwind (next_frame), next_frame, 1);
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if (proc_desc == NULL)
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/* I'm not sure how/whether this can happen. Normally when we
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can't find a proc_desc, we "synthesize" one using
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heuristic_proc_desc and set the saved_regs right away. */
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return cache;
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/* Extract the frame's base. */
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cache->base = (frame_unwind_register_signed (next_frame, NUM_REGS + PROC_FRAME_REG (proc_desc))
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+ PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc));
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kernel_trap = PROC_REG_MASK (proc_desc) & 1;
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gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc);
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float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc);
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/* In any frame other than the innermost or a frame interrupted by a
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signal, we assume that all registers have been saved. This
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assumes that all register saves in a function happen before the
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first function call. */
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if (in_prologue (frame_pc_unwind (next_frame), PROC_LOW_ADDR (proc_desc))
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/* Not sure exactly what kernel_trap means, but if it means the
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kernel saves the registers without a prologue doing it, we
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better not examine the prologue to see whether registers
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have been saved yet. */
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&& !kernel_trap)
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{
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/* We need to figure out whether the registers that the
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proc_desc claims are saved have been saved yet. */
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CORE_ADDR addr;
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/* Bitmasks; set if we have found a save for the register. */
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unsigned long gen_save_found = 0;
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unsigned long float_save_found = 0;
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int mips16;
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/* If the address is odd, assume this is MIPS16 code. */
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addr = PROC_LOW_ADDR (proc_desc);
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mips16 = pc_is_mips16 (addr);
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/* Scan through this function's instructions preceding the
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current PC, and look for those that save registers. */
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while (addr < frame_pc_unwind (next_frame))
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{
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if (mips16)
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{
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mips16_decode_reg_save (mips16_fetch_instruction (addr),
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&gen_save_found);
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addr += MIPS16_INSTLEN;
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}
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else
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{
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mips32_decode_reg_save (mips32_fetch_instruction (addr),
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&gen_save_found, &float_save_found);
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addr += MIPS_INSTLEN;
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}
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}
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gen_mask = gen_save_found;
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float_mask = float_save_found;
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}
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/* Fill in the offsets for the registers which gen_mask says were
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saved. */
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{
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CORE_ADDR reg_position = (cache->base
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+ PROC_REG_OFFSET (proc_desc));
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int ireg;
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for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1)
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if (gen_mask & 0x80000000)
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{
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cache->saved_regs[NUM_REGS + ireg].addr = reg_position;
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reg_position -= mips_abi_regsize (gdbarch);
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}
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}
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/* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
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order of that normally used by gcc. Therefore, we have to fetch
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the first instruction of the function, and if it's an entry
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instruction that saves $s0 or $s1, correct their saved addresses. */
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if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc)))
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{
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ULONGEST inst = mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc));
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if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700)
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/* entry */
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{
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int reg;
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int sreg_count = (inst >> 6) & 3;
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/* Check if the ra register was pushed on the stack. */
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CORE_ADDR reg_position = (cache->base
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+ PROC_REG_OFFSET (proc_desc));
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if (inst & 0x20)
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reg_position -= mips_abi_regsize (gdbarch);
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/* Check if the s0 and s1 registers were pushed on the
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stack. */
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/* NOTE: cagney/2004-02-08: Huh? This is doing no such
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check. */
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for (reg = 16; reg < sreg_count + 16; reg++)
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{
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cache->saved_regs[NUM_REGS + reg].addr = reg_position;
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reg_position -= mips_abi_regsize (gdbarch);
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}
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}
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}
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/* Fill in the offsets for the registers which float_mask says were
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saved. */
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{
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CORE_ADDR reg_position = (cache->base
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+ PROC_FREG_OFFSET (proc_desc));
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int ireg;
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/* Fill in the offsets for the float registers which float_mask
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says were saved. */
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for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1)
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if (float_mask & 0x80000000)
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{
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if (mips_abi_regsize (gdbarch) == 4
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&& TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
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{
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/* On a big endian 32 bit ABI, floating point registers
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are paired to form doubles such that the most
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significant part is in $f[N+1] and the least
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significant in $f[N] vis: $f[N+1] ||| $f[N]. The
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registers are also spilled as a pair and stored as a
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double.
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When little-endian the least significant part is
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stored first leading to the memory order $f[N] and
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then $f[N+1].
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Unfortunately, when big-endian the most significant
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part of the double is stored first, and the least
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significant is stored second. This leads to the
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registers being ordered in memory as firt $f[N+1] and
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then $f[N].
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For the big-endian case make certain that the
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addresses point at the correct (swapped) locations
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$f[N] and $f[N+1] pair (keep in mind that
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reg_position is decremented each time through the
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loop). */
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if ((ireg & 1))
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cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg]
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.addr = reg_position - mips_abi_regsize (gdbarch);
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else
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cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg]
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.addr = reg_position + mips_abi_regsize (gdbarch);
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}
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else
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cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg]
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.addr = reg_position;
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reg_position -= mips_abi_regsize (gdbarch);
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}
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cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc]
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= cache->saved_regs[NUM_REGS + RA_REGNUM];
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}
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/* SP_REGNUM, contains the value and not the address. */
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trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base);
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return (*this_cache);
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}
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static void
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mips16_frame_this_id (struct frame_info *next_frame, void **this_cache,
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struct frame_id *this_id)
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{
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struct mips_frame_cache *info = mips16_frame_cache (next_frame,
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this_cache);
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(*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame));
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}
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static void
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mips16_frame_prev_register (struct frame_info *next_frame,
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void **this_cache,
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int regnum, int *optimizedp,
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enum lval_type *lvalp, CORE_ADDR *addrp,
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int *realnump, void *valuep)
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{
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struct mips_frame_cache *info = mips16_frame_cache (next_frame,
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this_cache);
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trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
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optimizedp, lvalp, addrp, realnump, valuep);
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}
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static const struct frame_unwind mips16_frame_unwind =
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{
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NORMAL_FRAME,
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mips16_frame_this_id,
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mips16_frame_prev_register
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};
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static const struct frame_unwind *
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mips16_frame_sniffer (struct frame_info *next_frame)
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{
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CORE_ADDR pc = frame_pc_unwind (next_frame);
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if (pc_is_mips16 (pc))
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return &mips16_frame_unwind;
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return NULL;
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}
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static CORE_ADDR
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mips16_frame_base_address (struct frame_info *next_frame,
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void **this_cache)
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{
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struct mips_frame_cache *info = mips16_frame_cache (next_frame,
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this_cache);
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return info->base;
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}
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static const struct frame_base mips16_frame_base =
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{
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&mips16_frame_unwind,
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mips16_frame_base_address,
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mips16_frame_base_address,
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mips16_frame_base_address
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};
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static const struct frame_base *
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mips16_frame_base_sniffer (struct frame_info *next_frame)
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{
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if (mips16_frame_sniffer (next_frame) != NULL)
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return &mips16_frame_base;
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else
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return NULL;
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}
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static struct mips_frame_cache *
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mips32_frame_cache (struct frame_info *next_frame, void **this_cache)
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{
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mips_extra_func_info_t proc_desc;
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struct mips_frame_cache *cache;
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struct gdbarch *gdbarch = get_frame_arch (next_frame);
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struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
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/* r0 bit means kernel trap */
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int kernel_trap;
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/* What registers have been saved? Bitmasks. */
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unsigned long gen_mask, float_mask;
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if ((*this_cache) != NULL)
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return (*this_cache);
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cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache);
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(*this_cache) = cache;
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cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
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/* Get the mdebug proc descriptor. */
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proc_desc = find_proc_desc (frame_pc_unwind (next_frame), next_frame, 1);
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if (proc_desc == NULL)
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/* I'm not sure how/whether this can happen. Normally when we
|
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can't find a proc_desc, we "synthesize" one using
|
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heuristic_proc_desc and set the saved_regs right away. */
|
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return cache;
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/* Extract the frame's base. */
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cache->base = (frame_unwind_register_signed (next_frame, NUM_REGS + PROC_FRAME_REG (proc_desc))
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+ PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc));
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kernel_trap = PROC_REG_MASK (proc_desc) & 1;
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gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc);
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float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc);
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/* In any frame other than the innermost or a frame interrupted by a
|
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signal, we assume that all registers have been saved. This
|
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assumes that all register saves in a function happen before the
|
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first function call. */
|
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if (in_prologue (frame_pc_unwind (next_frame), PROC_LOW_ADDR (proc_desc))
|
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/* Not sure exactly what kernel_trap means, but if it means the
|
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kernel saves the registers without a prologue doing it, we
|
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better not examine the prologue to see whether registers
|
||||
have been saved yet. */
|
||||
&& !kernel_trap)
|
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{
|
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/* We need to figure out whether the registers that the
|
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proc_desc claims are saved have been saved yet. */
|
||||
|
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CORE_ADDR addr;
|
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|
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/* Bitmasks; set if we have found a save for the register. */
|
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unsigned long gen_save_found = 0;
|
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unsigned long float_save_found = 0;
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int mips16;
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/* If the address is odd, assume this is MIPS16 code. */
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addr = PROC_LOW_ADDR (proc_desc);
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mips16 = pc_is_mips16 (addr);
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/* Scan through this function's instructions preceding the
|
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current PC, and look for those that save registers. */
|
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while (addr < frame_pc_unwind (next_frame))
|
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{
|
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if (mips16)
|
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{
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mips16_decode_reg_save (mips16_fetch_instruction (addr),
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&gen_save_found);
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addr += MIPS16_INSTLEN;
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}
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else
|
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{
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mips32_decode_reg_save (mips32_fetch_instruction (addr),
|
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&gen_save_found, &float_save_found);
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addr += MIPS_INSTLEN;
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}
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}
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gen_mask = gen_save_found;
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float_mask = float_save_found;
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||||
}
|
||||
|
||||
/* Fill in the offsets for the registers which gen_mask says were
|
||||
saved. */
|
||||
{
|
||||
CORE_ADDR reg_position = (cache->base
|
||||
+ PROC_REG_OFFSET (proc_desc));
|
||||
int ireg;
|
||||
for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1)
|
||||
if (gen_mask & 0x80000000)
|
||||
{
|
||||
cache->saved_regs[NUM_REGS + ireg].addr = reg_position;
|
||||
reg_position -= mips_abi_regsize (gdbarch);
|
||||
}
|
||||
}
|
||||
|
||||
/* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
|
||||
order of that normally used by gcc. Therefore, we have to fetch
|
||||
the first instruction of the function, and if it's an entry
|
||||
instruction that saves $s0 or $s1, correct their saved addresses. */
|
||||
if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc)))
|
||||
{
|
||||
ULONGEST inst = mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc));
|
||||
if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700)
|
||||
/* entry */
|
||||
{
|
||||
int reg;
|
||||
int sreg_count = (inst >> 6) & 3;
|
||||
|
||||
/* Check if the ra register was pushed on the stack. */
|
||||
CORE_ADDR reg_position = (cache->base
|
||||
+ PROC_REG_OFFSET (proc_desc));
|
||||
if (inst & 0x20)
|
||||
reg_position -= mips_abi_regsize (gdbarch);
|
||||
|
||||
/* Check if the s0 and s1 registers were pushed on the
|
||||
stack. */
|
||||
/* NOTE: cagney/2004-02-08: Huh? This is doing no such
|
||||
check. */
|
||||
for (reg = 16; reg < sreg_count + 16; reg++)
|
||||
{
|
||||
cache->saved_regs[NUM_REGS + reg].addr = reg_position;
|
||||
reg_position -= mips_abi_regsize (gdbarch);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Fill in the offsets for the registers which float_mask says were
|
||||
saved. */
|
||||
{
|
||||
CORE_ADDR reg_position = (cache->base
|
||||
+ PROC_FREG_OFFSET (proc_desc));
|
||||
int ireg;
|
||||
/* Fill in the offsets for the float registers which float_mask
|
||||
says were saved. */
|
||||
for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1)
|
||||
if (float_mask & 0x80000000)
|
||||
{
|
||||
if (mips_abi_regsize (gdbarch) == 4
|
||||
&& TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
|
||||
{
|
||||
/* On a big endian 32 bit ABI, floating point registers
|
||||
are paired to form doubles such that the most
|
||||
significant part is in $f[N+1] and the least
|
||||
significant in $f[N] vis: $f[N+1] ||| $f[N]. The
|
||||
registers are also spilled as a pair and stored as a
|
||||
double.
|
||||
|
||||
When little-endian the least significant part is
|
||||
stored first leading to the memory order $f[N] and
|
||||
then $f[N+1].
|
||||
|
||||
Unfortunately, when big-endian the most significant
|
||||
part of the double is stored first, and the least
|
||||
significant is stored second. This leads to the
|
||||
registers being ordered in memory as firt $f[N+1] and
|
||||
then $f[N].
|
||||
|
||||
For the big-endian case make certain that the
|
||||
addresses point at the correct (swapped) locations
|
||||
$f[N] and $f[N+1] pair (keep in mind that
|
||||
reg_position is decremented each time through the
|
||||
loop). */
|
||||
if ((ireg & 1))
|
||||
cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg]
|
||||
.addr = reg_position - mips_abi_regsize (gdbarch);
|
||||
else
|
||||
cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg]
|
||||
.addr = reg_position + mips_abi_regsize (gdbarch);
|
||||
}
|
||||
else
|
||||
cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->fp0 + ireg]
|
||||
.addr = reg_position;
|
||||
reg_position -= mips_abi_regsize (gdbarch);
|
||||
}
|
||||
|
||||
cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc]
|
||||
= cache->saved_regs[NUM_REGS + RA_REGNUM];
|
||||
}
|
||||
|
||||
/* SP_REGNUM, contains the value and not the address. */
|
||||
trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base);
|
||||
|
||||
return (*this_cache);
|
||||
}
|
||||
|
||||
static void
|
||||
mips32_frame_this_id (struct frame_info *next_frame, void **this_cache,
|
||||
struct frame_id *this_id)
|
||||
{
|
||||
struct mips_frame_cache *info = mips32_frame_cache (next_frame,
|
||||
this_cache);
|
||||
(*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame));
|
||||
}
|
||||
|
||||
static void
|
||||
mips32_frame_prev_register (struct frame_info *next_frame,
|
||||
void **this_cache,
|
||||
int regnum, int *optimizedp,
|
||||
enum lval_type *lvalp, CORE_ADDR *addrp,
|
||||
int *realnump, void *valuep)
|
||||
{
|
||||
struct mips_frame_cache *info = mips32_frame_cache (next_frame,
|
||||
this_cache);
|
||||
trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
|
||||
optimizedp, lvalp, addrp, realnump, valuep);
|
||||
}
|
||||
|
||||
static const struct frame_unwind mips32_frame_unwind =
|
||||
{
|
||||
NORMAL_FRAME,
|
||||
mips32_frame_this_id,
|
||||
mips32_frame_prev_register
|
||||
};
|
||||
|
||||
static const struct frame_unwind *
|
||||
mips32_frame_sniffer (struct frame_info *next_frame)
|
||||
{
|
||||
CORE_ADDR pc = frame_pc_unwind (next_frame);
|
||||
if (! pc_is_mips16 (pc))
|
||||
return &mips32_frame_unwind;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static CORE_ADDR
|
||||
mips32_frame_base_address (struct frame_info *next_frame,
|
||||
void **this_cache)
|
||||
{
|
||||
struct mips_frame_cache *info = mips32_frame_cache (next_frame,
|
||||
this_cache);
|
||||
return info->base;
|
||||
}
|
||||
|
||||
static const struct frame_base mips32_frame_base =
|
||||
{
|
||||
&mips32_frame_unwind,
|
||||
mips32_frame_base_address,
|
||||
mips32_frame_base_address,
|
||||
mips32_frame_base_address
|
||||
};
|
||||
|
||||
static const struct frame_base *
|
||||
mips32_frame_base_sniffer (struct frame_info *next_frame)
|
||||
{
|
||||
if (mips32_frame_sniffer (next_frame) != NULL)
|
||||
return &mips32_frame_base;
|
||||
else
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static struct trad_frame_cache *
|
||||
mips_stub_frame_cache (struct frame_info *next_frame, void **this_cache)
|
||||
{
|
||||
CORE_ADDR pc;
|
||||
CORE_ADDR start_addr;
|
||||
CORE_ADDR stack_addr;
|
||||
struct trad_frame_cache *this_trad_cache;
|
||||
|
||||
if ((*this_cache) != NULL)
|
||||
return (*this_cache);
|
||||
this_trad_cache = trad_frame_cache_zalloc (next_frame);
|
||||
(*this_cache) = this_trad_cache;
|
||||
|
||||
/* The return address is in the link register. */
|
||||
trad_frame_set_reg_realreg (this_trad_cache, PC_REGNUM, RA_REGNUM);
|
||||
|
||||
/* Frame ID, since it's a frameless / stackless function, no stack
|
||||
space is allocated and SP on entry is the current SP. */
|
||||
pc = frame_pc_unwind (next_frame);
|
||||
find_pc_partial_function (pc, NULL, &start_addr, NULL);
|
||||
stack_addr = frame_unwind_register_signed (next_frame, SP_REGNUM);
|
||||
trad_frame_set_id (this_trad_cache, frame_id_build (start_addr, stack_addr));
|
||||
|
||||
/* Assume that the frame's base is the same as the
|
||||
stack-pointer. */
|
||||
trad_frame_set_this_base (this_trad_cache, stack_addr);
|
||||
|
||||
return this_trad_cache;
|
||||
}
|
||||
|
||||
static void
|
||||
mips_stub_frame_this_id (struct frame_info *next_frame, void **this_cache,
|
||||
struct frame_id *this_id)
|
||||
{
|
||||
struct trad_frame_cache *this_trad_cache
|
||||
= mips_stub_frame_cache (next_frame, this_cache);
|
||||
trad_frame_get_id (this_trad_cache, this_id);
|
||||
}
|
||||
|
||||
static void
|
||||
mips_stub_frame_prev_register (struct frame_info *next_frame,
|
||||
void **this_cache,
|
||||
int regnum, int *optimizedp,
|
||||
enum lval_type *lvalp, CORE_ADDR *addrp,
|
||||
int *realnump, void *valuep)
|
||||
{
|
||||
struct trad_frame_cache *this_trad_cache
|
||||
= mips_stub_frame_cache (next_frame, this_cache);
|
||||
trad_frame_get_register (this_trad_cache, next_frame, regnum, optimizedp,
|
||||
lvalp, addrp, realnump, valuep);
|
||||
}
|
||||
|
||||
static const struct frame_unwind mips_stub_frame_unwind =
|
||||
{
|
||||
NORMAL_FRAME,
|
||||
mips_stub_frame_this_id,
|
||||
mips_stub_frame_prev_register
|
||||
};
|
||||
|
||||
static const struct frame_unwind *
|
||||
mips_stub_frame_sniffer (struct frame_info *next_frame)
|
||||
{
|
||||
CORE_ADDR pc = frame_pc_unwind (next_frame);
|
||||
if (in_plt_section (pc, NULL))
|
||||
return &mips_stub_frame_unwind;
|
||||
else
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static CORE_ADDR
|
||||
mips_stub_frame_base_address (struct frame_info *next_frame,
|
||||
void **this_cache)
|
||||
{
|
||||
struct trad_frame_cache *this_trad_cache
|
||||
= mips_stub_frame_cache (next_frame, this_cache);
|
||||
return trad_frame_get_this_base (this_trad_cache);
|
||||
}
|
||||
|
||||
static const struct frame_base mips_stub_frame_base =
|
||||
{
|
||||
&mips_stub_frame_unwind,
|
||||
mips_stub_frame_base_address,
|
||||
mips_stub_frame_base_address,
|
||||
mips_stub_frame_base_address
|
||||
};
|
||||
|
||||
static const struct frame_base *
|
||||
mips_stub_frame_base_sniffer (struct frame_info *next_frame)
|
||||
{
|
||||
if (mips_stub_frame_sniffer (next_frame) != NULL)
|
||||
return &mips_stub_frame_base;
|
||||
else
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static CORE_ADDR
|
||||
|
|
@ -5801,8 +6425,14 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
|
|||
gdbarch_init_osabi (info, gdbarch);
|
||||
|
||||
/* Unwind the frame. */
|
||||
frame_unwind_append_sniffer (gdbarch, mips_stub_frame_sniffer);
|
||||
frame_unwind_append_sniffer (gdbarch, mips_mdebug_frame_sniffer);
|
||||
frame_unwind_append_sniffer (gdbarch, mips16_frame_sniffer);
|
||||
frame_unwind_append_sniffer (gdbarch, mips32_frame_sniffer);
|
||||
frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer);
|
||||
frame_base_append_sniffer (gdbarch, mips_mdebug_frame_base_sniffer);
|
||||
frame_base_append_sniffer (gdbarch, mips16_frame_base_sniffer);
|
||||
frame_base_append_sniffer (gdbarch, mips32_frame_base_sniffer);
|
||||
|
||||
return gdbarch;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue