Support for gcc to generate 16-bit i386 code. (.code16gcc)
This commit is contained in:
Alan Modra
parent
23b255aadd
commit
eecb386cd7
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@ -1,3 +1,27 @@
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1999-08-04 Alan Modra <alan@spri.levels.unisa.edu.au>
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* config/tc-i386.c (i386_operand): No need to change
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operand_string pointer in segment reg case before goto
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do_memory_reference. Initialise displacement_string_start and
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displacement_string_end after do_memory_reference label.
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(i386_index_check): Add operand_string param, and print error
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message on failure here.
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(i386_intel_memory_operand): Instead of here.
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(i386_operand): And here.
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(INFER_ADDR_PREFIX): Enable.
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* doc/c-i386.texi (i386-16bit): Document .code16gcc.
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* config/tc-i386.h (DefaultSize): Define. Renumber following
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opcode_modifier defines.
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From Etienne Lorrain <etienne.lorrain@ibm.net>
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* config/tc-i386.c (stackop_size): New variable.
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(set_16bit_code_flag): Clear it here.
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(set_16bit_gcc_code_flag): New function.
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(md_pseudo_table): Add "code16gcc" entry.
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(md_assemble): Set i.suffix for insns with DefaultSize modifier.
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1999-08-03 Ian Lance Taylor <ian@zembu.com>
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* config/obj-coff.c (coff_frob_symbol): Always update set_end with
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@ -41,7 +41,7 @@
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#endif
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#ifndef INFER_ADDR_PREFIX
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#define INFER_ADDR_PREFIX 0
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#define INFER_ADDR_PREFIX 1
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#endif
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#ifndef SCALE1_WHEN_NO_INDEX
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@ -63,6 +63,7 @@ static int fits_in_signed_word PARAMS ((long));
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static int smallest_imm_type PARAMS ((long));
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static int add_prefix PARAMS ((unsigned int));
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static void set_16bit_code_flag PARAMS ((int));
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static void set_16bit_gcc_code_flag PARAMS((int));
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static void set_intel_syntax PARAMS ((int));
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#ifdef BFD_ASSEMBLER
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@ -229,6 +230,10 @@ static int intel_syntax = 0; /* 1 for intel syntax, 0 if att syntax */
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static int allow_naked_reg = 0; /* 1 if register prefix % not required */
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static char stackop_size = '\0'; /* Used in 16 bit gcc mode to add an l
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suffix to call, ret, enter, leave, push,
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and pop instructions. */
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/* Interface to relax_segment.
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There are 2 relax states for 386 jump insns: one for conditional &
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one for unconditional jumps. This is because the these two types
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@ -516,14 +521,23 @@ add_prefix (prefix)
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static void
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set_16bit_code_flag (new_16bit_code_flag)
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int new_16bit_code_flag;
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int new_16bit_code_flag;
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{
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flag_16bit_code = new_16bit_code_flag;
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stackop_size = '\0';
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}
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static void
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set_16bit_gcc_code_flag (new_16bit_code_flag)
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int new_16bit_code_flag;
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{
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flag_16bit_code = new_16bit_code_flag;
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stackop_size = new_16bit_code_flag ? 'l' : '\0';
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}
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static void
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set_intel_syntax (syntax_flag)
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int syntax_flag;
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int syntax_flag;
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{
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/* Find out if register prefixing is specified. */
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int ask_naked_reg = 0;
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@ -575,6 +589,7 @@ const pseudo_typeS md_pseudo_table[] =
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{"value", cons, 2},
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{"noopt", s_ignore, 0},
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{"optim", s_ignore, 0},
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{"code16gcc", set_16bit_gcc_code_flag, 1},
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{"code16", set_16bit_code_flag, 1},
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{"code32", set_16bit_code_flag, 0},
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{"intel_syntax", set_intel_syntax, 1},
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@ -1632,6 +1647,10 @@ md_assemble (line)
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else
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abort();
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}
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else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
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{
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i.suffix = stackop_size;
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}
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/* Make still unresolved immediate matches conform to size of immediate
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given in i.suffix. Note: overlap2 cannot be an immediate! */
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@ -3064,13 +3083,18 @@ i386_parse_seg (op_string)
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}
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static int i386_index_check PARAMS((void));
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static int i386_index_check PARAMS((const char *));
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/* Make sure the memory operand we've been dealt is valid.
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Returns 1 on success, 0 on a failure.
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*/
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static int
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i386_index_check ()
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i386_index_check (operand_string)
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const char *operand_string;
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{
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/* Make sure the memory operand we've been dealt is valid. */
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#if INFER_ADDR_PREFIX
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int fudged = 0;
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tryprefix:
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#endif
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if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0) ?
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@ -3093,15 +3117,22 @@ i386_index_check ()
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!= (Reg32|BaseIndex)))))
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{
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#if INFER_ADDR_PREFIX
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if (i.prefix[ADDR_PREFIX] == 0)
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if (i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
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{
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i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
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i.prefixes += 1;
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fudged = 1;
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goto tryprefix;
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}
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else
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#endif
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return 0;
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if (fudged)
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as_bad (_("`%s' is not a valid base/index expression"),
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operand_string);
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else
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as_bad (_("`%s' is not a valid %s bit base/index expression"),
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operand_string,
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flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0) ? "16" : "32");
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return 0;
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}
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return 1;
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}
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@ -3240,12 +3271,8 @@ i386_intel_memory_operand (operand_string)
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}
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}
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if (i386_index_check () == 0)
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{
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as_bad (_("`%s' is not a valid base/index expression"),
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operand_string);
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return 0;
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}
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if (i386_index_check (operand_string) == 0)
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return 0;
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i.mem_operands++;
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return 1;
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@ -3411,8 +3438,6 @@ i386_operand (operand_string)
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if (is_space_char (*op_string))
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++op_string;
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/* Pretend given string starts here. */
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operand_string = op_string;
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if (!is_digit_char (*op_string)
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&& !is_identifier_char (*op_string)
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&& *op_string != '('
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@ -3461,10 +3486,12 @@ i386_operand (operand_string)
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int found_base_index_form;
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/* Start and end of displacement string expression (if found). */
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char *displacement_string_start = NULL;
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char *displacement_string_end = NULL;
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char *displacement_string_start;
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char *displacement_string_end;
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do_memory_reference:
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displacement_string_start = NULL;
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displacement_string_end = NULL;
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if ((i.mem_operands == 1
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&& (current_templates->start->opcode_modifier & IsString) == 0)
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@ -3638,12 +3665,8 @@ i386_operand (operand_string)
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return 1;
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}
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if (i386_index_check () == 0)
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{
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as_bad (_("`%s' is not a valid base/index expression"),
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operand_string);
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return 0;
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}
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if (i386_index_check (operand_string) == 0)
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return 0;
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i.mem_operands++;
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}
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else
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@ -344,17 +344,18 @@ typedef struct
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#define Size16 0x2000 /* needs size prefix if in 32-bit mode */
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#define Size32 0x4000 /* needs size prefix if in 16-bit mode */
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#define IgnoreSize 0x8000 /* instruction ignores operand size prefix */
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#define No_bSuf 0x10000 /* b suffix on instruction illegal */
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#define No_wSuf 0x20000 /* w suffix on instruction illegal */
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#define No_lSuf 0x40000 /* l suffix on instruction illegal */
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#define No_sSuf 0x80000 /* s suffix on instruction illegal */
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#define No_dSuf 0x100000 /* d suffix on instruction illegal */
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#define No_xSuf 0x200000 /* x suffix on instruction illegal */
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#define FWait 0x400000 /* instruction needs FWAIT */
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#define IsString 0x800000 /* quick test for string instructions */
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#define regKludge 0x1000000 /* fake an extra reg operand for clr, imul */
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#define IsPrefix 0x2000000 /* opcode is a prefix */
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#define ImmExt 0x4000000 /* instruction has extension in 8 bit imm */
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#define DefaultSize 0x10000 /* default insn size depends on mode */
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#define No_bSuf 0x20000 /* b suffix on instruction illegal */
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#define No_wSuf 0x40000 /* w suffix on instruction illegal */
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#define No_lSuf 0x80000 /* l suffix on instruction illegal */
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#define No_sSuf 0x100000 /* s suffix on instruction illegal */
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#define No_dSuf 0x200000 /* d suffix on instruction illegal */
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#define No_xSuf 0x400000 /* x suffix on instruction illegal */
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#define FWait 0x800000 /* instruction needs FWAIT */
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#define IsString 0x1000000 /* quick test for string instructions */
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#define regKludge 0x2000000 /* fake an extra reg operand for clr, imul */
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#define IsPrefix 0x4000000 /* opcode is a prefix */
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#define ImmExt 0x8000000 /* instruction has extension in 8 bit imm */
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#define Ugh 0x80000000 /* deprecated fp insn, gets a warning */
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/* operand_types[i] describes the type of operand i. This is made
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@ -443,14 +443,25 @@ instructions is reversed from the Intel syntax.
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@cindex i386 16-bit code
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@cindex 16-bit code, i386
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@cindex real-mode code, i386
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@cindex @code{code16gcc} directive, i386
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@cindex @code{code16} directive, i386
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@cindex @code{code32} directive, i386
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While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code,
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it also supports writing code to run in real mode or in 16-bit protected
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mode code segments. To do this, put a @samp{.code16} directive before
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the assembly language instructions to be run in 16-bit mode. You can
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switch @code{@value{AS}} back to writing normal 32-bit code with the
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@samp{.code32} directive.
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mode code segments. To do this, put a @samp{.code16} or
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@samp{.code16gcc} directive before the assembly language instructions to
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be run in 16-bit mode. You can switch @code{@value{AS}} back to writing
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normal 32-bit code with the @samp{.code32} directive.
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@samp{.code16gcc} provides experimental support for generating 16-bit
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code from gcc, and differs from @samp{.code16} in that @samp{call},
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@samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
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@samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
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default to 32-bit size. This is so that the stack pointer is
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manipulated in the same way over function calls, allowing access to
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function parameters at the same stack offsets as in 32-bit mode.
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@samp{.code16gcc} also automatically adds address size prefixes where
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necessary to use the 32-bit addressing modes that gcc generates.
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The code which @code{@value{AS}} generates in 16-bit mode will not
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necessarily run on a 16-bit pre-80386 processor. To write code that
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@ -1,3 +1,9 @@
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1999-08-04 Alan Modra <alan@spri.levels.unisa.edu.au>
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* i386.h (i386_optab): Add DefaultSize modifier to all insns
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that implicitly modify %esp. #undef d_Suf, x_suf, sld_suf,
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sldx_suf, bwld_Suf, d_FP, x_FP, sld_FP, sldx_FP at end of table.
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Wed Jul 28 02:04:24 1999 Jerry Quinn <jquinn@nortelnetworks.com>
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Jeff Law <law@cygnus.com>
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@ -105,23 +105,23 @@ static const template i386_optab[] = {
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{"movzx", 2, 0x0fb6, X, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} },
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/* push instructions */
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{"push", 1, 0x50, X, wl_Suf|ShortForm, { WordReg, 0, 0 } },
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{"push", 1, 0xff, 6, wl_Suf|Modrm, { WordReg|WordMem, 0, 0 } },
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{"push", 1, 0x6a, X, wl_Suf, { Imm8S, 0, 0} },
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{"push", 1, 0x68, X, wl_Suf, { Imm16|Imm32, 0, 0} },
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{"push", 1, 0x06, X, wl_Suf|Seg2ShortForm, { SReg2, 0, 0 } },
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{"push", 1, 0x0fa0, X, wl_Suf|Seg3ShortForm, { SReg3, 0, 0 } },
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{"push", 1, 0x50, X, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } },
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{"push", 1, 0xff, 6, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } },
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{"push", 1, 0x6a, X, wl_Suf|DefaultSize, { Imm8S, 0, 0} },
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{"push", 1, 0x68, X, wl_Suf|DefaultSize, { Imm16|Imm32, 0, 0} },
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{"push", 1, 0x06, X, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
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{"push", 1, 0x0fa0, X, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
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/* push all */
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{"pusha", 0, 0x60, X, wl_Suf, { 0, 0, 0 } },
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{"pusha", 0, 0x60, X, wl_Suf|DefaultSize, { 0, 0, 0 } },
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/* pop instructions */
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{"pop", 1, 0x58, X, wl_Suf|ShortForm, { WordReg, 0, 0 } },
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{"pop", 1, 0x8f, 0, wl_Suf|Modrm, { WordReg|WordMem, 0, 0 } },
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{"pop", 1, 0x58, X, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } },
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{"pop", 1, 0x8f, 0, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } },
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#define POP_SEG_SHORT 0x07
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{"pop", 1, 0x07, X, wl_Suf|Seg2ShortForm, { SReg2, 0, 0 } },
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{"pop", 1, 0x0fa1, X, wl_Suf|Seg3ShortForm, { SReg3, 0, 0 } },
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{"pop", 1, 0x07, X, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
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{"pop", 1, 0x0fa1, X, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
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/* pop all */
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{"popa", 0, 0x61, X, wl_Suf, { 0, 0, 0 } },
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{"popa", 0, 0x61, X, wl_Suf|DefaultSize, { 0, 0, 0 } },
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/* xchg exchange instructions
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xchg commutes: we allow both operand orders */
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@ -158,8 +158,8 @@ static const template i386_optab[] = {
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{"cmc", 0, 0xf5, X, NoSuf, { 0, 0, 0} },
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{"lahf", 0, 0x9f, X, NoSuf, { 0, 0, 0} },
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{"sahf", 0, 0x9e, X, NoSuf, { 0, 0, 0} },
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{"pushf", 0, 0x9c, X, wl_Suf, { 0, 0, 0} },
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{"popf", 0, 0x9d, X, wl_Suf, { 0, 0, 0} },
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{"pushf", 0, 0x9c, X, wl_Suf|DefaultSize, { 0, 0, 0} },
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{"popf", 0, 0x9d, X, wl_Suf|DefaultSize, { 0, 0, 0} },
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{"stc", 0, 0xf9, X, NoSuf, { 0, 0, 0} },
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{"std", 0, 0xfd, X, NoSuf, { 0, 0, 0} },
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{"sti", 0, 0xfb, X, NoSuf, { 0, 0, 0} },
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@ -311,12 +311,12 @@ static const template i386_optab[] = {
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{"sar", 1, 0xd0, 7, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
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/* control transfer instructions */
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{"call", 1, 0xe8, X, wl_Suf|JumpDword, { Disp16|Disp32, 0, 0} },
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{"call", 1, 0xff, 2, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} },
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{"call", 1, 0xe8, X, wl_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} },
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{"call", 1, 0xff, 2, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem|JumpAbsolute, 0, 0} },
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/* Intel Syntax */
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{"call", 2, 0x9a, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
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{"lcall", 2, 0x9a, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
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{"lcall", 1, 0xff, 3, wl_Suf|Modrm, { WordMem, 0, 0} },
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{"call", 2, 0x9a, X, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
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{"lcall", 2, 0x9a, X, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
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{"lcall", 1, 0xff, 3, wl_Suf|Modrm|DefaultSize, { WordMem, 0, 0} },
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#define JUMP_PC_RELATIVE 0xeb
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{"jmp", 1, 0xeb, X, NoSuf|Jump, { Disp, 0, 0} },
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@ -327,12 +327,12 @@ static const template i386_optab[] = {
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{"ljmp", 2, 0xea, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
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{"ljmp", 1, 0xff, 5, wl_Suf|Modrm, { WordMem, 0, 0} },
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{"ret", 0, 0xc3, X, wl_Suf, { 0, 0, 0} },
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{"ret", 1, 0xc2, X, wl_Suf, { Imm16, 0, 0} },
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{"lret", 0, 0xcb, X, wl_Suf, { 0, 0, 0} },
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{"lret", 1, 0xca, X, wl_Suf, { Imm16, 0, 0} },
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{"enter", 2, 0xc8, X, wl_Suf, { Imm16, Imm8, 0} },
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{"leave", 0, 0xc9, X, wl_Suf, { 0, 0, 0} },
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{"ret", 0, 0xc3, X, wl_Suf|DefaultSize, { 0, 0, 0} },
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{"ret", 1, 0xc2, X, wl_Suf|DefaultSize, { Imm16, 0, 0} },
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{"lret", 0, 0xcb, X, wl_Suf|DefaultSize, { 0, 0, 0} },
|
||||
{"lret", 1, 0xca, X, wl_Suf|DefaultSize, { Imm16, 0, 0} },
|
||||
{"enter", 2, 0xc8, X, wl_Suf|DefaultSize, { Imm16, Imm8, 0} },
|
||||
{"leave", 0, 0xc9, X, wl_Suf|DefaultSize, { 0, 0, 0} },
|
||||
|
||||
/* conditional jumps */
|
||||
{"jo", 1, 0x70, X, NoSuf|Jump, { Disp, 0, 0} },
|
||||
|
|
@ -1035,14 +1035,23 @@ static const template i386_optab[] = {
|
|||
#undef b_Suf
|
||||
#undef w_Suf
|
||||
#undef l_Suf
|
||||
#undef d_Suf
|
||||
#undef x_Suf
|
||||
#undef bw_Suf
|
||||
#undef bl_Suf
|
||||
#undef wl_Suf
|
||||
#undef sl_Suf
|
||||
#undef sld_Suf
|
||||
#undef sldx_Suf
|
||||
#undef bwl_Suf
|
||||
#undef bwld_Suf
|
||||
#undef FP
|
||||
#undef l_FP
|
||||
#undef d_FP
|
||||
#undef x_FP
|
||||
#undef sl_FP
|
||||
#undef sld_FP
|
||||
#undef sldx_FP
|
||||
|
||||
#define MAX_MNEM_SIZE 16 /* for parsing insn mnemonics from input */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue